index
NameDescriptionIdle
core/platform/alphaPlatform-specific files for the Cryptech Alpha board5 weeks
wikiCryptech developers pseudo-wiki source, see https://wiki.cryptech.is/7 weeks
user/sra/build-toolsUtilities for working with cryptech repository tree7 weeks
releng/alphaRelease engineering for Cryptech Alpha board7 weeks
gitolite-adminGitolite administration repository. Sysadmins only.7 weeks
user/shatov/ice40mkmUnnamed repository; edit this file 'description' to name the repository.3 months
user/shatov/alpha_rev04Unnamed repository; edit this file 'description' to name the repository.4 months
core/platform/commonSupport code used to build projects, not tied to a particular platform4 months
user/shatov/ecdsa_fpga_modelReference model written to help debug Verilog code4 months
user/shatov/modexpng_fpga_modelMath model of ModExpNG IP core4 months
sw/stm32Cryptech HSM on STM-32 ARM processor4 months
core/comm/fmcVerilog implementation of Flexible Memory Controller interface used to connect F...4 months
core/libCommon modules instantiated by other cores (math operations, etc)4 months
sw/libhalCryptech libhal: crypto software, HSM management, RPC5 months
core/hash/sha3Verilog implementation sponge construction defined in the SHA-3 hash standard6 months
sw/pkcs11PKCS #11 library for Cryptech on top of libhal RPC15 months
core/hash/sha1Verilog implementation of the SHA-1 cryptographic hash function19 months
core/util/keywrapAES KEY WRAP as defined in RFC 339419 months
core/math/modexpng"Next-generation" modular exponentiation using specialized DSP slices present in...20 months
sw/thirdparty/libtfmCryptech build of Tom's Fast Math bignum library21 months
user/shatov/modexpng"Next-generation" modular exponentiation using the specialized DSP slices presen...22 months
user/ln5/stm32-avalanche-noiseSTM32 avalanche noise entropy source22 months
core/cipher/aesVerilog implementation of the symmetric block cipher AES (Advanced Encryption St...2 years
user/js/fpga_mkmFPGA-based active Master Key Memory (MKM)3 years
core/cipher/chachaVerilog 2001 implementation of the ChaCha stream cipher3 years
user/js/keywrapAES KEY WRAP as defined in RFC 33943 years
user/js/vndecorrelatorVerilog implementation of von Neumann decorrelator3 years
core/rng/rosc_entropyDigital entropy source based on on jitter between multiple, digital ring oscilla...3 years
core/hash/sha256Verilog implementation of the SHA-256 cryptographic hash function3 years
user/shatov/curve25519_fpga_modelReference model written to help debug Verilog code3 years
core/pkey/ed25519Unnamed repository; edit this file 'description' to name the repository.3 years
core/pkey/ecdsa384Scalar base point multiplier for ECDSA curve P-3843 years
core/pkey/ecdsa256Scalar base point multiplier for ECDSA curve P-2563 years
core/math/modexpa7Modular exponentiation using the Artix-7 FPGA3 years
core/math/ecdsalibCode common to the ecdsa256 and ecdsa384 cores3 years
core/platform/novenaPlatform-specific files for the Novena PVT13 years
core/hash/sha512Verilog implementation of the SHA-512 hash function3 years
core/math/curve25519libUnnamed repository; edit this file 'description' to name the repository.3 years
core/rng/avalanche_entropyEntropy provider core for an external avalanche noise based entropy source3 years
user/js/mkmifMaster Key Memory Interface3 years
core/rng/trngTrue Random Number Generator core implemented in Verilog3 years
core/cipher/aes_speed(Old) Verilog implementation of the symmetric block cipher AES (Advanced Encrypt...3 years
user/sra/aes-keywrapPrototype implementation of AES-Keywrap3 years
user/js/toggleThis repo contains a simple deign that toggles an ouput pin3 years
user/ft/alpha_to_kicadWork-in-progress repository with output of altium2kicad conversion4 years
user/paul/hashsig-naiveReference implementation of LMS Hash Based Signature Scheme4 years
hardwareSTM32 firmware for Cryptech Alpha board4 years
core/pkey/ecdhp384Scalar point multiplier for ECDSA curve P-3844 years
core/pkey/ecdhp256Scalar point multiplier for ECDSA curve P-2564 years
user/shatov/ecdh_fpga_modelReference model written to help debug Verilog code4 years