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BranchCommit messageAuthorAge
cleanup(1) Cleanup of top an core code with no functional changes. The code is now m...Joachim Strömbergson5 years
master(1) Removed reset input port from qr module, qr module instances and qr modul...Joachim Strömbergson3 years
timing_fixDebugged pipeline register and state update. All test cases ok.Joachim Strömbergson3 years
 
 
AgeCommit messageAuthor
2019-02-08(1) Removed reset input port from qr module, qr module instances and qr modul...HEADmasterJoachim Strömbergson
2019-02-07Change reset to asynch assert. This matches comment. It also matches what is ...Joachim Strömbergson
2018-10-23Hardening the API to block writes to contol signals when core is performing o...Joachim Strömbergson
2018-10-16Adding width specification, fixed order and other nits as part of ceckning th...Joachim Strömbergson
2018-08-30Adding two more pipeline registers in the qr module. Added two more wait cycles.Joachim Strömbergson
2018-08-23Debugged pipeline register and state update. All test cases ok.timing_fixJoachim Strömbergson
2018-08-23Added missing define.Joachim Strömbergson
2018-08-23(1) Adding pipeline register update code and a set of pipeline registers. Reg...Joachim Strömbergson
2018-08-23(1) Updated qr interface to include clock and reset needed for internal pipel...Joachim Strömbergson
2016-12-28(1) Cleanup of top an core code with no functional changes. The code is now m...cleanupJoachim Strömbergson
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