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BranchCommit messageAuthorAge
fixModified the test program to verify that changes in Verilog do work.Pavel V. Shatov (Meister)6 years
master * Rewritten from scratch, uses the same hardware architecture as the Ed25519Pavel V. Shatov (Meister)5 years
test_dpa_fixFixed copyright notices.Pavel V. Shatov (Meister)3 years
 
 
AgeCommit messageAuthor
2018-12-19 * Rewritten from scratch, uses the same hardware architecture as the Ed25519HEADmasterPavel V. Shatov (Meister)
2018-09-06Replicated certain FSM-related signals for better placement and routing.Pavel V. Shatov (Meister)
2018-09-06Turned ROMs into distributed memories, otherwise synthesizer was combining themPavel V. Shatov (Meister)
2018-04-17Modified the test program to verify that changes in Verilog do work.fixPavel V. Shatov (Meister)
2018-04-01Added more test vectors to trigger the virtually never taken path in the curvePavel V. Shatov (Meister)
2018-04-01Fixed coordinates of the internally stored point H = 2 * G.Pavel V. Shatov (Meister)
2018-04-01Minor cleanup.Pavel V. Shatov (Meister)
2017-03-07Promote to a repository in the core tree.Rob Austein
2017-02-12Various clean-upsPavel V. Shatov (Meister)
2016-12-04Added README.md with core description, API details, etcPavel V. Shatov (Meister)
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