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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2018-04-01 23:37:08 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2018-04-01 23:37:08 +0300
commitf9705ee9ca9dbef18dfa2a4264ac67dad427edd6 (patch)
tree5edf639ee294fe2421ac420257a4a54582f97b58
parent0aafcece449b2ee806b9c08ae10fb7fb498d893d (diff)
Fixed coordinates of the internally stored point H = 2 * G.
-rw-r--r--rtl/curve/rom/brom_p256_h_x.v38
-rw-r--r--rtl/curve/rom/brom_p256_h_y.v40
2 files changed, 39 insertions, 39 deletions
diff --git a/rtl/curve/rom/brom_p256_h_x.v b/rtl/curve/rom/brom_p256_h_x.v
index 554d346..f426475 100644
--- a/rtl/curve/rom/brom_p256_h_x.v
+++ b/rtl/curve/rom/brom_p256_h_x.v
@@ -33,36 +33,36 @@
`timescale 1ns / 1ps
module brom_p256_h_x
- (
- input wire clk,
- input wire [ 3-1:0] b_addr,
- output wire [32-1:0] b_out
- );
+ (
+ input wire clk,
+ input wire [ 3-1:0] b_addr,
+ output wire [32-1:0] b_out
+ );
//
// Output Registers
//
- reg [31:0] bram_reg_b;
+ reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
- //
- always @(posedge clk)
- //
- case (b_addr)
- 3'b000: bram_reg_b <= 32'h4ece7ad0;
- 3'b001: bram_reg_b <= 32'h16bd8d74;
- 3'b010: bram_reg_b <= 32'ha42998be;
- 3'b011: bram_reg_b <= 32'h11f904fe;
- 3'b100: bram_reg_b <= 32'h38b77e1b;
- 3'b101: bram_reg_b <= 32'h0e863235;
- 3'b110: bram_reg_b <= 32'h3da77b71;
- 3'b111: bram_reg_b <= 32'h29d05c19;
- endcase
+ //
+ always @(posedge clk)
+ //
+ case (b_addr)
+ 3'b000: bram_reg_b <= 32'h47669978;
+ 3'b001: bram_reg_b <= 32'ha60b48fc;
+ 3'b010: bram_reg_b <= 32'h77f21b35;
+ 3'b011: bram_reg_b <= 32'hc08969e2;
+ 3'b100: bram_reg_b <= 32'h04b51ac3;
+ 3'b101: bram_reg_b <= 32'h8a523803;
+ 3'b110: bram_reg_b <= 32'h8d034f7e;
+ 3'b111: bram_reg_b <= 32'h7cf27b18;
+ endcase
endmodule
diff --git a/rtl/curve/rom/brom_p256_h_y.v b/rtl/curve/rom/brom_p256_h_y.v
index 6b5b8d9..c75d0da 100644
--- a/rtl/curve/rom/brom_p256_h_y.v
+++ b/rtl/curve/rom/brom_p256_h_y.v
@@ -33,36 +33,36 @@
`timescale 1ns / 1ps
module brom_p256_h_y
- (
- input wire clk,
- input wire [ 3-1:0] b_addr,
- output wire [32-1:0] b_out
- );
+ (
+ input wire clk,
+ input wire [ 3-1:0] b_addr,
+ output wire [32-1:0] b_out
+ );
//
// Output Registers
//
- reg [31:0] bram_reg_b;
+ reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
- //
- always @(posedge clk)
- //
- case (b_addr)
- 3'b000: bram_reg_b <= 32'hc840ae07;
- 3'b001: bram_reg_b <= 32'h3449bf97;
- 3'b010: bram_reg_b <= 32'h94cea131;
- 3'b011: bram_reg_b <= 32'hd431cca9;
- 3'b100: bram_reg_b <= 32'h83f061e9;
- 3'b101: bram_reg_b <= 32'h711814b5;
- 3'b110: bram_reg_b <= 32'h01e58065;
- 3'b111: bram_reg_b <= 32'hb01cbd1c;
- endcase
-
+ //
+ always @(posedge clk)
+ //
+ case (b_addr)
+ 3'b000: bram_reg_b <= 32'h227873d1;
+ 3'b001: bram_reg_b <= 32'h9e04b79d;
+ 3'b010: bram_reg_b <= 32'h3ce98229;
+ 3'b011: bram_reg_b <= 32'hba7dade6;
+ 3'b100: bram_reg_b <= 32'h9f7430db;
+ 3'b101: bram_reg_b <= 32'h293d9ac6;
+ 3'b110: bram_reg_b <= 32'hdb8ed040;
+ 3'b111: bram_reg_b <= 32'h07775510;
+ endcase
+
endmodule