| Branch | Commit message | Author | Age | |
|---|---|---|---|---|
| master | Tiny cleanup. | Pavel V. Shatov (Meister) | 5 years | |
| Age | Commit message | Author | ||
| 2018-12-19 | Tiny cleanup.HEADmaster | Pavel V. Shatov (Meister) | ||
| 2018-11-09 | Added randomized test vector. | Pavel V. Shatov (Meister) | ||
| 2018-10-15 | Ed25519 microcode parser. Verilog Ed25519 core is microsequenced, it contains a | Pavel V. Shatov (Meister) | ||
| 2018-10-15 | Removed move2(), because Verilog can only move one operand a time. Added magic | Pavel V. Shatov (Meister) | ||
| 2018-10-15 | Tiny cleanup. | Pavel V. Shatov (Meister) | ||
| 2018-10-15 | Reworked Ed25519-specific microcode, added magic markers to allow automatic | Pavel V. Shatov (Meister) | ||
| 2018-09-24 | Added readme file (unfinished, will update after Verilog for Ed25519 is done) | Pavel V. Shatov (Meister) | ||
| 2018-09-24 | Ignore make output | Pavel V. Shatov (Meister) | ||
| 2018-09-24 | Added Makefile | Pavel V. Shatov (Meister) | ||
| 2018-09-24 | Ed25519 tester | Pavel V. Shatov (Meister) | ||
| [...] | ||||
| Clone | ||||
| https://git.cryptech.is/user/shatov/curve25519_fpga_model | ||||
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index : user/shatov/curve25519_fpga_model | |
| Reference model written to help debug Verilog code | git repositories |
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