diff options
| author | Joachim StroĢmbergson <joachim@secworks.se> | 2015-01-31 09:03:06 +0100 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2015-01-31 09:03:06 +0100 |
| commit | a68ffdd6c327bcc5d0c0524c4dacd6ceeaf839d7 (patch) | |
| tree | 2fc4876ab32718ce45943e960fbd1f8be16eb1d5 /rtl/src | |
| parent | 785767f35cdee9aca04969b97734e05351bb084d (diff) | |
Adding all main hw source files and constraints.
Diffstat (limited to 'rtl/src')
70 files changed, 5232 insertions, 0 deletions
diff --git a/rtl/src/ipcore/_xmsgs/cg.xmsgs b/rtl/src/ipcore/_xmsgs/cg.xmsgs new file mode 100644 index 0000000..985e6e3 --- /dev/null +++ b/rtl/src/ipcore/_xmsgs/cg.xmsgs @@ -0,0 +1,27 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages> +<msg type="info" file="sim" num="172" delta="old" >Generating IP...
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Component clk_wiz_v3_6 does not have a valid model name for Verilog synthesis</arg>
+</msg>
+ +<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
+</msg>
+ +<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
+</msg>
+ +</messages> +
diff --git a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..2ccce38 --- /dev/null +++ b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated -->
+<!-- by the Xilinx ISE software. Any direct editing or -->
+<!-- changes made to this file may result in unpredictable -->
+<!-- behavior or data corruption. It is strongly advised that -->
+<!-- users do not edit the contents of this file. -->
+<!-- -->
+<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "E:/__DNSSEC/novena_baseline/src/ipcore/clkmgr_dcm.v" into library work</arg>
+</msg>
+
+</messages>
+
diff --git a/rtl/src/ipcore/clkmgr_dcm.asy b/rtl/src/ipcore/clkmgr_dcm.asy new file mode 100644 index 0000000..016d02a --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm.asy @@ -0,0 +1,25 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 clkmgr_dcm +RECTANGLE Normal 32 32 576 1088 +LINE Normal 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName clk_in1 +PINATTR Polarity IN +LINE Normal 0 432 32 432 +PIN 0 432 LEFT 36 +PINATTR PinName reset +PINATTR Polarity IN +LINE Normal 608 80 576 80 +PIN 608 80 RIGHT 36 +PINATTR PinName clk_out1 +PINATTR Polarity OUT +LINE Normal 608 880 576 880 +PIN 608 880 RIGHT 36 +PINATTR PinName input_clk_stopped +PINATTR Polarity OUT +LINE Normal 608 1008 576 1008 +PIN 608 1008 RIGHT 36 +PINATTR PinName clk_valid +PINATTR Polarity OUT +
diff --git a/rtl/src/ipcore/clkmgr_dcm.gise b/rtl/src/ipcore/clkmgr_dcm.gise new file mode 100644 index 0000000..ae9097a --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm.gise @@ -0,0 +1,31 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="../../../../src/ipcore/clkmgr_dcm.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="clkmgr_dcm.asy" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="clkmgr_dcm.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/rtl/src/ipcore/clkmgr_dcm.ncf b/rtl/src/ipcore/clkmgr_dcm.ncf new file mode 100644 index 0000000..0e5eb73 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm.ncf @@ -0,0 +1,60 @@ +# file: clkmgr_dcm.ucf
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints
+PIN "RESET" TIG;
+
+
diff --git a/rtl/src/ipcore/clkmgr_dcm.sym b/rtl/src/ipcore/clkmgr_dcm.sym new file mode 100644 index 0000000..7d178b8 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm.sym @@ -0,0 +1,24 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="clkmgr_dcm">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2015-1-28T21:56:19</timestamp>
+ <pin polarity="Input" x="0" y="80" name="clk_in1" />
+ <pin polarity="Input" x="0" y="432" name="reset" />
+ <pin polarity="Output" x="608" y="80" name="clk_out1" />
+ <pin polarity="Output" x="608" y="880" name="input_clk_stopped" />
+ <pin polarity="Output" x="608" y="1008" name="clk_valid" />
+ <graph>
+ <text style="fontsize:40;fontname:Arial" x="32" y="32">clkmgr_dcm</text>
+ <rect width="544" x="32" y="32" height="1056" />
+ <line x2="32" y1="80" y2="80" x1="0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin clk_in1" />
+ <line x2="32" y1="432" y2="432" x1="0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin reset" />
+ <line x2="576" y1="80" y2="80" x1="608" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="80" type="pin clk_out1" />
+ <line x2="576" y1="880" y2="880" x1="608" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="880" type="pin input_clk_stopped" />
+ <line x2="576" y1="1008" y2="1008" x1="608" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="1008" type="pin clk_valid" />
+ </graph>
+</symbol>
diff --git a/rtl/src/ipcore/clkmgr_dcm.ucf b/rtl/src/ipcore/clkmgr_dcm.ucf new file mode 100644 index 0000000..658fdb4 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm.ucf @@ -0,0 +1,59 @@ +# file: clkmgr_dcm.ucf
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints
+PIN "RESET" TIG;
+
diff --git a/rtl/src/ipcore/clkmgr_dcm.v b/rtl/src/ipcore/clkmgr_dcm.v new file mode 100644 index 0000000..b719b86 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm.v @@ -0,0 +1,151 @@ +// file: clkmgr_dcm.v
+//
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// "Output Output Phase Duty Pk-to-Pk Phase"
+// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
+//----------------------------------------------------------------------------
+// CLK_OUT1____80.000______0.000______50.0______450.000____150.000
+//
+//----------------------------------------------------------------------------
+// "Input Clock Freq (MHz) Input Jitter (UI)"
+//----------------------------------------------------------------------------
+// __primary______________50____________0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "clkmgr_dcm,clk_wiz_v3_6,{component_name=clkmgr_dcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=true,use_status=false,use_freeze=false,use_clk_valid=true,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
+module clkmgr_dcm
+ (// Clock in ports
+ input CLK_IN1,
+ // Clock out ports
+ output CLK_OUT1,
+ // Status and control signals
+ input RESET,
+ output INPUT_CLK_STOPPED,
+ output CLK_VALID
+ );
+
+ // Input buffering
+ //------------------------------------
+ assign clkin1 = CLK_IN1;
+
+
+ // Clocking primitive
+ //------------------------------------
+
+ // Instantiation of the DCM primitive
+ // * Unused inputs are tied off
+ // * Unused outputs are labeled unused
+ wire psdone_unused;
+ wire locked_int;
+ wire [7:0] status_int;
+ wire clkfb;
+ wire clk0;
+ wire clkfx;
+
+ DCM_SP
+ #(.CLKDV_DIVIDE (2.000),
+ .CLKFX_DIVIDE (5),
+ .CLKFX_MULTIPLY (8),
+ .CLKIN_DIVIDE_BY_2 ("FALSE"),
+ .CLKIN_PERIOD (20.0),
+ .CLKOUT_PHASE_SHIFT ("NONE"),
+ .CLK_FEEDBACK ("1X"),
+ .DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
+ .PHASE_SHIFT (0),
+ .STARTUP_WAIT ("FALSE"))
+ dcm_sp_inst
+ // Input clock
+ (.CLKIN (clkin1),
+ .CLKFB (clkfb),
+ // Output clocks
+ .CLK0 (clk0),
+ .CLK90 (),
+ .CLK180 (),
+ .CLK270 (),
+ .CLK2X (),
+ .CLK2X180 (),
+ .CLKFX (clkfx),
+ .CLKFX180 (),
+ .CLKDV (),
+ // Ports for dynamic phase shift
+ .PSCLK (1'b0),
+ .PSEN (1'b0),
+ .PSINCDEC (1'b0),
+ .PSDONE (),
+ // Other control and status signals
+ .LOCKED (locked_int),
+ .STATUS (status_int),
+
+ .RST (RESET),
+ // Unused pin- tie low
+ .DSSEN (1'b0));
+
+ assign INPUT_CLK_STOPPED = status_int[1];
+ assign CLK_VALID = ( ( locked_int == 1'b 1 ) && ( status_int[2:1] == 2'b 0 ) );
+
+ // Output buffering
+ //-----------------------------------
+ BUFG clkf_buf
+ (.O (clkfb),
+ .I (clk0));
+
+ BUFG clkout1_buf
+ (.O (CLK_OUT1),
+ .I (clkfx));
+
+
+
+
+endmodule
diff --git a/rtl/src/ipcore/clkmgr_dcm.veo b/rtl/src/ipcore/clkmgr_dcm.veo new file mode 100644 index 0000000..fa19d52 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm.veo @@ -0,0 +1,79 @@ +//
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// "Output Output Phase Duty Pk-to-Pk Phase"
+// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
+//----------------------------------------------------------------------------
+// CLK_OUT1____80.000______0.000______50.0______450.000____150.000
+//
+//----------------------------------------------------------------------------
+// "Input Clock Freq (MHz) Input Jitter (UI)"
+//----------------------------------------------------------------------------
+// __primary______________50____________0.010
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+
+ clkmgr_dcm instance_name
+ (// Clock in ports
+ .CLK_IN1(CLK_IN1), // IN
+ // Clock out ports
+ .CLK_OUT1(CLK_OUT1), // OUT
+ // Status and control signals
+ .RESET(RESET),// IN
+ .INPUT_CLK_STOPPED(INPUT_CLK_STOPPED), // OUT
+ .CLK_VALID(CLK_VALID)); // OUT
+// INST_TAG_END ------ End INSTANTIATION Template ---------
diff --git a/rtl/src/ipcore/clkmgr_dcm.xco b/rtl/src/ipcore/clkmgr_dcm.xco new file mode 100644 index 0000000..06b89ec --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm.xco @@ -0,0 +1,269 @@ +##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Wed Jan 28 21:56:02 2015
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:clk_wiz:3.6
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
+# END Select
+# BEGIN Parameters
+CSET calc_done=DONE
+CSET clk_in_sel_port=CLK_IN_SEL
+CSET clk_out1_port=CLK_OUT1
+CSET clk_out1_use_fine_ps_gui=false
+CSET clk_out2_port=CLK_OUT2
+CSET clk_out2_use_fine_ps_gui=false
+CSET clk_out3_port=CLK_OUT3
+CSET clk_out3_use_fine_ps_gui=false
+CSET clk_out4_port=CLK_OUT4
+CSET clk_out4_use_fine_ps_gui=false
+CSET clk_out5_port=CLK_OUT5
+CSET clk_out5_use_fine_ps_gui=false
+CSET clk_out6_port=CLK_OUT6
+CSET clk_out6_use_fine_ps_gui=false
+CSET clk_out7_port=CLK_OUT7
+CSET clk_out7_use_fine_ps_gui=false
+CSET clk_valid_port=CLK_VALID
+CSET clkfb_in_n_port=CLKFB_IN_N
+CSET clkfb_in_p_port=CLKFB_IN_P
+CSET clkfb_in_port=CLKFB_IN
+CSET clkfb_in_signaling=SINGLE
+CSET clkfb_out_n_port=CLKFB_OUT_N
+CSET clkfb_out_p_port=CLKFB_OUT_P
+CSET clkfb_out_port=CLKFB_OUT
+CSET clkfb_stopped_port=CLKFB_STOPPED
+CSET clkin1_jitter_ps=200.0
+CSET clkin1_ui_jitter=0.010
+CSET clkin2_jitter_ps=100.0
+CSET clkin2_ui_jitter=0.010
+CSET clkout1_drives=BUFG
+CSET clkout1_requested_duty_cycle=50.0
+CSET clkout1_requested_out_freq=80
+CSET clkout1_requested_phase=0.000
+CSET clkout2_drives=BUFG
+CSET clkout2_requested_duty_cycle=50.0
+CSET clkout2_requested_out_freq=50
+CSET clkout2_requested_phase=0
+CSET clkout2_used=false
+CSET clkout3_drives=BUFG
+CSET clkout3_requested_duty_cycle=50.0
+CSET clkout3_requested_out_freq=100.000
+CSET clkout3_requested_phase=0.000
+CSET clkout3_used=false
+CSET clkout4_drives=BUFG
+CSET clkout4_requested_duty_cycle=50.0
+CSET clkout4_requested_out_freq=100.000
+CSET clkout4_requested_phase=0.000
+CSET clkout4_used=false
+CSET clkout5_drives=BUFG
+CSET clkout5_requested_duty_cycle=50.0
+CSET clkout5_requested_out_freq=100.000
+CSET clkout5_requested_phase=0.000
+CSET clkout5_used=false
+CSET clkout6_drives=BUFG
+CSET clkout6_requested_duty_cycle=50.0
+CSET clkout6_requested_out_freq=100.000
+CSET clkout6_requested_phase=0.000
+CSET clkout6_used=false
+CSET clkout7_drives=BUFG
+CSET clkout7_requested_duty_cycle=50.0
+CSET clkout7_requested_out_freq=100.000
+CSET clkout7_requested_phase=0.000
+CSET clkout7_used=false
+CSET clock_mgr_type=MANUAL
+CSET component_name=clkmgr_dcm
+CSET daddr_port=DADDR
+CSET dclk_port=DCLK
+CSET dcm_clk_feedback=1X
+CSET dcm_clk_out1_port=CLKFX
+CSET dcm_clk_out2_port=CLK0
+CSET dcm_clk_out3_port=CLK0
+CSET dcm_clk_out4_port=CLK0
+CSET dcm_clk_out5_port=CLK0
+CSET dcm_clk_out6_port=CLK0
+CSET dcm_clkdv_divide=2.0
+CSET dcm_clkfx_divide=5
+CSET dcm_clkfx_multiply=8
+CSET dcm_clkgen_clk_out1_port=CLKFX
+CSET dcm_clkgen_clk_out2_port=CLKFX
+CSET dcm_clkgen_clk_out3_port=CLKFX
+CSET dcm_clkgen_clkfx_divide=1
+CSET dcm_clkgen_clkfx_md_max=0.000
+CSET dcm_clkgen_clkfx_multiply=4
+CSET dcm_clkgen_clkfxdv_divide=2
+CSET dcm_clkgen_clkin_period=10.000
+CSET dcm_clkgen_notes=None
+CSET dcm_clkgen_spread_spectrum=NONE
+CSET dcm_clkgen_startup_wait=false
+CSET dcm_clkin_divide_by_2=false
+CSET dcm_clkin_period=20.000
+CSET dcm_clkout_phase_shift=NONE
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
+CSET dcm_notes=None
+CSET dcm_phase_shift=0
+CSET dcm_pll_cascade=NONE
+CSET dcm_startup_wait=false
+CSET den_port=DEN
+CSET din_port=DIN
+CSET dout_port=DOUT
+CSET drdy_port=DRDY
+CSET dwe_port=DWE
+CSET feedback_source=FDBK_AUTO
+CSET in_freq_units=Units_MHz
+CSET in_jitter_units=Units_UI
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED
+CSET jitter_options=UI
+CSET jitter_sel=No_Jitter
+CSET locked_port=LOCKED
+CSET mmcm_bandwidth=OPTIMIZED
+CSET mmcm_clkfbout_mult_f=4.000
+CSET mmcm_clkfbout_phase=0.000
+CSET mmcm_clkfbout_use_fine_ps=false
+CSET mmcm_clkin1_period=10.000
+CSET mmcm_clkin2_period=10.000
+CSET mmcm_clkout0_divide_f=4.000
+CSET mmcm_clkout0_duty_cycle=0.500
+CSET mmcm_clkout0_phase=0.000
+CSET mmcm_clkout0_use_fine_ps=false
+CSET mmcm_clkout1_divide=1
+CSET mmcm_clkout1_duty_cycle=0.500
+CSET mmcm_clkout1_phase=0.000
+CSET mmcm_clkout1_use_fine_ps=false
+CSET mmcm_clkout2_divide=1
+CSET mmcm_clkout2_duty_cycle=0.500
+CSET mmcm_clkout2_phase=0.000
+CSET mmcm_clkout2_use_fine_ps=false
+CSET mmcm_clkout3_divide=1
+CSET mmcm_clkout3_duty_cycle=0.500
+CSET mmcm_clkout3_phase=0.000
+CSET mmcm_clkout3_use_fine_ps=false
+CSET mmcm_clkout4_cascade=false
+CSET mmcm_clkout4_divide=1
+CSET mmcm_clkout4_duty_cycle=0.500
+CSET mmcm_clkout4_phase=0.000
+CSET mmcm_clkout4_use_fine_ps=false
+CSET mmcm_clkout5_divide=1
+CSET mmcm_clkout5_duty_cycle=0.500
+CSET mmcm_clkout5_phase=0.000
+CSET mmcm_clkout5_use_fine_ps=false
+CSET mmcm_clkout6_divide=1
+CSET mmcm_clkout6_duty_cycle=0.500
+CSET mmcm_clkout6_phase=0.000
+CSET mmcm_clkout6_use_fine_ps=false
+CSET mmcm_clock_hold=false
+CSET mmcm_compensation=ZHOLD
+CSET mmcm_divclk_divide=1
+CSET mmcm_notes=None
+CSET mmcm_ref_jitter1=0.010
+CSET mmcm_ref_jitter2=0.010
+CSET mmcm_startup_wait=false
+CSET num_out_clks=1
+CSET override_dcm=false
+CSET override_dcm_clkgen=false
+CSET override_mmcm=false
+CSET override_pll=false
+CSET platform=nt
+CSET pll_bandwidth=OPTIMIZED
+CSET pll_clk_feedback=CLKFBOUT
+CSET pll_clkfbout_mult=8
+CSET pll_clkfbout_phase=0.000
+CSET pll_clkin_period=20.0
+CSET pll_clkout0_divide=2
+CSET pll_clkout0_duty_cycle=0.500
+CSET pll_clkout0_phase=0.000
+CSET pll_clkout1_divide=10
+CSET pll_clkout1_duty_cycle=0.500
+CSET pll_clkout1_phase=0.000
+CSET pll_clkout2_divide=1
+CSET pll_clkout2_duty_cycle=0.500
+CSET pll_clkout2_phase=0.000
+CSET pll_clkout3_divide=1
+CSET pll_clkout3_duty_cycle=0.500
+CSET pll_clkout3_phase=0.000
+CSET pll_clkout4_divide=1
+CSET pll_clkout4_duty_cycle=0.500
+CSET pll_clkout4_phase=0.000
+CSET pll_clkout5_divide=1
+CSET pll_clkout5_duty_cycle=0.500
+CSET pll_clkout5_phase=0.000
+CSET pll_compensation=SYSTEM_SYNCHRONOUS
+CSET pll_divclk_divide=1
+CSET pll_notes=None
+CSET pll_ref_jitter=0.010
+CSET power_down_port=POWER_DOWN
+CSET prim_in_freq=50
+CSET prim_in_jitter=0.010
+CSET prim_source=No_buffer
+CSET primary_port=CLK_IN1
+CSET primitive=MMCM
+CSET primtype_sel=DCM_SP
+CSET psclk_port=PSCLK
+CSET psdone_port=PSDONE
+CSET psen_port=PSEN
+CSET psincdec_port=PSINCDEC
+CSET relative_inclk=REL_PRIMARY
+CSET reset_port=RESET
+CSET secondary_in_freq=100.000
+CSET secondary_in_jitter=0.010
+CSET secondary_port=CLK_IN2
+CSET secondary_source=Single_ended_clock_capable_pin
+CSET ss_mod_freq=250
+CSET ss_mode=CENTER_HIGH
+CSET status_port=STATUS
+CSET summary_strings=empty
+CSET use_clk_valid=true
+CSET use_clkfb_stopped=false
+CSET use_dyn_phase_shift=false
+CSET use_dyn_reconfig=false
+CSET use_freeze=false
+CSET use_freq_synth=true
+CSET use_inclk_stopped=true
+CSET use_inclk_switchover=false
+CSET use_locked=false
+CSET use_max_i_jitter=false
+CSET use_min_o_jitter=false
+CSET use_min_power=false
+CSET use_phase_alignment=true
+CSET use_power_down=false
+CSET use_reset=true
+CSET use_spread_spectrum=false
+CSET use_spread_spectrum_1=false
+CSET use_status=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-05-10T12:44:55Z
+# END Extra information
+GENERATE
+# CRC: 9fa2003b
diff --git a/rtl/src/ipcore/clkmgr_dcm.xdc b/rtl/src/ipcore/clkmgr_dcm.xdc new file mode 100644 index 0000000..9ecc102 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm.xdc @@ -0,0 +1,67 @@ +# file: clkmgr_dcm.xdc
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1]
+set_propagated_clock CLK_IN1
+set_input_jitter CLK_IN1 0.2
+
+set_false_path -from [get_ports "RESET"]
+
+# Derived clock periods. These are commented out because they are
+# automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you
+# can copy them into your module level timing checks
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
diff --git a/rtl/src/ipcore/clkmgr_dcm.xise b/rtl/src/ipcore/clkmgr_dcm.xise new file mode 100644 index 0000000..6ab49ca --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm.xise @@ -0,0 +1,74 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="clkmgr_dcm.ucf" xil_pn:type="FILE_UCF"> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + </file> + <file xil_pn:name="clkmgr_dcm.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/> + </file> + </files> + + <properties> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|clkmgr_dcm" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="clkmgr_dcm.v" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clkmgr_dcm" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_DesignName" xil_pn:value="clkmgr_dcm" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-01-29T01:56:27" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="35ECECEDE6BC496293C4671B28106B0F" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings> + <binding xil_pn:location="/clkmgr_dcm" xil_pn:name="clkmgr_dcm.ucf"/> + </bindings> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/rtl/src/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt b/rtl/src/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt new file mode 100644 index 0000000..91dcdd0 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt @@ -0,0 +1,184 @@ +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: June 19, 2013 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with example design becoming core top in planAhead + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/rtl/src/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt b/rtl/src/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt new file mode 100644 index 0000000..91dcdd0 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt @@ -0,0 +1,184 @@ +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: June 19, 2013 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with example design becoming core top in planAhead + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/rtl/src/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html b/rtl/src/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html new file mode 100644 index 0000000..d6deba0 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html @@ -0,0 +1,195 @@ +<HTML> +<HEAD> +<TITLE>clk_wiz_v3_6_vinfo</TITLE> +<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1"> +</HEAD> +<BODY> +<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1"> +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: June 19, 2013 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A> + +For system requirements: + + <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A> + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + <A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A> + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with example design becoming core top in planAhead + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - <A HREF="http://www.xilinx.com/support/answers/50719.htm">www.xilinx.com/support/answers/50719.htm</A> + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A> + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A> +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + +</FONT> +</PRE> +</BODY> +</HTML> diff --git a/rtl/src/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf b/rtl/src/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf Binary files differnew file mode 100644 index 0000000..a7daa60 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf diff --git a/rtl/src/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf b/rtl/src/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf new file mode 100644 index 0000000..dffb528 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf @@ -0,0 +1,60 @@ +# file: clkmgr_dcm_exdes.ucf
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints
+PIN "COUNTER_RESET" TIG;
+PIN "RESET" TIG;
+
diff --git a/rtl/src/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v b/rtl/src/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v new file mode 100644 index 0000000..10627b3 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v @@ -0,0 +1,164 @@ +// file: clkmgr_dcm_exdes.v
+//
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+
+//----------------------------------------------------------------------------
+// Clocking wizard example design
+//----------------------------------------------------------------------------
+// This example design instantiates the created clocking network, where each
+// output clock drives a counter. The high bit of each counter is ported.
+//----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+module clkmgr_dcm_exdes
+ #(
+ parameter TCQ = 100
+ )
+ (// Clock in ports
+ input CLK_IN1,
+ // Reset that only drives logic in example design
+ input COUNTER_RESET,
+ output [1:1] CLK_OUT,
+ // High bits of counters driven by clocks
+ output COUNT,
+ // Status and control signals
+ input RESET,
+ output INPUT_CLK_STOPPED,
+ output CLK_VALID
+ );
+
+ // Parameters for the counters
+ //-------------------------------
+ // Counter width
+ localparam C_W = 16;
+ // Create reset for the counters
+ wire reset_int = RESET || COUNTER_RESET;
+
+ reg rst_sync;
+ reg rst_sync_int;
+ reg rst_sync_int1;
+ reg rst_sync_int2;
+
+
+
+ // Declare the clocks and counter
+ wire clk_int;
+ wire clk_n;
+ wire clk;
+ reg [C_W-1:0] counter;
+
+ // Insert BUFGs on all input clocks that don't already have them
+ //--------------------------------------------------------------
+ BUFG clkin1_buf
+ (.O (clk_in1_buf),
+ .I (CLK_IN1));
+
+ // Instantiation of the clocking network
+ //--------------------------------------
+ clkmgr_dcm clknetwork
+ (// Clock in ports
+ .CLK_IN1 (clk_in1_buf),
+ // Clock out ports
+ .CLK_OUT1 (clk_int),
+ // Status and control signals
+ .RESET (RESET),
+ .INPUT_CLK_STOPPED (INPUT_CLK_STOPPED),
+ .CLK_VALID (CLK_VALID));
+
+ assign clk_n = ~clk;
+
+ ODDR2 clkout_oddr
+ (.Q (CLK_OUT[1]),
+ .C0 (clk),
+ .C1 (clk_n),
+ .CE (1'b1),
+ .D0 (1'b1),
+ .D1 (1'b0),
+ .R (1'b0),
+ .S (1'b0));
+
+ // Connect the output clocks to the design
+ //-----------------------------------------
+ assign clk = clk_int;
+
+
+ // Reset synchronizer
+ //-----------------------------------
+ always @(posedge reset_int or posedge clk) begin
+ if (reset_int) begin
+ rst_sync <= 1'b1;
+ rst_sync_int <= 1'b1;
+ rst_sync_int1 <= 1'b1;
+ rst_sync_int2 <= 1'b1;
+ end
+ else begin
+ rst_sync <= 1'b0;
+ rst_sync_int <= rst_sync;
+ rst_sync_int1 <= rst_sync_int;
+ rst_sync_int2 <= rst_sync_int1;
+ end
+ end
+
+
+ // Output clock sampling
+ //-----------------------------------
+ always @(posedge clk or posedge rst_sync_int2) begin
+ if (rst_sync_int2) begin
+ counter <= #TCQ { C_W { 1'b 0 } };
+ end else begin
+ counter <= #TCQ counter + 1'b 1;
+ end
+ end
+
+ // alias the high bit to the output
+ assign COUNT = counter[C_W-1];
+
+
+
+endmodule
diff --git a/rtl/src/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc b/rtl/src/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc new file mode 100644 index 0000000..787023d --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc @@ -0,0 +1,69 @@ +# file: clkmgr_dcm_exdes.xdc
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1]
+set_propagated_clock CLK_IN1
+set_input_jitter CLK_IN1 0.2
+
+# FALSE PATH constraint added on COUNTER_RESET
+set_false_path -from [get_ports "COUNTER_RESET"]
+set_false_path -from [get_ports "RESET"]
+
+# Derived clock periods. These are commented out because they are
+# automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you
+# can copy them into your module level timing checks
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
diff --git a/rtl/src/ipcore/clkmgr_dcm/implement/implement.bat b/rtl/src/ipcore/clkmgr_dcm/implement/implement.bat new file mode 100644 index 0000000..3d313d5 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/implement/implement.bat @@ -0,0 +1,90 @@ +REM file: implement.bat
+REM
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM
+
+REM -----------------------------------------------------------------------------
+REM Script to synthesize and implement the RTL provided for the clocking wizard
+REM -----------------------------------------------------------------------------
+
+REM Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+REM Copy unisim_comp.v file to results directory
+copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
+
+REM Synthesize the Verilog Wrapper Files
+echo 'Synthesizing Clocking Wizard design with XST'
+xst -ifn xst.scr
+move clkmgr_dcm_exdes.ngc results\
+
+REM Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\clkmgr_dcm_exdes.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -uc clkmgr_dcm_exdes.ucf clkmgr_dcm_exdes
+
+echo 'Running map'
+map -timing -pr b clkmgr_dcm_exdes -o mapped.ncd
+
+echo 'Running par'
+par -w mapped.ncd routed mapped.pcf
+
+echo 'Running trce'
+trce -e 10 routed -o routed mapped.pcf
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level model for the clocking wizard example design'
+netgen -ofmt verilog -sim -sdf_anno false -tm clkmgr_dcm_exdes -w routed.ncd routed.v
+cd ..
+
diff --git a/rtl/src/ipcore/clkmgr_dcm/implement/implement.sh b/rtl/src/ipcore/clkmgr_dcm/implement/implement.sh new file mode 100644 index 0000000..2c64bee --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/implement/implement.sh @@ -0,0 +1,91 @@ +#!/bin/sh
+# file: implement.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the clocking wizard
+#-----------------------------------------------------------------------------
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+# Copy unisim_comp.v file to results directory
+cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
+
+# Synthesize the Verilog Wrapper Files
+echo 'Synthesizing Clocking Wizard design with XST'
+xst -ifn xst.scr
+mv clkmgr_dcm_exdes.ngc results/
+
+# Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/clkmgr_dcm_exdes.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -uc clkmgr_dcm_exdes.ucf clkmgr_dcm_exdes
+
+echo 'Running map'
+map -timing clkmgr_dcm_exdes -o mapped.ncd
+
+echo 'Running par'
+par -w mapped.ncd routed mapped.pcf
+
+echo 'Running trce'
+trce -e 10 routed -o routed mapped.pcf
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level model for the clocking wizard example design'
+netgen -ofmt verilog -sim -sdf_anno false -tm clkmgr_dcm_exdes -w routed.ncd routed.v
+
+cd ..
diff --git a/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_ise.bat b/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_ise.bat new file mode 100644 index 0000000..9782028 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_ise.bat @@ -0,0 +1,58 @@ +REM file: planAhead_ise.bat
+REM
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM
+
+REM-----------------------------------------------------------------------------
+REM Script to synthesize and implement the RTL provided for the clocking wizard
+REM-----------------------------------------------------------------------------
+
+del \f results
+mkdir results
+cd results
+
+planAhead -mode batch -source ..\planAhead_ise.tcl
diff --git a/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_ise.sh b/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_ise.sh new file mode 100644 index 0000000..7f436b6 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_ise.sh @@ -0,0 +1,59 @@ +#!/bin/sh
+# file: planAhead_ise.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the clocking wizard
+#-----------------------------------------------------------------------------
+
+rm -rf results
+mkdir results
+cd results
+
+planAhead -mode batch -source ../planAhead_ise.tcl
diff --git a/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl b/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl new file mode 100644 index 0000000..ab77638 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl @@ -0,0 +1,78 @@ +# file: planAhead_ise.tcl
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+set projDir [file dirname [info script]]
+set projName clkmgr_dcm
+set topName clkmgr_dcm_exdes
+set device xc6slx45csg324-3
+
+create_project $projName $projDir/results/$projName -part $device
+
+set_property design_mode RTL [get_filesets sources_1]
+
+## Source files
+#set verilogSources [glob $srcDir/*.v]
+import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/clkmgr_dcm_exdes.v
+import_files -fileset [get_filesets sources_1] -force -norecurse ../../../clkmgr_dcm.v
+
+
+#UCF file
+import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/clkmgr_dcm_exdes.ucf
+
+set_property top $topName [get_property srcset [current_run]]
+
+launch_runs -runs synth_1
+wait_on_run synth_1
+
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs -runs impl_1
+wait_on_run impl_1
+
+
+
diff --git a/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat b/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat new file mode 100644 index 0000000..3e1e03b --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat @@ -0,0 +1,58 @@ +REM file: planAhead_rdn.sh
+REM
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM
+
+REM-----------------------------------------------------------------------------
+REM Script to synthesize and implement the RTL provided for the XADC wizard
+REM-----------------------------------------------------------------------------
+
+del \f results
+mkdir results
+cd results
+
+planAhead -mode batch -source ..\planAhead_rdn.tcl
diff --git a/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh b/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh new file mode 100644 index 0000000..a5adee8 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh @@ -0,0 +1,57 @@ +#!/bin/sh
+# file: planAhead_rdn.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the XADC wizard
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+planAhead -mode batch -source ../planAhead_rdn.tcl
diff --git a/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl b/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl new file mode 100644 index 0000000..e8c0fdf --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl @@ -0,0 +1,69 @@ +# file : planAhead_rdn.tcl
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+set device xc6slx45csg324-3
+set projName clkmgr_dcm
+set design clkmgr_dcm
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module clkmgr_dcm_exdes
+set_property top clkmgr_dcm_exdes [get_property srcset [current_run]]
+add_files -norecurse {../../../clkmgr_dcm.v}
+add_files -norecurse {../../example_design/clkmgr_dcm_exdes.v}
+import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/clkmgr_dcm_exdes.xdc}
+synth_design
+opt_design
+place_design
+route_design
+write_sdf -rename_top_module clkmgr_dcm_exdes -file routed.sdf
+write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module clkmgr_dcm_exdes -file routed.v
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
diff --git a/rtl/src/ipcore/clkmgr_dcm/implement/xst.prj b/rtl/src/ipcore/clkmgr_dcm/implement/xst.prj new file mode 100644 index 0000000..cd0e0e6 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/implement/xst.prj @@ -0,0 +1,2 @@ +verilog work ../../clkmgr_dcm.v
+verilog work ../example_design/clkmgr_dcm_exdes.v
diff --git a/rtl/src/ipcore/clkmgr_dcm/implement/xst.scr b/rtl/src/ipcore/clkmgr_dcm/implement/xst.scr new file mode 100644 index 0000000..20d09f4 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/implement/xst.scr @@ -0,0 +1,9 @@ +run
+-ifmt MIXED
+-top clkmgr_dcm_exdes
+-p xc6slx45-csg324-3
+-ifn xst.prj
+-ofn clkmgr_dcm_exdes
+-keep_hierarchy soft
+-equivalent_register_removal no
+-max_fanout 65535
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v b/rtl/src/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v new file mode 100644 index 0000000..ee24750 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v @@ -0,0 +1,145 @@ +// file: clkmgr_dcm_tb.v
+//
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+
+//----------------------------------------------------------------------------
+// Clocking wizard demonstration testbench
+//----------------------------------------------------------------------------
+// This demonstration testbench instantiates the example design for the
+// clocking wizard. Input clocks are toggled, which cause the clocking
+// network to lock and the counters to increment.
+//----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+`define wait_lock @(posedge CLK_VALID)
+
+module clkmgr_dcm_tb ();
+
+ // Clock to Q delay of 100ps
+ localparam TCQ = 100;
+
+
+ // timescale is 1ps/1ps
+ localparam ONE_NS = 1000;
+ localparam PHASE_ERR_MARGIN = 100; // 100ps
+ // how many cycles to run
+ localparam COUNT_PHASE = 1024;
+ // we'll be using the period in many locations
+ localparam time PER1 = 20.0*ONE_NS;
+ localparam time PER1_1 = PER1/2;
+ localparam time PER1_2 = PER1 - PER1/2;
+
+ // Declare the input clock signals
+ reg CLK_IN1 = 1;
+
+ // The high bit of the sampling counter
+ wire COUNT;
+ // Status and control signals
+ reg RESET = 0;
+ wire INPUT_CLK_STOPPED;
+ wire CLK_VALID;
+ reg COUNTER_RESET = 0;
+wire [1:1] CLK_OUT;
+//Freq Check using the M & D values setting and actual Frequency generated
+
+
+ // Input clock generation
+ //------------------------------------
+ always begin
+ CLK_IN1 = #PER1_1 ~CLK_IN1;
+ CLK_IN1 = #PER1_2 ~CLK_IN1;
+ end
+
+ // Test sequence
+ reg [15*8-1:0] test_phase = "";
+ initial begin
+ // Set up any display statements using time to be readable
+ $timeformat(-12, 2, "ps", 10);
+ COUNTER_RESET = 0;
+ test_phase = "reset";
+ RESET = 1;
+ #(PER1*6);
+ RESET = 0;
+ test_phase = "wait lock";
+ `wait_lock;
+ #(PER1*6);
+ COUNTER_RESET = 1;
+ #(PER1*20)
+ COUNTER_RESET = 0;
+
+ test_phase = "counting";
+ #(PER1*COUNT_PHASE);
+
+ $display("SIMULATION PASSED");
+ $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
+ $finish;
+ end
+
+ // Instantiation of the example design containing the clock
+ // network and sampling counters
+ //---------------------------------------------------------
+ clkmgr_dcm_exdes
+ #(
+ .TCQ (TCQ)
+ ) dut
+ (// Clock in ports
+ .CLK_IN1 (CLK_IN1),
+ // Reset for logic in example design
+ .COUNTER_RESET (COUNTER_RESET),
+ .CLK_OUT (CLK_OUT),
+ // High bits of the counters
+ .COUNT (COUNT),
+ // Status and control signals
+ .RESET (RESET),
+ .INPUT_CLK_STOPPED (INPUT_CLK_STOPPED),
+ .CLK_VALID (CLK_VALID));
+
+// Freq Check
+
+endmodule
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl new file mode 100644 index 0000000..e19ead8 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl @@ -0,0 +1,8 @@ +# file: simcmds.tcl
+
+# create the simulation script
+vcd dumpfile isim.vcd
+vcd dumpvars -m /clkmgr_dcm_tb -l 0
+wave add /
+run 50000ns
+quit
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat new file mode 100644 index 0000000..80904cb --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat @@ -0,0 +1,59 @@ +REM file: simulate_isim.bat
+REM
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM
+
+vlogcomp -work work %XILINX%\verilog\src\glbl.v
+vlogcomp -work work ..\..\..\clkmgr_dcm.v
+vlogcomp -work work ..\..\example_design\clkmgr_dcm_exdes.v
+vlogcomp -work work ..\clkmgr_dcm_tb.v
+
+REM compile the project
+fuse work.clkmgr_dcm_tb work.glbl -L unisims_ver -o clkmgr_dcm_isim.exe
+
+REM run the simulation script
+.\clkmgr_dcm_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh new file mode 100644 index 0000000..9fb5029 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh @@ -0,0 +1,61 @@ +# file: simulate_isim.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# nt
+# create the project
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work ../../../clkmgr_dcm.v
+vlogcomp -work work ../../example_design/clkmgr_dcm_exdes.v
+vlogcomp -work work ../clkmgr_dcm_tb.v
+
+# compile the project
+fuse work.clkmgr_dcm_tb work.glbl -L unisims_ver -o clkmgr_dcm_isim.exe
+
+# run the simulation script
+./clkmgr_dcm_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat new file mode 100644 index 0000000..7497cd9 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat @@ -0,0 +1,61 @@ +REM file: simulate_mti.bat
+REM
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM
+
+REM set up the working directory
+vlib work
+
+REM compile all of the files
+vlog -work work %XILINX%\verilog\src\glbl.v
+vlog -work work ..\..\..\clkmgr_dcm.v
+vlog -work work ..\..\example_design\clkmgr_dcm_exdes.v
+vlog -work work ..\clkmgr_dcm_tb.v
+
+REM run the simulation
+vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.clkmgr_dcm_tb work.glbl
+
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do new file mode 100644 index 0000000..b0e526f --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $env(XILINX)/verilog/src/glbl.v
+vlog -work work ../../../clkmgr_dcm.v
+vlog -work work ../../example_design/clkmgr_dcm_exdes.v
+vlog -work work ../clkmgr_dcm_tb.v
+
+# run the simulation
+vsim -t ps -voptargs="+acc" -L unisims_ver work.clkmgr_dcm_tb work.glbl
+do wave.do
+log clkmgr_dcm_tb/dut/counter
+log -r /*
+run 50000ns
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh new file mode 100644 index 0000000..66099e0 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh
+# file: simulate_mti.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $XILINX/verilog/src/glbl.v
+vlog -work work ../../../clkmgr_dcm.v
+vlog -work work ../../example_design/clkmgr_dcm_exdes.v
+vlog -work work ../clkmgr_dcm_tb.v
+
+# run the simulation
+vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.clkmgr_dcm_tb work.glbl
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh new file mode 100644 index 0000000..01b0412 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,62 @@ +#/bin/sh
+# file: simulate_ncsim.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# set up the working directory
+mkdir work
+
+# compile all of the files
+ncvlog -work work ${XILINX}/verilog/src/glbl.v
+ncvlog -work work ../../../clkmgr_dcm.v
+ncvlog -work work ../../example_design/clkmgr_dcm_exdes.v
+ncvlog -work work ../clkmgr_dcm_tb.v
+
+# elaborate and run the simulation
+ncelab -work work -access +wc work.clkmgr_dcm_tb work.glbl
+ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.clkmgr_dcm_tb
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh new file mode 100644 index 0000000..39668df --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh
+# file: simulate_vcs.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# remove old files
+rm -rf simv* csrc DVEfiles AN.DB
+
+# compile all of the files
+# Note that -sverilog is not strictly required- You can
+# remove the -sverilog if you change the type of the
+# localparam for the periods in the testbench file to
+# [63:0] from time
+vlogan -sverilog \
+ ${XILINX}/verilog/src/glbl.v \
+ ../../../clkmgr_dcm.v \
+ ../../example_design/clkmgr_dcm_exdes.v \
+ ../clkmgr_dcm_tb.v
+
+# prepare the simulation
+vcs +vcs+lic+wait -debug clkmgr_dcm_tb glbl
+
+# run the simulation
+./simv -ucli -i ucli_commands.key
+
+# launch the viewer
+dve -vpd vcdplus.vpd -session vcs_session.tcl
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key new file mode 100644 index 0000000..2bbdd0f --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key @@ -0,0 +1,5 @@ +call {$vcdpluson}
+call {$vcdplusmemon(clkmgr_dcm_tb.dut.counter)}
+run
+call {$vcdplusclose}
+quit
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl new file mode 100644 index 0000000..628e55a --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl @@ -0,0 +1,18 @@ +gui_open_window Wave
+gui_sg_create clkmgr_dcm_group
+gui_list_add_group -id Wave.1 {clkmgr_dcm_group}
+gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.test_phase}
+gui_set_radix -radix {ascii} -signals {clkmgr_dcm_tb.test_phase}
+gui_sg_addsignal -group clkmgr_dcm_group {{Input_clocks}} -divider
+gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.CLK_IN1}
+gui_sg_addsignal -group clkmgr_dcm_group {{Output_clocks}} -divider
+gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.dut.clk}
+gui_list_expand -id Wave.1 clkmgr_dcm_tb.dut.clk
+gui_sg_addsignal -group clkmgr_dcm_group {{Status_control}} -divider
+gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.RESET}
+gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.USE_INCLK_STOPPED}
+gui_sg_addsignal -group clkmgr_dcm_group {{Counters}} -divider
+gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.COUNT}
+gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.dut.counter}
+gui_list_expand -id Wave.1 clkmgr_dcm_tb.dut.counter
+gui_zoom -window Wave.1 -full
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/functional/wave.do b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/wave.do new file mode 100644 index 0000000..eee7422 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/wave.do @@ -0,0 +1,60 @@ +# file: wave.do
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+add wave -noupdate -format Literal -radix ascii /clkmgr_dcm_tb/test_phase
+add wave -noupdate -divider {Input clocks}
+add wave -noupdate -format Logic /clkmgr_dcm_tb/CLK_IN1
+add wave -noupdate -divider {Output clocks}
+add wave -noupdate -format Logic /clkmgr_dcm_tb/dut/clk
+add wave -noupdate -divider Status/control
+add wave -noupdate -format Logic /clkmgr_dcm_tb/RESET
+add wave -noupdate -format Logic /clkmgr_dcm_tb/INPUT_CLK_STOPPED
+add wave -noupdate -divider Counters
+add wave -noupdate -format Literal -radix hexadecimal /clkmgr_dcm_tb/COUNT
+add wave -noupdate -format Literal -radix hexadecimal /clkmgr_dcm_tb/dut/counter
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/functional/wave.sv b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/wave.sv new file mode 100644 index 0000000..c3c3eef --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/wave.sv @@ -0,0 +1,118 @@ +# file: wave.sv
+#
+# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# Get the windows set up
+#
+if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} {
+ window geometry "Design Browser 1" 1054x819+536+322
+}
+window target "Design Browser 1" on
+browser using {Design Browser 1}
+browser set \
+ -scope nc::clkmgr_dcm_tb
+browser yview see nc::clkmgr_dcm_tb
+browser timecontrol set -lock 0
+
+if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
+ window geometry "Waveform 1" 1010x600+0+541
+}
+window target "Waveform 1" on
+waveform using {Waveform 1}
+waveform sidebar visibility partial
+waveform set \
+ -primarycursor TimeA \
+ -signalnames name \
+ -signalwidth 175 \
+ -units ns \
+ -valuewidth 75
+cursor set -using TimeA -time 0
+waveform baseline set -time 0
+waveform xview limits 0 20000n
+
+#
+# Define signal groups
+#
+catch {group new -name {Output clocks} -overlay 0}
+catch {group new -name {Status/control} -overlay 0}
+catch {group new -name {Counters} -overlay 0}
+
+set id [waveform add -signals [list {nc::clkmgr_dcm_tb.CLK_IN1}]]
+
+group using {Output clocks}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+ {clkmgr_dcm_tb.dut.clk} \
+
+group using {Counters}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+ {clkmgr_dcm_tb.dut.counter} \
+
+group using {Status/control}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+ {nc::clkmgr_dcm_tb.RESET} {nc::clkmgr_dcm_tb.INPUT_CLK_STOPPED}
+
+set id [waveform add -signals [list {nc::clkmgr_dcm_tb.COUNT} ]]
+
+set id [waveform add -signals [list {nc::clkmgr_dcm_tb.test_phase} ]]
+waveform format $id -radix %a
+
+set groupId [waveform add -groups {{Input clocks}}]
+set groupId [waveform add -groups {{Output clocks}}]
+set groupId [waveform add -groups {{Status/control}}]
+set groupId [waveform add -groups {{Counters}}]
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v new file mode 100644 index 0000000..9618253 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v @@ -0,0 +1,149 @@ +// file: clkmgr_dcm_tb.v
+//
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+
+//----------------------------------------------------------------------------
+// Clocking wizard demonstration testbench
+//----------------------------------------------------------------------------
+// This demonstration testbench instantiates the example design for the
+// clocking wizard. Input clocks are toggled, which cause the clocking
+// network to lock and the counters to increment.
+//----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+`define wait_lock @(posedge CLK_VALID)
+
+module clkmgr_dcm_tb ();
+
+ // Clock to Q delay of 100ps
+ localparam TCQ = 100;
+
+
+ // timescale is 1ps/1ps
+ localparam ONE_NS = 1000;
+ localparam PHASE_ERR_MARGIN = 100; // 100ps
+ // how many cycles to run
+ localparam COUNT_PHASE = 1024;
+ // we'll be using the period in many locations
+ localparam time PER1 = 20.0*ONE_NS;
+ localparam time PER1_1 = PER1/2;
+ localparam time PER1_2 = PER1 - PER1/2;
+
+ // Declare the input clock signals
+ reg CLK_IN1 = 1;
+
+ // The high bit of the sampling counter
+ wire COUNT;
+ // Status and control signals
+ reg RESET = 0;
+ wire INPUT_CLK_STOPPED;
+ wire CLK_VALID;
+ reg COUNTER_RESET = 0;
+wire [1:1] CLK_OUT;
+//Freq Check using the M & D values setting and actual Frequency generated
+
+ reg [13:0] timeout_counter = 14'b00000000000000;
+
+ // Input clock generation
+ //------------------------------------
+ always begin
+ CLK_IN1 = #PER1_1 ~CLK_IN1;
+ CLK_IN1 = #PER1_2 ~CLK_IN1;
+ end
+
+ // Test sequence
+ reg [15*8-1:0] test_phase = "";
+ initial begin
+ // Set up any display statements using time to be readable
+ $timeformat(-12, 2, "ps", 10);
+ $display ("Timing checks are not valid");
+ COUNTER_RESET = 0;
+ test_phase = "reset";
+ RESET = 1;
+ #(PER1*6);
+ RESET = 0;
+ test_phase = "wait lock";
+ `wait_lock;
+ #(PER1*6);
+ COUNTER_RESET = 1;
+ #(PER1*19.5)
+ COUNTER_RESET = 0;
+ #(PER1*1)
+ $display ("Timing checks are valid");
+ test_phase = "counting";
+ #(PER1*COUNT_PHASE);
+
+ $display("SIMULATION PASSED");
+ $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
+ $finish;
+ end
+
+
+
+ // Instantiation of the example design containing the clock
+ // network and sampling counters
+ //---------------------------------------------------------
+ clkmgr_dcm_exdes
+ dut
+ (// Clock in ports
+ .CLK_IN1 (CLK_IN1),
+ // Reset for logic in example design
+ .COUNTER_RESET (COUNTER_RESET),
+ .CLK_OUT (CLK_OUT),
+ // High bits of the counters
+ .COUNT (COUNT),
+ // Status and control signals
+ .RESET (RESET),
+ .INPUT_CLK_STOPPED (INPUT_CLK_STOPPED),
+ .CLK_VALID (CLK_VALID));
+
+
+// Freq Check
+
+endmodule
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file new file mode 100644 index 0000000..d59e315 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file @@ -0,0 +1,2 @@ +COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
+SCOPE = clkmgr_dcm_tb.dut;
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl new file mode 100644 index 0000000..14523af --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl @@ -0,0 +1,9 @@ +# file: simcmds.tcl
+
+# create the simulation script
+vcd dumpfile isim.vcd
+vcd dumpvars -m /clkmgr_dcm_tb -l 0
+wave add /
+run 50000ns
+quit
+
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh new file mode 100644 index 0000000..0152cb0 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh @@ -0,0 +1,62 @@ +# file: simulate_isim.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# create the project
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work ../../implement/results/routed.v
+vlogcomp -work work clkmgr_dcm_tb.v
+
+# compile the project
+fuse work.clkmgr_dcm_tb work.glbl -L secureip -L simprims_ver -o clkmgr_dcm_isim.exe
+
+# run the simulation script
+./clkmgr_dcm_isim.exe -tclbatch simcmds.tcl -sdfmax /clkmgr_dcm_tb/dut=../../implement/results/routed.sdf
+
+# run the simulation script
+#./clkmgr_dcm_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat new file mode 100644 index 0000000..8a08dc0 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat @@ -0,0 +1,59 @@ +REM file: simulate_mti.bat
+REM
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM
+# set up the working directory
+set work work
+vlib work
+
+REM compile all of the files
+vlog -work work %XILINX%\verilog\src\glbl.v
+vlog -work work ..\..\implement\results\routed.v
+vlog -work work clkmgr_dcm_tb.v
+
+REM run the simulation
+vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clkmgr_dcm_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.clkmgr_dcm_tb work.glbl
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do new file mode 100644 index 0000000..bfeb9c5 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $env(XILINX)/verilog/src/glbl.v
+vlog -work work ../../implement/results/routed.v
+vlog -work work clkmgr_dcm_tb.v
+
+# run the simulation
+vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clkmgr_dcm_tb/dut=../../implement/results/routed.sdf +no_notifier work.clkmgr_dcm_tb work.glbl
+#do wave.do
+#log -r /*
+run 50000ns
+
+
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh new file mode 100644 index 0000000..b842adc --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh
+# file: simulate_mti.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $XILINX/verilog/src/glbl.v
+vlog -work work ../../implement/results/routed.v
+vlog -work work clkmgr_dcm_tb.v
+
+# run the simulation
+vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clkmgr_dcm_tb/dut=../../implement/results/routed.sdf +no_notifier work.clkmgr_dcm_tb work.glbl
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh new file mode 100644 index 0000000..fd18dde --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,64 @@ +#!/bin/sh
+# file: simulate_ncsim.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# set up the working directory
+mkdir work
+
+# compile all of the files
+ncvlog -work work ${XILINX}/verilog/src/glbl.v
+ncvlog -work work ../../implement/results/routed.v
+ncvlog -work work clkmgr_dcm_tb.v
+
+# elaborate and run the simulation
+ncsdfc ../../implement/results/routed.sdf
+
+ncelab -work work -access +wc -pulse_r 10 -nonotifier work.clkmgr_dcm_tb work.glbl -sdf_cmd_file sdf_cmd_file
+ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.clkmgr_dcm_tb
+
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh new file mode 100644 index 0000000..26a8c27 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh
+# file: simulate_vcs.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# remove old files
+rm -rf simv* csrc DVEfiles AN.DB
+
+# compile all of the files
+# Note that -sverilog is not strictly required- You can
+# remove the -sverilog if you change the type of the
+# localparam for the periods in the testbench file to
+# [63:0] from time
+ vlogan -sverilog \
+ clkmgr_dcm_tb.v \
+ ../../implement/results/routed.v
+
+
+# prepare the simulation
+vcs -sdf max:clkmgr_dcm_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \
+ +libext+.v -debug clkmgr_dcm_tb.v ../../implement/results/routed.v
+
+# run the simulation
+./simv -ucli -i ucli_commands.key
+
+# launch the viewer
+#dve -vpd vcdplus.vpd -session vcs_session.tcl
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key new file mode 100644 index 0000000..b32669e --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key @@ -0,0 +1,5 @@ +
+call {$vcdpluson}
+run 50000ns
+call {$vcdplusclose}
+quit
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl new file mode 100644 index 0000000..6cc6e24 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl @@ -0,0 +1 @@ +gui_open_window Wave
diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/timing/wave.do b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/wave.do new file mode 100644 index 0000000..7cc804b --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/wave.do @@ -0,0 +1,71 @@ +# file: wave.do
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /clkmgr_dcm_tb/CLK_IN1
+add wave -noupdate /clkmgr_dcm_tb/COUNT
+add wave -noupdate /clkmgr_dcm_tb/RESET
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}
+configure wave -namecolwidth 238
+configure wave -valuecolwidth 107
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {74848022 ps}
diff --git a/rtl/src/ipcore/clkmgr_dcm_flist.txt b/rtl/src/ipcore/clkmgr_dcm_flist.txt new file mode 100644 index 0000000..33943f8 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm_flist.txt @@ -0,0 +1,55 @@ +# Output products list for <clkmgr_dcm>
+_xmsgs\pn_parser.xmsgs
+clkmgr_dcm.asy
+clkmgr_dcm.gise
+clkmgr_dcm.sym
+clkmgr_dcm.ucf
+clkmgr_dcm.v
+clkmgr_dcm.veo
+clkmgr_dcm.xco
+clkmgr_dcm.xdc
+clkmgr_dcm.xise
+clkmgr_dcm\clk_wiz_v3_6_readme.txt
+clkmgr_dcm\doc\clk_wiz_v3_6_readme.txt
+clkmgr_dcm\doc\clk_wiz_v3_6_vinfo.html
+clkmgr_dcm\doc\pg065_clk_wiz.pdf
+clkmgr_dcm\example_design\clkmgr_dcm_exdes.ucf
+clkmgr_dcm\example_design\clkmgr_dcm_exdes.v
+clkmgr_dcm\example_design\clkmgr_dcm_exdes.xdc
+clkmgr_dcm\implement\implement.bat
+clkmgr_dcm\implement\implement.sh
+clkmgr_dcm\implement\planAhead_ise.bat
+clkmgr_dcm\implement\planAhead_ise.sh
+clkmgr_dcm\implement\planAhead_ise.tcl
+clkmgr_dcm\implement\planAhead_rdn.bat
+clkmgr_dcm\implement\planAhead_rdn.sh
+clkmgr_dcm\implement\planAhead_rdn.tcl
+clkmgr_dcm\implement\xst.prj
+clkmgr_dcm\implement\xst.scr
+clkmgr_dcm\simulation\clkmgr_dcm_tb.v
+clkmgr_dcm\simulation\functional\simcmds.tcl
+clkmgr_dcm\simulation\functional\simulate_isim.bat
+clkmgr_dcm\simulation\functional\simulate_isim.sh
+clkmgr_dcm\simulation\functional\simulate_mti.bat
+clkmgr_dcm\simulation\functional\simulate_mti.do
+clkmgr_dcm\simulation\functional\simulate_mti.sh
+clkmgr_dcm\simulation\functional\simulate_ncsim.sh
+clkmgr_dcm\simulation\functional\simulate_vcs.sh
+clkmgr_dcm\simulation\functional\ucli_commands.key
+clkmgr_dcm\simulation\functional\vcs_session.tcl
+clkmgr_dcm\simulation\functional\wave.do
+clkmgr_dcm\simulation\functional\wave.sv
+clkmgr_dcm\simulation\timing\clkmgr_dcm_tb.v
+clkmgr_dcm\simulation\timing\sdf_cmd_file
+clkmgr_dcm\simulation\timing\simcmds.tcl
+clkmgr_dcm\simulation\timing\simulate_isim.sh
+clkmgr_dcm\simulation\timing\simulate_mti.bat
+clkmgr_dcm\simulation\timing\simulate_mti.do
+clkmgr_dcm\simulation\timing\simulate_mti.sh
+clkmgr_dcm\simulation\timing\simulate_ncsim.sh
+clkmgr_dcm\simulation\timing\simulate_vcs.sh
+clkmgr_dcm\simulation\timing\ucli_commands.key
+clkmgr_dcm\simulation\timing\vcs_session.tcl
+clkmgr_dcm\simulation\timing\wave.do
+clkmgr_dcm_flist.txt
+clkmgr_dcm_xmdf.tcl
diff --git a/rtl/src/ipcore/clkmgr_dcm_xmdf.tcl b/rtl/src/ipcore/clkmgr_dcm_xmdf.tcl new file mode 100644 index 0000000..307029b --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm_xmdf.tcl @@ -0,0 +1,140 @@ +# The package naming convention is <core_name>_xmdf
+package provide clkmgr_dcm_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::clkmgr_dcm_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::clkmgr_dcm_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name clkmgr_dcm
+}
+# ::clkmgr_dcm_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::clkmgr_dcm_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/clk_wiz_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/doc/clk_wiz_ds709.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/doc/clk_wiz_gsg521.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/implement/implement.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/implement/implement.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/implement/xst.prj
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/implement/xst.scr
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/clkmgr_dcm_tb.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/simcmds.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/simulate_isim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/simulate_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/simulate_ncsim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/simulate_vcs.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/ucli_commands.key
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/vcs_session.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/wave.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/wave.sv
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.ejp
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module clkmgr_dcm
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/rtl/src/ipcore/coregen.cgp b/rtl/src/ipcore/coregen.cgp new file mode 100644 index 0000000..929723b --- /dev/null +++ b/rtl/src/ipcore/coregen.cgp @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = Verilog
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET package = csg324
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
diff --git a/rtl/src/ipcore/create_clkmgr_dcm.tcl b/rtl/src/ipcore/create_clkmgr_dcm.tcl new file mode 100644 index 0000000..fec8dec --- /dev/null +++ b/rtl/src/ipcore/create_clkmgr_dcm.tcl @@ -0,0 +1,37 @@ +##
+## Core Generator Run Script, generator for Project Navigator create command
+##
+
+proc findRtfPath { relativePath } {
+ set xilenv ""
+ if { [info exists ::env(XILINX) ] } {
+ if { [info exists ::env(MYXILINX)] } {
+ set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+ } else {
+ set xilenv $::env(XILINX)
+ }
+ }
+ foreach path [ split $xilenv $::xilinx::path_sep ] {
+ set fullPath [ file join $path $relativePath ]
+ if { [ file exists $fullPath ] } {
+ return $fullPath
+ }
+ }
+ return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "clkmgr_dcm" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx45-3csg324 Verilog ]
+
+if { $result == 0 } {
+ puts "Core Generator create command completed successfully."
+} elseif { $result == 1 } {
+ puts "Core Generator create command failed."
+} elseif { $result == 3 || $result == 4 } {
+ # convert 'version check' result to real return range, bypassing any messages.
+ set result [ expr $result - 3 ]
+} else {
+ puts "Core Generator create cancelled."
+}
+exit $result
diff --git a/rtl/src/ipcore/edit_clkmgr_dcm.tcl b/rtl/src/ipcore/edit_clkmgr_dcm.tcl new file mode 100644 index 0000000..4992eb1 --- /dev/null +++ b/rtl/src/ipcore/edit_clkmgr_dcm.tcl @@ -0,0 +1,37 @@ +##
+## Core Generator Run Script, generator for Project Navigator edit command
+##
+
+proc findRtfPath { relativePath } {
+ set xilenv ""
+ if { [info exists ::env(XILINX) ] } {
+ if { [info exists ::env(MYXILINX)] } {
+ set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+ } else {
+ set xilenv $::env(XILINX)
+ }
+ }
+ foreach path [ split $xilenv $::xilinx::path_sep ] {
+ set fullPath [ file join $path $relativePath ]
+ if { [ file exists $fullPath ] } {
+ return $fullPath
+ }
+ }
+ return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_edit "clkmgr_dcm" xc6slx45-3csg324 Verilog ]
+
+if { $result == 0 } {
+ puts "Core Generator edit command completed successfully."
+} elseif { $result == 1 } {
+ puts "Core Generator edit command failed."
+} elseif { $result == 3 || $result == 4 } {
+ # convert 'version check' result to real return range, bypassing any messages.
+ set result [ expr $result - 3 ]
+} else {
+ puts "Core Generator edit cancelled."
+}
+exit $result
diff --git a/rtl/src/testbench/tb_demo_adder.v b/rtl/src/testbench/tb_demo_adder.v new file mode 100644 index 0000000..5abbf06 --- /dev/null +++ b/rtl/src/testbench/tb_demo_adder.v @@ -0,0 +1,173 @@ +`timescale 1ns / 1ps
+
+module tb_demo_adder;
+
+ //
+ // Inputs
+ //
+ reg gclk;
+ wire gclk_p = gclk;
+ wire gclk_n = ~gclk;
+ reg reset_mcu_b;
+
+ //
+ // Outputs
+ //
+ wire led;
+
+ //
+ // EIM
+ //
+ reg eim_cs_n;
+ reg eim_bclk;
+ reg eim_lba_n;
+ wire [15: 0] eim_da;
+ reg [15: 0] eim_da_out;
+ reg eim_da_drive;
+ reg eim_oe_n;
+ reg eim_wr_n;
+ wire eim_wait_n;
+
+ assign eim_da = (eim_da_drive == 1'b1) ? eim_da_out : {16{1'bZ}};
+
+ //
+ // UUT
+ //
+ novena_baseline_top uut
+ (
+ .gclk_p_pin (gclk_p),
+ .gclk_n_pin (gclk_n),
+
+ .eim_bclk (eim_bclk),
+ .eim_cs0_n (eim_cs_n),
+ .eim_da (eim_da),
+ .eim_lba_n (eim_lba_n),
+ .eim_wr_n (eim_wr_n),
+ .eim_oe_n (eim_oe_n),
+ .eim_wait_n (eim_wait_n),
+
+ .reset_mcu_b_pin (reset_mcu_b),
+
+ .led_pin (led_pin),
+ .apoptosis_pin (apoptosis_pin)
+ );
+
+ //
+ // CLK2 (50 MHz)
+ //
+ always #10 gclk = ~gclk;
+
+ //
+ // Initialize EIM
+ //
+ initial begin
+ eim_cs_n = 1'b1;
+ eim_bclk = 1'b0;
+ eim_lba_n = 1'b1;
+ eim_da_out = {16{1'bX}};
+ eim_da_drive = 1'b1;
+ eim_oe_n = 1'b1;
+ eim_wr_n = 1'b1;
+ end
+
+ //
+ // Test Logic
+ //
+ reg [31: 0] eim_rd = {32{1'bX}};
+
+ initial begin
+ gclk = 1'b0;
+ reset_mcu_b = 1'b1;
+ //
+ #2000;
+ //
+ eim_write({12'h321, 2'd0, 2'b00}, 32'hAA_55_A5_A5); // write X
+ #100;
+ eim_write({12'h321, 2'd1, 2'b00}, 32'h11_22_12_12); // write Y
+ #100;
+ eim_read( {12'h321, 2'd3, 2'b00}, eim_rd); // read {STS, CTL} <-- should be 0x0000_0000
+ #100;
+ eim_rd = eim_rd + 1'b1;
+ eim_write({12'h321, 2'd3, 2'b00}, eim_rd); // write {STS, CTL} <-- STS is ignored by adder
+ #100;
+ eim_read( {12'h321, 2'd3, 2'b00}, eim_rd); // read {STS, CTL} <-- should be 0x0001_0001
+ #100;
+ eim_read( {12'h321, 2'd2, 2'b00}, eim_rd); // read Z <-- should be 0xBB77B7B7
+ end
+
+ //
+ // Write Access
+ //
+ integer wr;
+ task eim_write;
+ input [15: 0] addr;
+ input [31: 0] data;
+ begin
+ #15 eim_cs_n = 1'b0;
+ eim_lba_n = 1'b0;
+ eim_da_out = addr;
+ eim_wr_n = 1'b0;
+ #15 eim_bclk = 1'b1;
+ #15 eim_bclk = 1'b0;
+ eim_lba_n = 1'b1;
+ eim_da_out = data[15:0];
+ #15 eim_bclk = 1'b1;
+ #15 eim_bclk = 1'b0;
+ eim_da_out = data[31:16];
+ #15 eim_bclk = 1'b1;
+ #15 eim_bclk = 1'b0;
+ eim_da_out = {16{1'bX}};
+ while (eim_wait_n == 1'b0) begin
+ #15 eim_bclk = 1'b1;
+ #15 eim_bclk = 1'b0;
+ end
+ #15 eim_cs_n = 1'b1;
+ eim_wr_n = 1'b1;
+ #30;
+ end
+ endtask;
+
+
+ //
+ // Read Access
+ //
+ task eim_read;
+ input [15: 0] addr;
+ output [31: 0] data;
+ begin
+ #15 eim_cs_n = 1'b0;
+ eim_lba_n = 1'b0;
+ eim_da_out = addr;
+
+ #15 eim_bclk = 1'b1;
+
+ #15 eim_bclk = 1'b0;
+ eim_lba_n = 1'b1;
+ eim_oe_n = 1'b0;
+ eim_da_drive = 1'b0;
+ #15;
+ while (eim_wait_n == 1'b0) begin
+ eim_bclk = 1'b1;
+ #15 eim_bclk = 1'b0;
+ #15;
+ end
+ eim_bclk = 1'b1;
+ #15 eim_bclk = 1'b0;
+ #15 eim_bclk = 1'b1;
+ data[15: 0] = eim_da;
+ #15 eim_bclk = 1'b0;
+ #15 eim_bclk = 1'b1;
+ data[31:16] = eim_da;
+ #15 eim_bclk = 1'b0;
+ eim_da_out = {16{1'bX}};
+
+ #15 eim_cs_n = 1'b1;
+ eim_oe_n = 1'b1;
+ eim_da_drive = 1'b1;
+ #30;
+ end
+ endtask;
+
+
+endmodule
+
diff --git a/rtl/src/ucf/novena_baseline.ucf b/rtl/src/ucf/novena_baseline.ucf new file mode 100644 index 0000000..6638d7b --- /dev/null +++ b/rtl/src/ucf/novena_baseline.ucf @@ -0,0 +1,98 @@ +#-------------------------------------------------------------------------------
+# FPGA Config
+#-------------------------------------------------------------------------------
+CONFIG VCCAUX = 3.3 ;
+#-------------------------------------------------------------------------------
+
+
+#-------------------------------------------------------------------------------- +# GCLK Timing +#-------------------------------------------------------------------------------- +NET "gclk_p_pin" TNM_NET = TNM_gclk ; +TIMESPEC TS_gclk = PERIOD TNM_gclk 20 ns HIGH 50% ;
+
+
+#-------------------------------------------------------------------------------
+# BCLK Timing
+#-------------------------------------------------------------------------------
+NET "eim_bclk" TNM_NET = TNM_bclk ; +TIMESPEC TS_bclk = PERIOD TNM_bclk 30 ns HIGH 50% ;
+
+
+#-------------------------------------------------------------------------------
+# FPGA Pinout
+#-------------------------------------------------------------------------------
+NET "led_pin" LOC = "A16" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 12 ;
+NET "apoptosis_pin" LOC = "K1" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 12 ;
+NET "reset_mcu_b_pin" LOC = "F1" | IOSTANDARD = "LVCMOS33" | PULLUP ;
+
+NET "gclk_p_pin" LOC = "H2" | IOSTANDARD = "LVDS_33" | DIFF_TERM = "TRUE" ; +NET "gclk_n_pin" LOC = "H1" | IOSTANDARD = "LVDS_33" | DIFF_TERM = "TRUE" ;
+
+NET "eim_bclk" LOC = "C9" | IOSTANDARD = "LVCMOS33" ;
+NET "eim_cs0_n" LOC = "B11" | IOSTANDARD = "LVCMOS33" ;
+
+NET "eim_da<0>" LOC = "G9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET "eim_da<1>" LOC = "A10" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET "eim_da<2>" LOC = "F9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET "eim_da<3>" LOC = "B9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET "eim_da<4>" LOC = "E13" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET "eim_da<5>" LOC = "F13" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET "eim_da<6>" LOC = "A9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET "eim_da<7>" LOC = "A8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET "eim_da<8>" LOC = "B8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET "eim_da<9>" LOC = "D8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET "eim_da<10>" LOC = "D11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET "eim_da<11>" LOC = "C8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET "eim_da<12>" LOC = "C7" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET "eim_da<13>" LOC = "C11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET "eim_da<14>" LOC = "C4" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET "eim_da<15>" LOC = "B6" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+
+NET "eim_lba_n" LOC = "B14" | IOSTANDARD = "LVCMOS33" ;
+NET "eim_wr_n" LOC = "C14" | IOSTANDARD = "LVCMOS33" ;
+NET "eim_oe_n" LOC = "C10" | IOSTANDARD = "LVCMOS33" ;
+NET "eim_wait_n" LOC = "A7" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+
+
+#-------------------------------------------------------------------------------
+# EIM Input Timing
+#-------------------------------------------------------------------------------
+NET "eim_cs0_n" TNM = "TNM_EIM_IN" ; +NET "eim_da<*>" TNM = "TNM_EIM_IN" ;
+NET "eim_lba_n" TNM = "TNM_EIM_IN" ;
+NET "eim_wr_n" TNM = "TNM_EIM_IN" ;
+NET "eim_oe_n" TNM = "TNM_EIM_IN" ;
+ +TIMEGRP "TNM_EIM_IN" OFFSET = IN 9.75 ns VALID 16.0 ns BEFORE "eim_bclk" RISING ;
+
+
+#-------------------------------------------------------------------------------
+# EIM Output Timing
+#------------------------------------------------------------------------------- +NET "eim_da<*>" TNM = "TNM_EIM_OUT" ;
+NET "eim_wait_n" TNM = "TNM_EIM_OUT" ;
+
+TIMEGRP "TNM_EIM_OUT" OFFSET = OUT 13.0 ns AFTER "eim_bclk" FALLING ;
+
+
+#-------------------------------------------------------------------------------
+# CDC Paths
+#-------------------------------------------------------------------------------
+INST "eim/eim_cdc/cdc_eim_sys/src_ff" TNM = "TNM_from_bclk" ;
+INST "eim/eim_cdc/cdc_eim_sys/src_latch*" TNM = "TNM_from_bclk" ;
+INST "eim/eim_cdc/cdc_eim_sys/ff_sync*" TNM = "TNM_to_sys_clk" ; +INST "eim/eim_cdc/cdc_eim_sys/dst_latch*" TNM = "TNM_to_sys_clk" ;
+
+INST "eim/eim_cdc/cdc_sys_eim/src_ff" TNM = "TNM_from_sys_clk" ;
+INST "eim/eim_cdc/cdc_sys_eim/src_latch*" TNM = "TNM_from_sys_clk" ;
+INST "eim/eim_cdc/cdc_sys_eim/ff_sync*" TNM = "TNM_to_bclk" ; +INST "eim/eim_cdc/cdc_sys_eim/dst_latch*" TNM = "TNM_to_bclk" ;
+
+TIMESPEC "TS_bclk_2_sys_clk" = FROM "TNM_from_bclk" TO "TNM_to_sys_clk" TIG ;
+TIMESPEC "TS_sys_clk_2_bclk" = FROM "TNM_from_sys_clk" TO "TNM_to_bclk" TIG ;
+
+
+#-------------------------------------------------------------------------------
+# End-of-File
+#-------------------------------------------------------------------------------
diff --git a/rtl/src/verilog/cdc_bus_pulse.v b/rtl/src/verilog/cdc_bus_pulse.v new file mode 100644 index 0000000..104bfa5 --- /dev/null +++ b/rtl/src/verilog/cdc_bus_pulse.v @@ -0,0 +1,114 @@ +`timescale 1ns / 1ps
+
+module cdc_bus_pulse
+ (
+ src_clk, src_din, src_req,
+ dst_clk, dst_dout, dst_pulse
+ );
+
+ /* This module is based on design suggested on page 27 of an article titled
+ "Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog"
+ by Clifford E. Cummings (Sunburst Design, Inc.)
+ */
+
+ //
+ // Parameters
+ //
+ parameter DATA_WIDTH = 32; // width of data bus
+
+
+ //
+ // Ports
+ //
+ input wire src_clk; // source domain clock
+ input wire [DATA_WIDTH-1:0] src_din; // data from source clock domain
+ input wire src_req; // start transfer pulse from source clock domain
+
+ input wire dst_clk; // destination domain clock
+ output wire [DATA_WIDTH-1:0] dst_dout; // data to destination clock domain
+ output wire dst_pulse; // transfer done pulse to destination clock domain
+
+
+ //
+ // Source Side Registers
+ //
+ reg src_ff = 1'b0; // transfer request flag
+ reg [DATA_WIDTH-1:0] src_latch = {DATA_WIDTH{1'bX}}; // source data buffer
+
+
+ //
+ // Source Request Handler
+ //
+ always @(posedge src_clk)
+ //
+ if (src_req) begin // transfer request pulse?
+ src_ff <= ~src_ff; // toggle transfer request flag...
+ src_latch <= src_din; // ... and capture data in source buffer
+ end
+
+
+ //
+ // Source -> Destination Flag Sync Logic
+ //
+
+ /* ISE may decide to infer SRL here, so we explicitly instantiate slice registers. */
+
+ wire flag_sync_first; // first FF output
+ wire flag_sync_second; // second FF output
+ wire flag_sync_third; // third FF output
+ wire flag_sync_pulse; // flag toggle detector output
+
+ FDCE ff_sync_first
+ (
+ .C (dst_clk),
+ .D (src_ff), // capture flag from another clock domain + .Q (flag_sync_first), // metastability can occur here
+ .CLR (1'b0),
+ .CE (1'b1) + );
+ FDCE ff_sync_second
+ (
+ .C (dst_clk),
+ .D (flag_sync_first), // synchronize captured flag to remove metastability + .Q (flag_sync_second), // and pass it to another flip-flop
+ .CLR (1'b0),
+ .CE (1'b1) + );
+ FDCE ff_sync_third
+ (
+ .C (dst_clk),
+ .D (flag_sync_second), // delay synchronized flag in another flip-flip, because we need + .Q (flag_sync_third), // two synchronized flag values (current and delayed) to detect its change
+ .CLR (1'b0),
+ .CE (1'b1) + );
+
+ // when delayed flag value differs from its current value, it was changed
+ // by the source side, so there must have been a transfer request
+ assign flag_sync_pulse = flag_sync_second ^ flag_sync_third;
+
+
+ //
+ // Destination Side Registers
+ //
+ reg dst_pulse_reg = 1'b0; // transfer done flag
+ reg [DATA_WIDTH-1:0] dst_latch = {DATA_WIDTH{1'bX}}; // destination data buffer
+
+ assign dst_pulse = dst_pulse_reg;
+ assign dst_dout = dst_latch;
+
+ //
+ // Destination Request Handler
+ //
+ always @(posedge dst_clk) begin
+ //
+ dst_pulse_reg <= flag_sync_pulse; // generate pulse if flag change was detected
+ //
+ if (flag_sync_pulse) dst_latch <= src_latch; // by the time destination side receives synchronized
+ // // flag value, data should be stable, we can safely
+ // // capture and store it in the destination buffer
+ //
+ end
+
+
+endmodule
diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v new file mode 100644 index 0000000..2db2a05 --- /dev/null +++ b/rtl/src/verilog/core_selector.v @@ -0,0 +1,112 @@ +`timescale 1ns / 1ps
+
+module core_selector
+ (
+ sys_clk, sys_rst,
+ sys_eim_addr, sys_eim_wr, sys_eim_rd, + sys_eim_dout, sys_eim_din
+ );
+
+ //
+ // Ports
+ //
+ input wire sys_clk;
+ input wire sys_rst;
+
+ input wire [13: 0] sys_eim_addr;
+ input wire sys_eim_wr;
+ input wire sys_eim_rd; + input wire [31: 0] sys_eim_dout;
+ output wire [31: 0] sys_eim_din;
+
+
+ //
+ // Internal Registers
+ //
+ reg [31: 0] reg_x = {32{1'b0}};
+ reg [31: 0] reg_y = {32{1'b0}};
+ reg [15: 0] reg_ctl = {16{1'b0}};
+ reg [31: 0] sys_eim_din_reg = {32{1'b0}};
+
+
+ //
+ // Parameters
+ //
+ localparam ADDER_BASE_ADDR = 12'h321; // upper 12 bits of address
+ localparam ADDER_OFFSET_REG_X = 2'd0; // X
+ localparam ADDER_OFFSET_REG_Y = 2'd1; // Y
+ localparam ADDER_OFFSET_REG_Z = 2'd2; // Z
+ localparam ADDER_OFFSET_REG_SC = 2'd3; // {STATUS, CONTROL}
+
+
+ /* This flag detects whether adder core is being addressed. */
+ wire eim_access_adder = (sys_eim_addr[13:2] == ADDER_BASE_ADDR) ? 1'b1 : 1'b0;
+
+ /* These flags detect whether write or read access is requested. */
+ wire eim_access_write = sys_eim_wr & eim_access_adder;
+ wire eim_access_read = sys_eim_rd & eim_access_adder;
+
+
+ //
+ // Write Request Handler
+ //
+ always @(posedge sys_clk)
+ //
+ if (sys_rst) begin
+ reg_x <= {32{1'b0}};
+ reg_y <= {32{1'b0}};
+ reg_ctl <= {16{1'b0}};
+ end else if (eim_access_write) begin
+ //
+ case (sys_eim_addr[1:0])
+ ADDER_OFFSET_REG_X: reg_x <= sys_eim_dout;
+ ADDER_OFFSET_REG_Y: reg_y <= sys_eim_dout;
+ ADDER_OFFSET_REG_SC: reg_ctl <= sys_eim_dout[15: 0];
+ endcase
+ //
+ end
+
+
+ //
+ // Read Request Handler
+ //
+ wire [31: 0] reg_z;
+ wire [15: 0] reg_sts;
+
+ always @(posedge sys_clk)
+ //
+ if (sys_rst) sys_eim_din_reg <= {32{1'b0}};
+ //
+ else if (eim_access_read) begin
+ //
+ case (sys_eim_addr[1:0])
+ ADDER_OFFSET_REG_X: sys_eim_din_reg <= reg_x;
+ ADDER_OFFSET_REG_Y: sys_eim_din_reg <= reg_y;
+ ADDER_OFFSET_REG_Z: sys_eim_din_reg <= reg_z;
+ ADDER_OFFSET_REG_SC: sys_eim_din_reg <= {reg_sts, reg_ctl};
+ endcase
+ //
+ end
+
+ assign sys_eim_din = sys_eim_din_reg;
+
+
+ //
+ // Demo Adder Core
+ //
+ demo_adder adder_core
+ (
+ .clk (sys_clk),
+ .rst (sys_rst),
+
+ .x (reg_x),
+ .y (reg_y),
+ .z (reg_z),
+
+ .ctl (reg_ctl),
+ .sts (reg_sts)
+ );
+
+
+
+endmodule
diff --git a/rtl/src/verilog/demo_adder.v b/rtl/src/verilog/demo_adder.v new file mode 100644 index 0000000..a86f114 --- /dev/null +++ b/rtl/src/verilog/demo_adder.v @@ -0,0 +1,66 @@ +`timescale 1ns / 1ps
+
+module demo_adder
+ (
+ clk, rst,
+ x, y, z,
+ ctl, sts
+ );
+
+ //
+ // Ports
+ //
+ input wire clk; // clock
+ input wire rst; // reset
+
+ input wire [31: 0] x; // x
+ input wire [31: 0] y; // y
+ output wire [31: 0] z; // z = x + y
+
+ input wire [15: 0] ctl; // control
+ output wire [15: 0] sts; // status
+
+
+ //
+ // Internal Registers
+ //
+ reg [31: 0] z_reg = {32{1'b0}};
+ reg [15: 0] sts_reg = {16{1'b0}};
+ reg [15: 0] ctl_dly = {16{1'b0}};
+
+ assign z = z_reg;
+ assign sts = sts_reg;
+
+
+ //
+ // Control Logic
+ //
+ always @(posedge clk)
+ //
+ if (rst) ctl_dly <= {16{1'b0}};
+ else ctl_dly <= ctl;
+
+ /* This flag is set whenever different value is written to control register. */
+
+ wire adder_go = (ctl != ctl_dly) ? 1'b1 : 1'b0;
+
+
+ //
+ // Adder Logic
+ //
+ always @(posedge clk)
+ //
+ if (rst) z_reg <= {32{1'b0}};
+ else if (adder_go) z_reg <= x + y;
+
+
+ //
+ // Status Logic
+ //
+ always @(posedge clk)
+ //
+ if (rst) sts_reg <= {16{1'b0}};
+ else if (adder_go) sts_reg <= ctl;
+
+
+endmodule
diff --git a/rtl/src/verilog/eim_arbiter.v b/rtl/src/verilog/eim_arbiter.v new file mode 100644 index 0000000..247ff69 --- /dev/null +++ b/rtl/src/verilog/eim_arbiter.v @@ -0,0 +1,247 @@ +`timescale 1ns / 1ps
+
+module eim_arbiter
+ (
+ eim_bclk, eim_cs0_n, eim_da, + eim_lba_n, eim_wr_n, + eim_oe_n, eim_wait_n,
+
+ sys_clk,
+ sys_addr,
+ sys_wren, sys_data_out,
+ sys_rden, sys_data_in
+ );
+
+
+ //
+ // Ports
+ //
+ input wire eim_bclk; // | eim bus
+ input wire eim_cs0_n; // |
+ inout wire [15: 0] eim_da; // | + input wire eim_lba_n; // |
+ input wire eim_wr_n; // | + input wire eim_oe_n; // |
+ output wire eim_wait_n; // |
+
+ input wire sys_clk; // system clock
+
+ output wire [13: 0] sys_addr; // | user bus
+ output wire sys_wren; // |
+ output wire [31: 0] sys_data_out; // |
+ output wire sys_rden; // |
+ input wire [31: 0] sys_data_in; // |
+
+
+ //
+ // Data/Address PHY
+ //
+
+ /* PHY is needed to control bi-directional address/data bus. */
+
+ wire [15: 0] da_ro; // value read from pins
+ reg [15: 0] da_di; // value drives onto pins
+
+ eim_da_phy da_phy
+ (
+ .buf_io (eim_da), // <-- connect directly top-level port
+ .buf_di (da_di),
+ .buf_ro (da_ro),
+ .buf_t (eim_oe_n) // <-- driven by EIM directly
+ );
+
+
+ //
+ // FSM
+ //
+ localparam EIM_FSM_STATE_INIT = 5'b0_0_000; // arbiter is idle
+
+ localparam EIM_FSM_STATE_WRITE_START = 5'b1_1_000; // got address to write at
+ localparam EIM_FSM_STATE_WRITE_LSB = 5'b1_1_001; // got lower 16 bits of data to write
+ localparam EIM_FSM_STATE_WRITE_MSB = 5'b1_1_010; // got upper 16 bits of data to write
+ localparam EIM_FSM_STATE_WRITE_WAIT = 5'b1_1_100; // request to user-side logic sent
+ localparam EIM_FSM_STATE_WRITE_DONE = 5'b1_1_111; // user-side logic acknowledged transaction
+
+ localparam EIM_FSM_STATE_READ_START = 5'b1_0_000; // got address to read from
+ localparam EIM_FSM_STATE_READ_WAIT = 5'b1_0_100; // request to user-side logic sent
+ localparam EIM_FSM_STATE_READ_READY = 5'b1_0_011; // got acknowledge from user logic
+ localparam EIM_FSM_STATE_READ_LSB = 5'b1_0_001; // returned lower 16 bits to master
+ localparam EIM_FSM_STATE_READ_MSB = 5'b1_0_010; // returned upper 16 bits to master
+ localparam EIM_FSM_STATE_READ_DONE = 5'b1_0_111; // transaction complete
+
+ reg [ 4: 0] eim_fsm_state = EIM_FSM_STATE_INIT; // fsm state
+ reg [13: 0] eim_addr_latch = {14{1'bX}}; // transaction address
+ reg [15: 0] eim_write_lsb_latch = {16{1'bX}}; // lower 16 bits of data to write
+
+ /* These flags are used to wake up from INIT state. */
+ wire eim_write_start_flag = (eim_lba_n == 1'b0) && (eim_wr_n == 1'b0) && (da_ro[1:0] == 2'b00);
+ wire eim_read_start_flag = (eim_lba_n == 1'b0) && (eim_wr_n == 1'b1) && (da_ro[1:0] == 2'b00);
+
+ /* These are transaction response flag and data from user-side logic. */
+ wire eim_user_ack;
+ wire [31: 0] eim_user_data;
+
+ /* FSM is reset whenever Chip Select is de-asserted. */
+
+ //
+ // FSM Transition Logic
+ //
+ always @(posedge eim_bclk or posedge eim_cs0_n) begin
+ //
+ if (eim_cs0_n == 1'b1) eim_fsm_state <= EIM_FSM_STATE_INIT;
+ //
+ else begin
+ //
+ case (eim_fsm_state)
+ //
+ // INIT -> WRITE, INIT -> READ
+ //
+ EIM_FSM_STATE_INIT: begin
+ if (eim_write_start_flag) eim_fsm_state <= EIM_FSM_STATE_WRITE_START;
+ if (eim_read_start_flag) eim_fsm_state <= EIM_FSM_STATE_READ_START;
+ end
+ //
+ // WRITE
+ //
+ EIM_FSM_STATE_WRITE_START: eim_fsm_state <= EIM_FSM_STATE_WRITE_LSB;
+ //
+ EIM_FSM_STATE_WRITE_LSB: eim_fsm_state <= EIM_FSM_STATE_WRITE_MSB;
+ //
+ EIM_FSM_STATE_WRITE_MSB: eim_fsm_state <= EIM_FSM_STATE_WRITE_WAIT;
+ //
+ EIM_FSM_STATE_WRITE_WAIT:
+ if (eim_user_ack) eim_fsm_state <= EIM_FSM_STATE_WRITE_DONE;
+ //
+ EIM_FSM_STATE_WRITE_DONE: eim_fsm_state <= EIM_FSM_STATE_INIT;
+ //
+ // READ
+ //
+ EIM_FSM_STATE_READ_START: eim_fsm_state <= EIM_FSM_STATE_READ_WAIT;
+ //
+ EIM_FSM_STATE_READ_WAIT:
+ if (eim_user_ack) eim_fsm_state <= EIM_FSM_STATE_READ_READY;
+ //
+ EIM_FSM_STATE_READ_READY: eim_fsm_state <= EIM_FSM_STATE_READ_LSB;
+ //
+ EIM_FSM_STATE_READ_LSB: eim_fsm_state <= EIM_FSM_STATE_READ_MSB;
+ //
+ EIM_FSM_STATE_READ_MSB: eim_fsm_state <= EIM_FSM_STATE_READ_DONE;
+ //
+ EIM_FSM_STATE_READ_DONE: eim_fsm_state <= EIM_FSM_STATE_INIT;
+ //
+ //
+ //
+ default: eim_fsm_state <= EIM_FSM_STATE_INIT;
+ //
+ endcase
+ //
+ end
+ //
+ end
+
+
+ //
+ // Address Latch
+ //
+ always @(posedge eim_bclk)
+ //
+ if ((eim_fsm_state == EIM_FSM_STATE_INIT) && (eim_write_start_flag || eim_read_start_flag))
+ eim_addr_latch <= da_ro[15:2];
+
+
+ //
+ // Additional Write Logic
+ //
+ always @(posedge eim_bclk)
+ //
+ if (eim_fsm_state == EIM_FSM_STATE_WRITE_START)
+ eim_write_lsb_latch <= da_ro;
+
+
+ //
+ // Additional Read Logic
+ //
+
+ /* Note that this stuff operates on falling clock edge, because the cpu
+ * samples our bi-directional data bus on rising clock edge.
+ */
+
+ always @(negedge eim_bclk or posedge eim_cs0_n)
+ //
+ if (eim_cs0_n == 1'b1) da_di <= {16{1'bX}}; // don't care what to drive
+ else begin
+ //
+ if (eim_fsm_state == EIM_FSM_STATE_READ_LSB) da_di <= eim_user_data[15: 0]; // drive lower 16 bits at first...
+ if (eim_fsm_state == EIM_FSM_STATE_READ_MSB) da_di <= eim_user_data[31:16]; // ...then drive upper 16 bits
+ //
+ end
+
+
+ //
+ // Wait Logic
+ //
+
+ /* Note that this stuff operates on falling clock edge, because the cpu
+ * samples our WAIT_N flag on rising clock edge.
+ */
+
+ reg eim_wait_reg = 1'b0;
+
+ always @(negedge eim_bclk or posedge eim_cs0_n)
+ //
+ if (eim_cs0_n == 1'b1) eim_wait_reg <= 1'b0; // clear wait
+ else begin
+ //
+ if (eim_fsm_state == EIM_FSM_STATE_WRITE_START) eim_wait_reg <= 1'b1; // start waiting for write to complete
+ if (eim_fsm_state == EIM_FSM_STATE_READ_START) eim_wait_reg <= 1'b1; // start waiting for read to complete
+ //
+ if (eim_fsm_state == EIM_FSM_STATE_WRITE_DONE) eim_wait_reg <= 1'b0; // write transaction done
+ if (eim_fsm_state == EIM_FSM_STATE_READ_READY) eim_wait_reg <= 1'b0; // read transaction done
+ //
+ if (eim_fsm_state == EIM_FSM_STATE_INIT) eim_wait_reg <= 1'b0; // fsm is idle, no need to wait any more
+ //
+ end
+
+ assign eim_wait_n = ~eim_wait_reg;
+
+
+ /* These flags are used to generate 1-cycle pulses to trigger CDC transaction.
+ * Note that FSM goes from WRITE_LSB to WRITE_MSB and from READ_START to READ_WAIT
+ * unconditionally, so these flags will always be active for 1 cycle only, which
+ * is exactly what we need.
+ */
+
+ wire arbiter_write_req_pulse = (eim_fsm_state == EIM_FSM_STATE_WRITE_LSB) ? 1'b1 : 1'b0;
+ wire arbiter_read_req_pulse = (eim_fsm_state == EIM_FSM_STATE_READ_START) ? 1'b1 : 1'b0;
+
+ //
+ // CDC Block
+ //
+
+ /* This block is used to transfer request data from BCLK clock domain to SYS_CLK clock domain and
+ * then transfer acknowledge from SYS_CLK to BCLK clock domain in return. Af first 1+1+14+32 = 48 bits
+ * are transfered, these are: write flag, read flag, address, write data. During read transaction
+ * some bogus write data is passed, which is not used later anyway. During read requests 32 bits of data
+ * are returned, during write requests 32 bits of bogus data are returned, that are never used later.
+ */
+
+ eim_arbiter_cdc eim_cdc
+ (
+ .eim_clk (eim_bclk),
+
+ .eim_req (arbiter_write_req_pulse | arbiter_read_req_pulse),
+ .eim_ack (eim_user_ack),
+
+ .eim_din ({arbiter_write_req_pulse, arbiter_read_req_pulse, eim_addr_latch, da_ro, eim_write_lsb_latch}),
+ .eim_dout (eim_user_data),
+
+ .sys_clk (sys_clk),
+ .sys_addr (sys_addr),
+ .sys_wren (sys_wren),
+ .sys_data_out (sys_data_out),
+ .sys_rden (sys_rden),
+ .sys_data_in (sys_data_in)
+ );
+
+
+endmodule
diff --git a/rtl/src/verilog/eim_arbiter_cdc.v b/rtl/src/verilog/eim_arbiter_cdc.v new file mode 100644 index 0000000..6a60552 --- /dev/null +++ b/rtl/src/verilog/eim_arbiter_cdc.v @@ -0,0 +1,106 @@ +`timescale 1ns / 1ps
+
+module eim_arbiter_cdc
+ (
+ eim_clk, eim_req, eim_ack, eim_din, eim_dout,
+ sys_clk, sys_addr,
+ sys_wren, sys_data_out,
+ sys_rden, sys_data_in
+ );
+
+
+ input wire eim_clk; // eim clock
+ input wire eim_req; // eim transaction request
+ output wire eim_ack; // eim transaction acknowledge
+ input wire [47: 0] eim_din; // data from cpu to fpga (write access)
+ output wire [31: 0] eim_dout; // data from fpga to cpu (read access)
+
+ input wire sys_clk; // user internal clock
+ output wire [13: 0] sys_addr; // user access address
+ output wire sys_wren; // user write flag
+ output wire [31: 0] sys_data_out; // user write data
+ output wire sys_rden; // user read flag
+ input wire [31: 0] sys_data_in; // user read data
+
+
+ //
+ // EIM_CLK -> SYS_CLK Request
+ //
+ wire sys_req; // request pulse in sys_clk clock domain
+ wire [47: 0] sys_dout; // transaction data in sys_clk clock domain
+
+ cdc_bus_pulse #
+ (
+ .DATA_WIDTH (48) // {write, read, addr, data}
+ )
+ cdc_eim_sys
+ (
+ .src_clk (eim_clk),
+ .src_din (eim_din),
+ .src_req (eim_req),
+
+ .dst_clk (sys_clk),
+ .dst_dout (sys_dout),
+ .dst_pulse (sys_req)
+ );
+
+
+ //
+ // Output Registers
+ //
+ reg [13: 0] sys_addr_reg = {14{1'bX}}; //
+ reg sys_wren_reg = 1'b0; //
+ reg [31: 0] sys_data_out_reg = {32{1'bX}}; //
+ reg sys_rden_reg = 1'b0; //
+
+ assign sys_addr = sys_addr_reg;
+ assign sys_wren = sys_wren_reg;
+ assign sys_data_out = sys_data_out_reg;
+ assign sys_rden = sys_rden_reg;
+
+
+ //
+ // System (User) Clock Access Handler
+ //
+ always @(posedge sys_clk)
+ //
+ if (sys_req) begin // request detected?
+ sys_wren_reg <= sys_dout[47]; // set write flag if needed
+ sys_addr_reg <= sys_dout[45:32]; // set operation address
+ sys_data_out_reg <= sys_dout[31: 0]; // set data to write
+ sys_rden_reg <= sys_dout[46]; // set read flag if needed
+ end else begin // no request active
+ sys_wren_reg <= 1'b0; // clear write flag
+ sys_rden_reg <= 1'b0; // clear read flag
+ end
+
+
+ //
+ // System Request 2-cycle delay to compensate registered mux delay in user-side logic
+ //
+ reg [ 1: 0] sys_req_dly = 2'b00;
+
+ always @(posedge sys_clk)
+ sys_req_dly <= {sys_req_dly[0], sys_req};
+
+
+ //
+ // SYS_CLK -> EIM_CLK Acknowledge
+ //
+ cdc_bus_pulse #
+ (
+ .DATA_WIDTH (32) // {data}
+ )
+ cdc_sys_eim
+ (
+ .src_clk (sys_clk),
+ .src_din (sys_data_in),
+ .src_req (sys_req_dly[1]),
+
+ .dst_clk (eim_clk),
+ .dst_dout (eim_dout),
+ .dst_pulse (eim_ack)
+ );
+
+
+endmodule
diff --git a/rtl/src/verilog/eim_da_phy.v b/rtl/src/verilog/eim_da_phy.v new file mode 100644 index 0000000..9fe0c3b --- /dev/null +++ b/rtl/src/verilog/eim_da_phy.v @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps
+
+module eim_da_phy
+ (
+ buf_io,
+ buf_di, buf_ro,
+ buf_t
+ );
+
+ //
+ // Parameters
+ //
+ parameter BUS_WIDTH = 16;
+
+ //
+ // Ports
+ //
+ inout wire [BUS_WIDTH-1:0] buf_io; // connect directly to top-level pins
+ input wire [BUS_WIDTH-1:0] buf_di; // drive input (value driven onto pins)
+ output wire [BUS_WIDTH-1:0] buf_ro; // receiver output (value read from pins)
+ input wire buf_t; // tristate control (driver is disabled during tristate)
+
+ //
+ // IOBUFs
+ //
+ genvar i; + generate for (i=0; i<BUS_WIDTH; i=i+1)
+ begin: eim_da + //
+ IOBUF #
+ (
+ .IOSTANDARD ("LVCMOS33"), + .DRIVE (12), + .SLEW ("FAST") + )
+ IOBUF_inst
+ (
+ .IO (buf_io[i]), + .O (buf_ro[i]), + .I (buf_di[i]), + .T (buf_t) + );
+ // + end + endgenerate
+
+endmodule
diff --git a/rtl/src/verilog/eim_indicator.v b/rtl/src/verilog/eim_indicator.v new file mode 100644 index 0000000..1324afb --- /dev/null +++ b/rtl/src/verilog/eim_indicator.v @@ -0,0 +1,36 @@ +`timescale 1ns / 1ps
+
+module eim_indicator
+ (
+ sys_clk, sys_rst,
+ eim_active,
+ led_out
+ );
+
+ //
+ // Ports
+ //
+ input wire sys_clk;
+ input wire sys_rst;
+ input wire eim_active;
+ output wire led_out;
+
+ //
+ // Parameters
+ //
+ localparam CNT_BITS = 24; // led will be dim for 2**(24-1) = 8388608 ticks, which is ~100 ms @ 80 MHz.
+
+ //
+ // Counter
+ //
+ reg [CNT_BITS-1:0] cnt;
+
+ always @(posedge sys_clk)
+ //
+ if (sys_rst) cnt <= {CNT_BITS{1'b0}};
+ else if (cnt > {CNT_BITS{1'b0}}) cnt <= cnt - 1'b1;
+ else if (eim_active) cnt <= {CNT_BITS{1'b1}};
+
+ assign led_out = ~cnt[CNT_BITS-1];
+
+endmodule
diff --git a/rtl/src/verilog/novena_baseline_top.v b/rtl/src/verilog/novena_baseline_top.v new file mode 100644 index 0000000..a62f311 --- /dev/null +++ b/rtl/src/verilog/novena_baseline_top.v @@ -0,0 +1,132 @@ +`timescale 1ns / 1ps
+
+module novena_baseline_top
+ (
+ gclk_p_pin, gclk_n_pin, + + eim_bclk, eim_cs0_n, eim_da, + eim_lba_n, eim_wr_n, + eim_oe_n, eim_wait_n, + + reset_mcu_b_pin, + apoptosis_pin, + led_pin
+ );
+
+ // + // Top-Levl Ports + // + input wire gclk_p_pin; // general-purpose 50 MHz LVDS clock + input wire gclk_n_pin; // + + input wire eim_bclk; // burst clock from cpu + input wire eim_cs0_n; // chip select (active low) + inout wire [15: 0] eim_da; // bi-directional address/data bus + input wire eim_lba_n; // latch address signal (active low) + input wire eim_wr_n; // write enable signal (active low) + input wire eim_oe_n; // output enable signal (active low) + output wire eim_wait_n; // wait signal (active low) + + input wire reset_mcu_b_pin; // this must be configured as input w/pullup
+ // not to kill the cpu after configuration + output wire apoptosis_pin; // not used, tied to 0 + output wire led_pin; // visual activity indicator
+
+
+ //
+ // Clock Manager
+ //
+
+ /* Clock manager is used to buffer BCLK and also generate SYS_CLK from GCLK. */
+
+ wire sys_clk;
+ wire sys_rst;
+
+ wire eim_bclk_buf;
+
+ novena_clkmgr clkmgr
+ (
+ .gclk_p (gclk_p_pin),
+ .gclk_n (gclk_n_pin),
+ + .reset_mcu_b (reset_mcu_b_pin),
+ + .sys_clk (sys_clk),
+ .sys_rst (sys_rst),
+
+ .bclk_in (eim_bclk),
+ .bclk_out (eim_bclk_buf)
+ );
+
+
+ //
+ // EIM Arbiter
+ //
+
+ /* EIM arbiter handles EIM access and transfers it into `sys_clk' clock domain. */
+
+ wire [13: 0] sys_eim_addr; + wire sys_eim_wr;
+ wire sys_eim_rd; + wire [31: 0] sys_eim_dout; + wire [31: 0] sys_eim_din;
+
+ eim_arbiter eim
+ (
+ .eim_bclk (eim_bclk_buf),
+ .eim_cs0_n (eim_cs0_n),
+ .eim_da (eim_da), + .eim_lba_n (eim_lba_n),
+ .eim_wr_n (eim_wr_n), + .eim_oe_n (eim_oe_n),
+ .eim_wait_n (eim_wait_n),
+
+ .sys_clk (sys_clk),
+
+ .sys_addr (sys_eim_addr),
+ .sys_wren (sys_eim_wr),
+ .sys_data_out (sys_eim_dout),
+ .sys_rden (sys_eim_rd),
+ .sys_data_in (sys_eim_din)
+ );
+
+
+ //
+ // Core Selector (MUX)
+ //
+
+ /* This multiplexor is used to map demo adder registers somewhere into EIM address space. */
+
+ core_selector mux
+ (
+ .sys_clk (sys_clk),
+ .sys_rst (sys_rst),
+
+ .sys_eim_addr (sys_eim_addr),
+ .sys_eim_wr (sys_eim_wr),
+ .sys_eim_rd (sys_eim_rd),
+ + .sys_eim_dout (sys_eim_dout),
+ .sys_eim_din (sys_eim_din)
+ );
+
+
+ //
+ // LED Driver
+ //
+ eim_indicator led
+ (
+ .sys_clk (sys_clk),
+ .sys_rst (sys_rst),
+ .eim_active (sys_eim_wr | sys_eim_rd),
+ .led_out (led_pin)
+ );
+
+
+ //
+ // Unused
+ //
+ assign apoptosis_pin = 1'b0;
+
+
+endmodule
diff --git a/rtl/src/verilog/novena_clkmgr.v b/rtl/src/verilog/novena_clkmgr.v new file mode 100644 index 0000000..2f8c02f --- /dev/null +++ b/rtl/src/verilog/novena_clkmgr.v @@ -0,0 +1,100 @@ +`timescale 1ns / 1ps
+
+module novena_clkmgr
+ (
+ gclk_p, gclk_n, + reset_mcu_b, + sys_clk, sys_rst,
+ bclk_in, bclk_out
+ );
+
+ //
+ // Ports
+ //
+ input wire gclk_p; // signal from clock pins
+ input wire gclk_n; //
+ + input wire reset_mcu_b; // cpu reset (async)
+ + output wire sys_clk; // buffered system clock output
+ output wire sys_rst; // system reset output (sync)
+
+ input wire bclk_in; // signal from clock pin
+ output wire bclk_out; // buffered clock output
+
+
+ //
+ // IBUFGDS
+ //
+ (* BUFFER_TYPE="NONE" *)
+ wire gclk;
+ + IBUFGDS IBUFGDS_gclk + ( + .I (gclk_p), + .IB (gclk_n), + .O (gclk) + );
+
+
+ //
+ // DCM
+ //
+ wire dcm_reset; // dcm reset
+ wire dcm_locked; // output clock valid
+ wire gclk_missing; // no input clock
+
+ clkmgr_dcm dcm
+ (
+ .CLK_IN1 (gclk),
+ .RESET (dcm_reset),
+ .INPUT_CLK_STOPPED (gclk_missing),
+
+ .CLK_OUT1 (sys_clk),
+ .CLK_VALID (dcm_locked)
+ );
+
+
+ // + // DCM Reset Logic + //
+
+ /* DCM should be reset on power-up, when input clock is stopped or when the CPU gets reset. */
+ + reg [15: 0] dcm_rst_shreg = {16{1'b1}}; // 16-bit shift register
+ + always @(posedge gclk or negedge reset_mcu_b or posedge gclk_missing) + // + if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1)) dcm_rst_shreg <= {16{1'b1}}; + else dcm_rst_shreg <= {dcm_rst_shreg[14:0], 1'b0}; + + assign dcm_reset = dcm_rst_shreg[15];
+
+
+ // + // System Reset Logic + //
+
+ /* System reset is asserted for 16 cycles whenever DCM aquires lock. */
+ + reg [15: 0] sys_rst_shreg = {16{1'b1}}; // 16-bit shift register + + always @(posedge sys_clk or negedge reset_mcu_b or posedge gclk_missing or negedge dcm_locked) + // + if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1) || (dcm_locked == 1'b0)) sys_rst_shreg <= {16{1'b1}}; + else if (dcm_locked == 1'b1) sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b0}; + + assign sys_rst = sys_rst_shreg[15];
+
+
+ //
+ // BCLK BUFG
+ //
+ BUFG BUFG_BCLK
+ (
+ .I (bclk_in),
+ .O (bclk_out)
+ );
+
+
+endmodule
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