simcmds.tcl « timing « simulation « clkmgr_dcm « ipcore « src « rtl - test/novena_base - Cryptech Novena FPGA baseline

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path: root/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl

blob: 14523af619e9d4d7b934466dcc17f86e04176b9c (plain) (blame)

# file: simcmds.tcl

# create the simulation script
vcd dumpfile isim.vcd
vcd dumpvars -m /clkmgr_dcm_tb -l 0
wave add /
run 50000ns
quit