diff options
Diffstat (limited to 'rtl/src/verilog/novena_baseline_top.v')
-rw-r--r-- | rtl/src/verilog/novena_baseline_top.v | 132 |
1 files changed, 132 insertions, 0 deletions
diff --git a/rtl/src/verilog/novena_baseline_top.v b/rtl/src/verilog/novena_baseline_top.v new file mode 100644 index 0000000..a62f311 --- /dev/null +++ b/rtl/src/verilog/novena_baseline_top.v @@ -0,0 +1,132 @@ +`timescale 1ns / 1ps
+
+module novena_baseline_top
+ (
+ gclk_p_pin, gclk_n_pin, + + eim_bclk, eim_cs0_n, eim_da, + eim_lba_n, eim_wr_n, + eim_oe_n, eim_wait_n, + + reset_mcu_b_pin, + apoptosis_pin, + led_pin
+ );
+
+ // + // Top-Levl Ports + // + input wire gclk_p_pin; // general-purpose 50 MHz LVDS clock + input wire gclk_n_pin; // + + input wire eim_bclk; // burst clock from cpu + input wire eim_cs0_n; // chip select (active low) + inout wire [15: 0] eim_da; // bi-directional address/data bus + input wire eim_lba_n; // latch address signal (active low) + input wire eim_wr_n; // write enable signal (active low) + input wire eim_oe_n; // output enable signal (active low) + output wire eim_wait_n; // wait signal (active low) + + input wire reset_mcu_b_pin; // this must be configured as input w/pullup
+ // not to kill the cpu after configuration + output wire apoptosis_pin; // not used, tied to 0 + output wire led_pin; // visual activity indicator
+
+
+ //
+ // Clock Manager
+ //
+
+ /* Clock manager is used to buffer BCLK and also generate SYS_CLK from GCLK. */
+
+ wire sys_clk;
+ wire sys_rst;
+
+ wire eim_bclk_buf;
+
+ novena_clkmgr clkmgr
+ (
+ .gclk_p (gclk_p_pin),
+ .gclk_n (gclk_n_pin),
+ + .reset_mcu_b (reset_mcu_b_pin),
+ + .sys_clk (sys_clk),
+ .sys_rst (sys_rst),
+
+ .bclk_in (eim_bclk),
+ .bclk_out (eim_bclk_buf)
+ );
+
+
+ //
+ // EIM Arbiter
+ //
+
+ /* EIM arbiter handles EIM access and transfers it into `sys_clk' clock domain. */
+
+ wire [13: 0] sys_eim_addr; + wire sys_eim_wr;
+ wire sys_eim_rd; + wire [31: 0] sys_eim_dout; + wire [31: 0] sys_eim_din;
+
+ eim_arbiter eim
+ (
+ .eim_bclk (eim_bclk_buf),
+ .eim_cs0_n (eim_cs0_n),
+ .eim_da (eim_da), + .eim_lba_n (eim_lba_n),
+ .eim_wr_n (eim_wr_n), + .eim_oe_n (eim_oe_n),
+ .eim_wait_n (eim_wait_n),
+
+ .sys_clk (sys_clk),
+
+ .sys_addr (sys_eim_addr),
+ .sys_wren (sys_eim_wr),
+ .sys_data_out (sys_eim_dout),
+ .sys_rden (sys_eim_rd),
+ .sys_data_in (sys_eim_din)
+ );
+
+
+ //
+ // Core Selector (MUX)
+ //
+
+ /* This multiplexor is used to map demo adder registers somewhere into EIM address space. */
+
+ core_selector mux
+ (
+ .sys_clk (sys_clk),
+ .sys_rst (sys_rst),
+
+ .sys_eim_addr (sys_eim_addr),
+ .sys_eim_wr (sys_eim_wr),
+ .sys_eim_rd (sys_eim_rd),
+ + .sys_eim_dout (sys_eim_dout),
+ .sys_eim_din (sys_eim_din)
+ );
+
+
+ //
+ // LED Driver
+ //
+ eim_indicator led
+ (
+ .sys_clk (sys_clk),
+ .sys_rst (sys_rst),
+ .eim_active (sys_eim_wr | sys_eim_rd),
+ .led_out (led_pin)
+ );
+
+
+ //
+ // Unused
+ //
+ assign apoptosis_pin = 1'b0;
+
+
+endmodule
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