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diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat
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+REM file: simulate_mti.bat
+REM  
+REM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM  
+REM  This file contains confidential and proprietary information
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+REM  
+# set up the working directory
+set work work
+vlib work
+
+REM compile all of the files
+vlog -work work %XILINX%\verilog\src\glbl.v
+vlog -work work ..\..\implement\results\routed.v
+vlog -work work clkmgr_dcm_tb.v
+
+REM run the simulation
+vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clkmgr_dcm_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.clkmgr_dcm_tb work.glbl