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2018-10-16Added width definition.Joachim Strömbergson
2018-08-28Connected the pipeline regs for t1 and t2 in the stat update logic. Verified ↵Joachim Strömbergson
functionality. Updated README after test implementation. The design now meets 100 MHz clock in Artix7 with speed grade -1.
2018-08-28Added pipeline register and stall cycle in the FSM to accomodate the ↵Joachim Strömbergson
pipeline. Registers not yet used in the design. Cleaned up constants to silence lint.
2018-04-27Removed FSM and cleaned up code in W mem. Cleaned up testbenches to silence ↵Joachim Strömbergson
warnings.
2018-04-27Updated Makefile with flags for cc. Added support for linting.Joachim Strömbergson
2016-05-31Updated README with status info, note about the new SHA224 functionality and ↵Joachim Strömbergson
the changes to the API.
2016-05-31Adding functionality to support both SHA224 and SHA256 digest modes. Note: ↵Joachim Strömbergson
This update changes the ADDR_CTRL API register since it adds a mode bit. The version major number has been bumped to reflect this API change. The top level testbench contains tests for SHA224 as well as old tests for SHA256. The core level tb still only tests SHA256.
2016-05-31Fixed long constants and instead rely on zero extend in Verilog.Joachim Strömbergson
2015-12-13whack copyrightsPaul Selkirk
2015-07-17Fixed state restore testcase in core testbench. Fixed the double block test ↵Joachim Strömbergson
case to really test the core. Added data valid task.
2015-07-17Minor cleanup.Joachim Strömbergson
2015-07-17Removed the address defines not needed.Joachim Strömbergson
2015-07-17Since state is digest having separate addresses for writing state is ↵Joachim Strömbergson
superflous. Captain slow.
2015-07-17Added top level test case for restore state and continue hashing. Test OK.Joachim Strömbergson
2015-07-16Adding a task to dump the H state.Joachim Strömbergson
2015-07-16Adding test case for state restore.Joachim Strömbergson
2015-07-16Added logic to write state into the state registers. Simplified the state ↵Joachim Strömbergson
write interface to a common data port.
2015-07-16The digest is the complete state so we only need to be able to write back ↵Joachim Strömbergson
state. The state addresses are still readable though.
2015-07-16(1) Adding addresses to be able to read and write the internal hash state ↵Joachim Strömbergson
from the API. (2) Bumped version to reflect the changes to the API. (3) Added ports for state access in the core module and connected them in the top level wrapper.
2015-03-31Remove wishbone testbench code, because we no longer have the verilog.Paul Selkirk
2015-03-31Revert streamlined wrapper, and don't delay register reads.Paul Selkirk
2015-03-17Rearrange cores.Paul Selkirk
2015-03-11Removed the wishbone wrapper we don't use.Joachim Strömbergson
2014-11-07Changed to asynch reset.Joachim Strömbergson
2014-11-06Fixed nits found using verilator linter. Removed trailing whitespace.Joachim Strömbergson
2014-05-16Adding helper functions for printing digest. Adding testcase for message ↵Joachim Strömbergson
with 1000 blocks.
2014-04-01Updating sha256 python model with NIST dual block test case and test case ↵Joachim Strömbergson
with huge message. Disabling verbose mode.
2014-03-17Removed redundant flag reset wires.Joachim Strömbergson
2014-03-16Adding self resetting init and next flags. Updating TBs to not reset the ↵Joachim Strömbergson
flags. Fixing clock parameter naming.
2014-03-15(1) Updated interface to new std. (2) Added missing input designation in ↵Joachim Strömbergson
tasks. Now simumaltion with ModelSim works.
2014-02-26Removed the positions of W no longer needed.Joachim Strömbergson
2014-02-26Changed the python model to use a sliding window for W.Joachim Strömbergson
2014-02-25Adding more info about the core.Joachim Strömbergson
2014-02-25Updating README with info on the design.Joachim Strömbergson
2014-02-23Fixed compile problems due to copy crime.Joachim Strömbergson
2014-02-23Update or README with more info on status.Joachim Strömbergson
2014-02-23Moved wmem update logic to a separate process.Joachim Strömbergson
2014-02-22Updated status with info on the sliding window W-mem and the new ↵Joachim Strömbergson
implementation results.
2014-02-22Updated testbenches to the new sliding window W-mem.Joachim Strömbergson
2014-02-22Changed W-memory into sliding window. This also affected interface and ↵Joachim Strömbergson
integration in the core.
2014-02-19Adding a simple README file in markdown format that describes the core.Joachim Strömbergson
2014-02-19Adding a Python model for the SHA256 core.Joachim Strömbergson
2014-02-19Adding a testbench for the Wishbone wrapper.Joachim Strömbergson
2014-02-19Adding a testbench for the SHA256 top level wrapper.Joachim Strömbergson
2014-02-19Adding a testbench for the SHA256 core.Joachim Strömbergson
2014-02-19Adding a testbench for the w memory module.Joachim Strömbergson
2014-02-19Adding a Wishbone wrapper for the SHA256 core.Joachim Strömbergson
2014-02-19Adding top level wrapper for the sha256. This wrapper provides a simple ↵Joachim Strömbergson
memory like interface.
2014-02-19Source for the main part of the sha256 core.Joachim Strömbergson
2014-02-19Adding the W memory including scheduler and expansion functionality.Joachim Strömbergson