Added pipeline register and stall cycle in the FSM to accomodate the pipeline. Registers not yet used in the design. Cleaned up constants to silence lint.

1 files changed, 106 insertions, 93 deletions

diff --git a/src/rtl/sha256_core.v b/src/rtl/sha256_core.v
index 6553aab..95ad28b 100644
--- a/src/rtl/sha256_core.v
+++ b/src/rtl/sha256_core.v
@@ -89,9 +89,10 @@ module sha256_core(
 
   localparam SHA256_ROUNDS = 63;
 
-  localparam CTRL_IDLE   = 0;
-  localparam CTRL_ROUNDS = 1;
-  localparam CTRL_DONE   = 2;
+  localparam CTRL_IDLE    = 0;
+  localparam CTRL_ROUNDS0 = 1;
+  localparam CTRL_ROUNDS1 = 2;
+  localparam CTRL_DONE    = 3;
 
 
   //----------------------------------------------------------------
@@ -133,6 +134,9 @@ module sha256_core(
   reg [31 : 0] H7_new;
   reg          H_we;
 
+  reg [31 : 0] t1_reg;
+  reg [31 : 0] t2_reg;
+
   reg [5 : 0] t_ctr_reg;
   reg [5 : 0] t_ctr_new;
   reg         t_ctr_we;
@@ -213,28 +217,32 @@ module sha256_core(
     begin : reg_update
       if (!reset_n)
         begin
-          a_reg            <= 32'h00000000;
-          b_reg            <= 32'h00000000;
-          c_reg            <= 32'h00000000;
-          d_reg            <= 32'h00000000;
-          e_reg            <= 32'h00000000;
-          f_reg            <= 32'h00000000;
-          g_reg            <= 32'h00000000;
-          h_reg            <= 32'h00000000;
-          H0_reg           <= 32'h00000000;
-          H1_reg           <= 32'h00000000;
-          H2_reg           <= 32'h00000000;
-          H3_reg           <= 32'h00000000;
-          H4_reg           <= 32'h00000000;
-          H5_reg           <= 32'h00000000;
-          H6_reg           <= 32'h00000000;
-          H7_reg           <= 32'h00000000;
-          digest_valid_reg <= 0;
-          t_ctr_reg        <= 6'b000000;
+          a_reg            <= 32'h0;
+          b_reg            <= 32'h0;
+          c_reg            <= 32'h0;
+          d_reg            <= 32'h0;
+          e_reg            <= 32'h0;
+          f_reg            <= 32'h0;
+          g_reg            <= 32'h0;
+          h_reg            <= 32'h0;
+          H0_reg           <= 32'h0;
+          H1_reg           <= 32'h0;
+          H2_reg           <= 32'h0;
+          H3_reg           <= 32'h0;
+          H4_reg           <= 32'h0;
+          H5_reg           <= 32'h0;
+          H6_reg           <= 32'h0;
+          H7_reg           <= 32'h0;
+          t1_reg           <= 32'h0;
+          t2_reg           <= 32'h0;
+          digest_valid_reg <= 1'h0;
+          t_ctr_reg        <= 6'h0;
           sha256_ctrl_reg  <= CTRL_IDLE;
         end
       else
         begin
+          t1_reg <= t1;
+          t2_reg <= t2;
 
           if (a_h_we)
             begin
@@ -309,19 +317,19 @@ module sha256_core(
   //----------------------------------------------------------------
   always @*
     begin : digest_logic
-      H0_new = 32'h00000000;
-      H1_new = 32'h00000000;
-      H2_new = 32'h00000000;
-      H3_new = 32'h00000000;
-      H4_new = 32'h00000000;
-      H5_new = 32'h00000000;
-      H6_new = 32'h00000000;
-      H7_new = 32'h00000000;
-      H_we = 0;
+      H0_new = 32'h0;
+      H1_new = 32'h0;
+      H2_new = 32'h0;
+      H3_new = 32'h0;
+      H4_new = 32'h0;
+      H5_new = 32'h0;
+      H6_new = 32'h0;
+      H7_new = 32'h0;
+      H_we = 1'h0;
 
       if (digest_init)
         begin
-          H_we = 1;
+          H_we = 1'h1;
           if (mode)
             begin
               H0_new = SHA256_H0_0;
@@ -356,7 +364,7 @@ module sha256_core(
           H5_new = H5_reg + f_reg;
           H6_new = H6_reg + g_reg;
           H7_new = H7_reg + h_reg;
-          H_we = 1;
+          H_we = 1'h1;
         end
     end // digest_logic
 
@@ -409,19 +417,19 @@ module sha256_core(
   //----------------------------------------------------------------
   always @*
     begin : state_logic
-      a_new  = 32'h00000000;
-      b_new  = 32'h00000000;
-      c_new  = 32'h00000000;
-      d_new  = 32'h00000000;
-      e_new  = 32'h00000000;
-      f_new  = 32'h00000000;
-      g_new  = 32'h00000000;
-      h_new  = 32'h00000000;
-      a_h_we = 0;
+      a_new  = 32'h0;
+      b_new  = 32'h0;
+      c_new  = 32'h0;
+      d_new  = 32'h0;
+      e_new  = 32'h0;
+      f_new  = 32'h0;
+      g_new  = 32'h0;
+      h_new  = 32'h0;
+      a_h_we = 1'h0;
 
       if (state_init)
         begin
-          a_h_we = 1;
+          a_h_we = 1'h1;
           if (first_block)
             begin
               if (mode)
@@ -470,7 +478,7 @@ module sha256_core(
           f_new  = e_reg;
           g_new  = f_reg;
           h_new  = g_reg;
-          a_h_we = 1;
+          a_h_we = 1'h1;
         end
     end // state_logic
 
@@ -483,19 +491,19 @@ module sha256_core(
   //----------------------------------------------------------------
   always @*
     begin : t_ctr
-      t_ctr_new = 0;
-      t_ctr_we  = 0;
+      t_ctr_new = 6'h0;
+      t_ctr_we  = 1'h0;
 
       if (t_ctr_rst)
         begin
-          t_ctr_new = 0;
-          t_ctr_we  = 1;
+          t_ctr_new = 6'h0;
+          t_ctr_we  = 1'h1;
         end
 
       if (t_ctr_inc)
         begin
           t_ctr_new = t_ctr_reg + 1'b1;
-          t_ctr_we  = 1;
+          t_ctr_we  = 1'h1;
         end
     end // t_ctr
 
@@ -507,81 +515,86 @@ module sha256_core(
   //----------------------------------------------------------------
   always @*
     begin : sha256_ctrl_fsm
-      digest_init      = 0;
-      digest_update    = 0;
-
-      state_init       = 0;
-      state_update     = 0;
-
-      first_block      = 0;
-      ready_flag       = 0;
-
-      w_init           = 0;
-      w_next           = 0;
-
-      t_ctr_inc        = 0;
-      t_ctr_rst        = 0;
-
-      digest_valid_new = 0;
-      digest_valid_we  = 0;
-
+      digest_init      = 1'h0;
+      digest_update    = 1'h0;
+      state_init       = 1'h0;
+      state_update     = 1'h0;
+      first_block      = 1'h0;
+      ready_flag       = 1'h0;
+      w_init           = 1'h0;
+      w_next           = 1'h0;
+      t_ctr_inc        = 1'h0;
+      t_ctr_rst        = 1'h0;
+      digest_valid_new = 1'h0;
+      digest_valid_we  = 1'h0;
       sha256_ctrl_new  = CTRL_IDLE;
-      sha256_ctrl_we   = 0;
+      sha256_ctrl_we   = 1'h0;
 
 
       case (sha256_ctrl_reg)
         CTRL_IDLE:
           begin
-            ready_flag = 1;
+            ready_flag = 1'h1;
 
             if (init)
               begin
-                digest_init      = 1;
-                w_init           = 1;
-                state_init       = 1;
-                first_block      = 1;
-                t_ctr_rst        = 1;
-                digest_valid_new = 0;
-                digest_valid_we  = 1;
-                sha256_ctrl_new  = CTRL_ROUNDS;
-                sha256_ctrl_we   = 1;
+                digest_init      = 1'h1;
+                w_init           = 1'h1;
+                state_init       = 1'h1;
+                first_block      = 1'h1;
+                t_ctr_rst        = 1'h1;
+                digest_valid_new = 1'h0;
+                digest_valid_we  = 1'h1;
+                sha256_ctrl_new  = CTRL_ROUNDS0;
+                sha256_ctrl_we   = 1'h1;
               end
 
             if (next)
               begin
-                w_init           = 1;
-                state_init       = 1;
-                t_ctr_rst        = 1;
-                digest_valid_new = 0;
-                digest_valid_we  = 1;
-                sha256_ctrl_new  = CTRL_ROUNDS;
-                sha256_ctrl_we   = 1;
+                w_init           = 1'h1;
+                state_init       = 1'h1;
+                t_ctr_rst        = 1'h1;
+                digest_valid_new = 1'h0;
+                digest_valid_we  = 1'h1;
+                sha256_ctrl_new  = CTRL_ROUNDS0;
+                sha256_ctrl_we   = 1'h1;
               end
           end
 
+        CTRL_ROUNDS0:
+          begin
+            sha256_ctrl_new = CTRL_ROUNDS1;
+            sha256_ctrl_we  = 1'h1;
+          end
+
 
-        CTRL_ROUNDS:
+        CTRL_ROUNDS1:
           begin
-            w_next       = 1;
-            state_update = 1;
-            t_ctr_inc    = 1;
+            w_next       = 1'h1;
+            state_update = 1'h1;
+            t_ctr_inc    = 1'h1;
 
             if (t_ctr_reg == SHA256_ROUNDS)
               begin
                 sha256_ctrl_new = CTRL_DONE;
-                sha256_ctrl_we  = 1;
+                sha256_ctrl_we  = 1'h1;
+              end
+            else
+              begin
+                sha256_ctrl_new = CTRL_ROUNDS0;
+                sha256_ctrl_we  = 1'h1;
               end
           end
 
 
         CTRL_DONE:
           begin
-            digest_update    = 1;
-            digest_valid_new = 1;
-            digest_valid_we  = 1;
+            digest_update    = 1'h1;
+            digest_valid_new = 1'h1;
+            digest_valid_we  = 1'h1;
 
             sha256_ctrl_new  = CTRL_IDLE;
-            sha256_ctrl_we   = 1;
+            sha256_ctrl_we   = 1'h1;
           end
       endcase // case (sha256_ctrl_reg)
     end // sha256_ctrl_fsm