Updated README with status info, note about the new SHA224 functionality and the changes to the API.

1 files changed, 18 insertions, 3 deletions

diff --git a/README.md b/README.md
index 10150df..79f17f5 100644
--- a/README.md
+++ b/README.md
@@ -80,6 +80,24 @@ Implementation results using Altera Quartus-II 13.1.
 
 
 ## Status ##
+***(2016-05-31)***
+
+The core now supports both sha224 and sha256 modes. The default mode is
+sha256.
+
+NOTE: The mode bit is located in the ADDR_CTRL API register and this
+means that when writing to this register to start processing a block,
+care must be taken to set the mode bit to the intended mode. This means
+that old code that for example simply wrote 0x01 to initiate SHA256
+processing will now initiate SHA224 processing. Writing 0x05 will
+now initiate SHA256 processing.
+
+The API version has been bumped a major number to reflect this change.
+
+Regarding SHA224, it is up to the user to only read seven, not eight
+words from the digest registers. The core will update the LSW too.
+
+
 ***(2013-02-23)***
 
 Cleanup, more results etc. Move all wmem update logic to a separate
@@ -108,6 +126,3 @@ The new implementation resources and performance:
 **(2014-02-19)**
 - The core has been added to the Cryptech repo. The core comes from
   https://github.com/secworks/sha256
-
-
-