Adding a simple README file in markdown format that describes the core.

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+# sha256 #
+Hardware implementation of the SHA-256 cryptographic hash function. The
+implementation is written in Verilog 2001 compliant code. The
+implementation includes a core and a wrapper that provides a 32-bit
+interface for simple integration. There is also an alternative wrapper
+that implements a Wishbone compliant interface.
+
+This is a low area implementation that iterates over the rounds but
+there is no sharing of operations such as adders.
+
+The hardware implementation is complemented by a functional model
+written in Python.
+
+
+## Implementation ##
+Implementation results using the Altera Quartus-II v13.1 design tool.
+
+### Cyclone IV GX ###
+- 9587 LEs
+- 3349 registers
+- 73 MHz
+- 66 cycles latency
+
+
+## Todo ##
+- Extensive verification in physical device.
+- Complete documentation.
+
+
+## Status ##
+**(2014-02-19)**
+- The core has been added to the Cryptech repo. The core comes from
+  https://github.com/secworks/sha256
+
+
+