Added top level test case for restore state and continue hashing. Test OK.

1 files changed, 148 insertions, 72 deletions

diff --git a/src/tb/tb_sha256.v b/src/tb/tb_sha256.v
index 72e7d21..b6916cd 100644
--- a/src/tb/tb_sha256.v
+++ b/src/tb/tb_sha256.v
@@ -8,30 +8,30 @@
 // Author: Joachim Strombergson
 // Copyright (c) 2014, SUNET
 // All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or 
-// without modification, are permitted provided that the following 
-// conditions are met: 
-// 
-// 1. Redistributions of source code must retain the above copyright 
-//    notice, this list of conditions and the following disclaimer. 
-// 
-// 2. Redistributions in binary form must reproduce the above copyright 
-//    notice, this list of conditions and the following disclaimer in 
-//    the documentation and/or other materials provided with the 
-//    distribution. 
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
-// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in
+//    the documentation and/or other materials provided with the
+//    distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 // ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 //
 //======================================================================
@@ -46,7 +46,7 @@
 // Test module.
 //------------------------------------------------------------------
 module tb_sha256();
-  
+
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
@@ -67,7 +67,7 @@ module tb_sha256();
   parameter ADDR_STATUS      = 8'h09;
   parameter STATUS_READY_BIT = 0;
   parameter STATUS_VALID_BIT = 1;
-                             
+
   parameter ADDR_BLOCK0    = 8'h10;
   parameter ADDR_BLOCK1    = 8'h11;
   parameter ADDR_BLOCK2    = 8'h12;
@@ -84,7 +84,7 @@ module tb_sha256();
   parameter ADDR_BLOCK13   = 8'h1d;
   parameter ADDR_BLOCK14   = 8'h1e;
   parameter ADDR_BLOCK15   = 8'h1f;
-                             
+
   parameter ADDR_DIGEST0   = 8'h20;
   parameter ADDR_DIGEST1   = 8'h21;
   parameter ADDR_DIGEST2   = 8'h22;
@@ -94,7 +94,16 @@ module tb_sha256();
   parameter ADDR_DIGEST6   = 8'h26;
   parameter ADDR_DIGEST7   = 8'h27;
 
-  
+  parameter ADDR_STATE0    = 8'h30;
+  parameter ADDR_STATE1    = 8'h31;
+  parameter ADDR_STATE2    = 8'h32;
+  parameter ADDR_STATE3    = 8'h33;
+  parameter ADDR_STATE4    = 8'h34;
+  parameter ADDR_STATE5    = 8'h35;
+  parameter ADDR_STATE6    = 8'h36;
+  parameter ADDR_STATE7    = 8'h37;
+
+
   //----------------------------------------------------------------
   // Register and Wire declarations.
   //----------------------------------------------------------------
@@ -113,36 +122,36 @@ module tb_sha256();
 
   reg [31 : 0]  read_data;
   reg [255 : 0] digest_data;
-  
-  
+
+
   //----------------------------------------------------------------
   // Device Under Test.
   //----------------------------------------------------------------
   sha256 dut(
              .clk(tb_clk),
              .reset_n(tb_reset_n),
-             
+
              .cs(tb_cs),
              .we(tb_we),
-             
-             
+
+
              .address(tb_address),
              .write_data(tb_write_data),
              .read_data(tb_read_data),
              .error(tb_error)
             );
-  
+
 
   //----------------------------------------------------------------
   // clk_gen
   //
-  // Clock generator process. 
+  // Clock generator process.
   //----------------------------------------------------------------
-  always 
+  always
     begin : clk_gen
       #CLK_HALF_PERIOD tb_clk = !tb_clk;
     end // clk_gen
-    
+
 
   //----------------------------------------------------------------
   // sys_monitor
@@ -156,7 +165,7 @@ module tb_sha256();
       cycle_ctr = cycle_ctr + 1;
     end
 
-  
+
   //----------------------------------------------------------------
   // dump_dut_state()
   //
@@ -167,20 +176,20 @@ module tb_sha256();
       $display("State of DUT");
       $display("------------");
       $display("Inputs and outputs:");
-      $display("cs = 0x%01x, we = 0x%01x", 
+      $display("cs = 0x%01x, we = 0x%01x",
                dut.cs, dut.we);
       $display("address = 0x%02x", dut.address);
-      $display("write_data = 0x%08x, read_data = 0x%08x", 
+      $display("write_data = 0x%08x, read_data = 0x%08x",
                dut.write_data, dut.read_data);
       $display("tmp_read_data = 0x%08x", dut.tmp_read_data);
       $display("");
 
       $display("Control and status:");
-      $display("ctrl = 0x%02x, status = 0x%02x", 
-               {dut.next_reg, dut.init_reg}, 
+      $display("ctrl = 0x%02x, status = 0x%02x",
+               {dut.next_reg, dut.init_reg},
                {dut.digest_valid_reg, dut.ready_reg});
       $display("");
-      
+
       $display("Message block:");
       $display("block0  = 0x%08x, block1  = 0x%08x, block2  = 0x%08x,  block3  = 0x%08x",
                dut.block0_reg, dut.block1_reg, dut.block2_reg, dut.block3_reg);
@@ -192,15 +201,31 @@ module tb_sha256();
      $display("block12 = 0x%08x, block13 = 0x%08x, block14 = 0x%08x,  block15 = 0x%08x",
                dut.block12_reg, dut.block13_reg, dut.block14_reg, dut.block15_reg);
       $display("");
-      
+
       $display("Digest:");
       $display("digest = 0x%064x", dut.digest_reg);
       $display("");
-      
+
     end
   endtask // dump_dut_state
-  
-  
+
+
+  //----------------------------------------------------------------
+  // dump_H_state()
+  //
+  // Dump the state of the H registers when needed.
+  //----------------------------------------------------------------
+  task dump_H_state();
+    begin
+      $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x",
+               dut.core.H0_reg, dut.core.H1_reg, dut.core.H2_reg, dut.core.H3_reg);
+      $display("H4_reg = 0x%08x, H5_reg = 0x%08x, H6_reg = 0x%08x, H7_reg = 0x%08x",
+               dut.core.H4_reg, dut.core.H5_reg, dut.core.H6_reg, dut.core.H7_reg);
+      $display("");
+    end
+  endtask // dump_H_state
+
+
   //----------------------------------------------------------------
   // reset_dut()
   //
@@ -215,7 +240,7 @@ module tb_sha256();
     end
   endtask // reset_dut
 
-  
+
   //----------------------------------------------------------------
   // init_sim()
   //
@@ -227,7 +252,7 @@ module tb_sha256();
       cycle_ctr = 32'h00000000;
       error_ctr = 32'h00000000;
       tc_ctr = 32'h00000000;
-      
+
       tb_clk = 0;
       tb_reset_n = 0;
       tb_cs = 0;
@@ -237,7 +262,7 @@ module tb_sha256();
     end
   endtask // init_dut
 
-  
+
   //----------------------------------------------------------------
   // display_test_result()
   //
@@ -256,8 +281,8 @@ module tb_sha256();
         end
     end
   endtask // display_test_result
-  
-  
+
+
   //----------------------------------------------------------------
   // wait_ready()
   //
@@ -271,14 +296,14 @@ module tb_sha256();
   task wait_ready();
     begin
       read_data = 0;
-      
+
       while (read_data == 0)
         begin
           read_word(ADDR_STATUS);
         end
     end
   endtask // wait_ready
-  
+
 
   //----------------------------------------------------------------
   // write_word()
@@ -293,7 +318,7 @@ module tb_sha256();
           $display("*** Writing 0x%08x to 0x%02x.", word, address);
           $display("");
         end
-         
+
       tb_address = address;
       tb_write_data = word;
       tb_cs = 1;
@@ -330,7 +355,7 @@ module tb_sha256();
       write_word(ADDR_BLOCK15, block[31  :   0]);
     end
   endtask // write_block
-  
+
 
   //----------------------------------------------------------------
   // read_word()
@@ -356,7 +381,7 @@ module tb_sha256();
     end
   endtask // read_word
 
-  
+
   //----------------------------------------------------------------
   // check_name_version()
   //
@@ -382,7 +407,7 @@ module tb_sha256();
                version[31 : 24], version[23 : 16], version[15 : 8], version[7 : 0]);
     end
   endtask // check_name_version
-  
+
 
   //----------------------------------------------------------------
   // read_digest()
@@ -410,8 +435,8 @@ module tb_sha256();
       digest_data[31  :   0] = read_data;
     end
   endtask // read_digest
-    
-  
+
+
   //----------------------------------------------------------------
   // single_block_test()
   //
@@ -421,8 +446,8 @@ module tb_sha256();
   task single_block_test(input [511 : 0] block,
                          input [255 : 0] expected);
     begin
-      $display("*** TC%01d - Single block test started.", tc_ctr); 
-     
+      $display("*** TC%01d - Single block test started.", tc_ctr);
+
       write_block(block);
       write_word(ADDR_CTRL, CTRL_INIT_VALUE);
       #(CLK_PERIOD);
@@ -440,12 +465,12 @@ module tb_sha256();
           $display("TC%01d: Got:      0x%064x", tc_ctr, digest_data);
           error_ctr = error_ctr + 1;
         end
-      $display("*** TC%01d - Single block test done.", tc_ctr); 
+      $display("*** TC%01d - Single block test done.", tc_ctr);
       tc_ctr = tc_ctr + 1;
     end
   endtask // single_block_test
-    
-  
+
+
   //----------------------------------------------------------------
   // double_block_test()
   //
@@ -459,7 +484,7 @@ module tb_sha256();
                          input [255 : 0] expected1
                         );
     begin
-      $display("*** TC%01d - Double block test started.", tc_ctr); 
+      $display("*** TC%01d - Double block test started.", tc_ctr);
 
       // First block
       write_block(block0);
@@ -486,7 +511,7 @@ module tb_sha256();
       #(CLK_PERIOD);
       wait_ready();
       read_digest();
-      
+
       if (digest_data == expected1)
         begin
           $display("TC%01d final block: OK.", tc_ctr);
@@ -499,15 +524,64 @@ module tb_sha256();
           error_ctr = error_ctr + 1;
         end
 
-      $display("*** TC%01d - Double block test done.", tc_ctr); 
+      $display("*** TC%01d - Double block test done.", tc_ctr);
       tc_ctr = tc_ctr + 1;
     end
   endtask // double_block_test
 
-    
+
+  //----------------------------------------------------------------
+  // restore_state_test()
+  //
+  //
+  // Perform test of a double block digest. Note that we check
+  // the digests for both the first and final block.
+  //----------------------------------------------------------------
+  task restore_state_test(input [255 : 0] state,
+                          input [511 : 0] block,
+                          input [255 : 0] expected
+                         );
+    begin
+      $display("*** TC%01d - Restore state test started.", tc_ctr);
+
+      // Write state.
+      write_word(ADDR_STATE0, state[255 : 224]);
+      write_word(ADDR_STATE1, state[223 : 192]);
+      write_word(ADDR_STATE2, state[191 : 160]);
+      write_word(ADDR_STATE3, state[159 : 128]);
+      write_word(ADDR_STATE4, state[127 : 096]);
+      write_word(ADDR_STATE5, state[095 : 0064]);
+      write_word(ADDR_STATE6, state[063 : 0032]);
+      write_word(ADDR_STATE7, state[031 : 000]);
+
+      // Process block.
+      write_block(block);
+      write_word(ADDR_CTRL, CTRL_NEXT_VALUE);
+      #(CLK_PERIOD);
+      wait_ready();
+      read_digest();
+
+      if (digest_data == expected)
+        begin
+          $display("TC%01d final digest: OK.", tc_ctr);
+        end
+      else
+        begin
+          $display("TC%01d: ERROR in final digest", tc_ctr);
+          $display("TC%01d: Expected: 0x%064x", tc_ctr, expected);
+          $display("TC%01d: Got:      0x%064x", tc_ctr, digest_data);
+          error_ctr = error_ctr + 1;
+        end
+
+      $display("*** TC%01d - Restore state test done.", tc_ctr);
+      tc_ctr = tc_ctr + 1;
+    end
+  endtask // restore_state_test
+
+
   //----------------------------------------------------------------
   // sha256_test
-  // The main test functionality. 
+  // The main test functionality.
   //
   // Test cases taken from:
   // http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA256.pdf
@@ -521,7 +595,7 @@ module tb_sha256();
       reg [255 : 0] res1_0;
       reg [511 : 0] tc1_1;
       reg [255 : 0] res1_1;
-      
+
       $display("   -- Testbench for sha256 started --");
 
       init_sim();
@@ -543,9 +617,11 @@ module tb_sha256();
       tc1_1 = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001C0;
       res1_1 = 256'h248D6A61D20638B8E5C026930C3E6039A33CE45964FF2167F6ECEDD419DB06C1;
       double_block_test(tc1_0, res1_0, tc1_1, res1_1);
-      
+
+      restore_state_test(res1_0, tc1_1, res1_1);
+
       display_test_result();
-      
+
       $display("   -- Testbench for sha256 done. --");
       $finish;
     end // sha256_test