core/hash/sha256 - Verilog implementation of the SHA-256 cryptographic hash function

Age	Commit message (Expand)	Author
2019-01-08	Ported the timing fix from SHA-512 to SHA-256. The core can now run at 170 MH...HEAD master	Joachim Strömbergson
2018-10-18	Compacted the code for K constants.	Joachim Strömbergson
2018-10-18	(1) Locked down API to ignore read or write requests that could leak info or ...	Joachim Strömbergson
2018-10-16	Added width definition.	Joachim Strömbergson
2018-08-28	Connected the pipeline regs for t1 and t2 in the stat update logic. Verified ...	Joachim Strömbergson
2018-08-28	Added pipeline register and stall cycle in the FSM to accomodate the pipeline...	Joachim Strömbergson
2018-04-27	Removed FSM and cleaned up code in W mem. Cleaned up testbenches to silence w...	Joachim Strömbergson
2018-04-27	Updated Makefile with flags for cc. Added support for linting.	Joachim Strömbergson
2016-05-31	Updated README with status info, note about the new SHA224 functionality and ...	Joachim Strömbergson
2016-05-31	Adding functionality to support both SHA224 and SHA256 digest modes. Note: Th...	Joachim Strömbergson
2016-05-31	Fixed long constants and instead rely on zero extend in Verilog.	Joachim Strömbergson
2015-12-13	whack copyrights	Paul Selkirk
2015-07-17	Fixed state restore testcase in core testbench. Fixed the double block test c...	Joachim Strömbergson
2015-07-17	Minor cleanup.	Joachim Strömbergson
2015-07-17	Removed the address defines not needed.	Joachim Strömbergson
2015-07-17	Since state is digest having separate addresses for writing state is superflo...	Joachim Strömbergson
2015-07-17	Added top level test case for restore state and continue hashing. Test OK.	Joachim Strömbergson
2015-07-16	Adding a task to dump the H state.	Joachim Strömbergson
2015-07-16	Adding test case for state restore.	Joachim Strömbergson
2015-07-16	Added logic to write state into the state registers. Simplified the state wri...	Joachim Strömbergson
2015-07-16	The digest is the complete state so we only need to be able to write back sta...	Joachim Strömbergson
2015-07-16	(1) Adding addresses to be able to read and write the internal hash state fro...	Joachim Strömbergson
2015-03-31	Remove wishbone testbench code, because we no longer have the verilog.	Paul Selkirk
2015-03-31	Revert streamlined wrapper, and don't delay register reads.	Paul Selkirk
2015-03-17	Rearrange cores.	Paul Selkirk
2015-03-11	Removed the wishbone wrapper we don't use.	Joachim Strömbergson
2014-11-07	Changed to asynch reset.	Joachim Strömbergson
2014-11-06	Fixed nits found using verilator linter. Removed trailing whitespace.	Joachim Strömbergson
2014-05-16	Adding helper functions for printing digest. Adding testcase for message with...	Joachim Strömbergson
2014-04-01	Updating sha256 python model with NIST dual block test case and test case wit...	Joachim Strömbergson
2014-03-17	Removed redundant flag reset wires.	Joachim Strömbergson
2014-03-16	Adding self resetting init and next flags. Updating TBs to not reset the flag...	Joachim Strömbergson
2014-03-15	(1) Updated interface to new std. (2) Added missing input designation in task...	Joachim Strömbergson
2014-02-26	Removed the positions of W no longer needed.	Joachim Strömbergson
2014-02-26	Changed the python model to use a sliding window for W.	Joachim Strömbergson
2014-02-25	Adding more info about the core.	Joachim Strömbergson
2014-02-25	Updating README with info on the design.	Joachim Strömbergson
2014-02-23	Fixed compile problems due to copy crime.	Joachim Strömbergson
2014-02-23	Update or README with more info on status.	Joachim Strömbergson
2014-02-23	Moved wmem update logic to a separate process.	Joachim Strömbergson
2014-02-22	Updated status with info on the sliding window W-mem and the new implementati...	Joachim Strömbergson
2014-02-22	Updated testbenches to the new sliding window W-mem.	Joachim Strömbergson
2014-02-22	Changed W-memory into sliding window. This also affected interface and integr...	Joachim Strömbergson
2014-02-19	Adding a simple README file in markdown format that describes the core.	Joachim Strömbergson
2014-02-19	Adding a Python model for the SHA256 core.	Joachim Strömbergson
2014-02-19	Adding a testbench for the Wishbone wrapper.	Joachim Strömbergson
2014-02-19	Adding a testbench for the SHA256 top level wrapper.	Joachim Strömbergson
2014-02-19	Adding a testbench for the SHA256 core.	Joachim Strömbergson
2014-02-19	Adding a testbench for the w memory module.	Joachim Strömbergson
2014-02-19	Adding a Wishbone wrapper for the SHA256 core.	Joachim Strömbergson