Synced AES repo. This commit fixes many nits such as: (1) Silence warnings on size of contants. (2) warning on tasks for empty arguments in tasks. (3) timescale directives not needed. It also implements API in a code-wise more compact way. Info about implementation status updated. No changes affect the functionality of the core.api_error_fix

12 files changed, 525 insertions, 734 deletions

diff --git a/README.md b/README.md
index f8a04fc..2fa2eb4 100644
--- a/README.md
+++ b/README.md
@@ -1,5 +1,5 @@
 aes
-======
+===
 
 Verilog implementation of the symmetric block cipher AES (Advanced
 Encryption Standard) as specified in the NIST document [FIPS 197](http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf).
@@ -26,28 +26,146 @@ achived by just having a single S-box. Similarly the performane can be
 increased by having 8 or even 16 S-boxes which would reduce the number
 of cycles to two cycles for each round.
 
+## Status ##
+The core is completed, has been used in FPGAs and in ASIC.
+
+
+## Implementation results - ASIC ##
+
+The core has been implemented in standard cell ASIC processes.
+
+### TSMC 180 nm ###
+Target frequency: 20 MHz
+Complete flow from RTL to placed gates. Automatic clock gating and scan
+insertion.
+
+- 8 kCells
+- Aera: 520 x 520 um
+- Good timing margin with no big cells and buffers.
+
+
+## Implementation results - FPGA ##
 
-## Implementation results ##
 The core has been implemented in Altera and Xilinx FPGA devices.
 
+### Altera Cyclone V GX ###
+- 2624 ALMs
+- 3123 Regs
+- 96 MHz
+- 46 cycles/block
+
+
 ### Altera Cyclone IV GX ###
-- 7497 LEs
+- 7426 LEs
 - 2994 Regs
 - 96 MHz fmax
-- 5 cycles/round
+- 46 cycles/block
 
-This means that we can do just about 2 Mblocks/s or 256 Mbps
+This means that we can do more than 2 Mblocks/s or 256 Mbps
 performance.
 
 Removing the decipher module yields:
 - 5497 LEs
 - 2855 Regs
 - 106 MHz fmax
-- 5 cycles/round
+- 46 cycles/block
 
 
 ### Xilinx Spartan6LX-3 ###
 - 2576 slices
 - 3000 regs
 - 100 MHz
-- 5 cycles/round
+- 46 cycles/block
+
+
+### Xilinx Artix 7 200T-3 ###
+- 2298 slices
+- 2989 regs
+- 97 MHz
+- 46 cycles/block
+
+
+## Development Log ##
+***(2017-05-10)***
+
+Updated with results from ASIC implementation in TSMC 180 nm process.
+
+Removed timescale directives from testbenches which are not needed and
+just makes simulation with other cores harder.
+
+
+***(2017-04-13)***
+
+Some code cleanup to make it more readable and remove warnings from some
+parsers. No functional changes.
+
+Added implementation results for Altera Cyclone V GX.
+
+
+***(2016-11-20)***
+
+__HEADSUP__
+The API addresses for config and status registers has been switched. The
+reason for this is all other cores provided have status on 0x09. And any
+possible config on 0x0a. This change aligns the core for easier
+integration, but breaks designs that uses the old version.
+
+The core VERSION string has been updated to reflect the API change.
+
+The core NAME has also been updated. Precviously the NAME contained
+"-128", indicating that the core only supports 128 bit key length. But
+the core does in fact support both 128 and 256 bit key lengths.
+
+
+***(2016-09-06)***
+
+Updated implementation results with results from Xilinx Artix-7. There
+has also been done several minor fixes to shorten the code size, clarify
+the implementation etc. But the functionality of the core has not been
+altered. The core has been used in several designs.
+
+
+***(2014-11-28)***
+
+Top level simulation now passes all NISTs tests.
+
+
+***(2014-11-26)***
+
+Encryption and decryption now passes all NIST test cases on block level
+as well as core level. The Python model can do encryption but not
+decryption. The Python model contains separate tests for key generation,
+mixcolumns and inverse mixcolumns.
+
+
+***(2014-08-07)***
+
+Round key generation for both AES-128 and AES-256 now works when tested
+separately. Datapaths and core are yet to be debugged.
+
+
+***(2014-07-27)***
+
+Reworked the partitioning of block registers, round counters etc -
+basically a rather big change. The block processing is now pretty much
+self contained machines. Removed support for 192 bit keys.
+
+
+***(2014-04-26)***
+
+Most of the RTL completed but not yet debugged. The key expansion is
+still lacking. The architecture has been reworked several times, but
+this one looks promising.
+
+
+***(2014-03-19)***
+
+Several commits done up to this date. Halfway there.
+Changed name of repo to simply 'aes' to reflect that we will support at
+least both 128 and 256 bit keys. Possibly also 192 albeit nobody uses it
+(afaik).
+
+
+***(2014-02-21***:
+
+Initial commit. Nothing really here yet.
diff --git a/src/rtl/aes.v b/src/rtl/aes.v
index d79fe06..57c649f 100644
--- a/src/rtl/aes.v
+++ b/src/rtl/aes.v
@@ -51,7 +51,6 @@ module aes(
            output wire [31 : 0] read_data
           );
 
-
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
@@ -66,24 +65,15 @@ module aes(
   localparam ADDR_STATUS      = 8'h09;
   localparam STATUS_READY_BIT = 0;
   localparam STATUS_VALID_BIT = 1;
-  localparam STATUS_ERROR_BIT = 2;
 
-  localparam ADDR_CONFIG       = 8'h0a;
-  localparam CONFIG_ENCDEC_BIT = 0;
-  localparam CONFIG_KEYLEN_BIT = 1;
+  localparam ADDR_CONFIG      = 8'h0a;
+  localparam CTRL_ENCDEC_BIT  = 0;
+  localparam CTRL_KEYLEN_BIT  = 1;
 
   localparam ADDR_KEY0        = 8'h10;
-  localparam ADDR_KEY1        = 8'h11;
-  localparam ADDR_KEY2        = 8'h12;
-  localparam ADDR_KEY3        = 8'h13;
-  localparam ADDR_KEY4        = 8'h14;
-  localparam ADDR_KEY5        = 8'h15;
-  localparam ADDR_KEY6        = 8'h16;
   localparam ADDR_KEY7        = 8'h17;
 
   localparam ADDR_BLOCK0      = 8'h20;
-  localparam ADDR_BLOCK1      = 8'h21;
-  localparam ADDR_BLOCK2      = 8'h22;
   localparam ADDR_BLOCK3      = 8'h23;
 
   localparam ADDR_RESULT0     = 8'h30;
@@ -93,7 +83,7 @@ module aes(
 
   localparam CORE_NAME0       = 32'h61657320; // "aes "
   localparam CORE_NAME1       = 32'h20202020; // "    "
-  localparam CORE_VERSION     = 32'h302e3831; // "0.81"
+  localparam CORE_VERSION     = 32'h302e3630; // "0.60"
 
 
   //----------------------------------------------------------------
@@ -101,47 +91,19 @@ module aes(
   //----------------------------------------------------------------
   reg init_reg;
   reg init_new;
-  reg init_we;
-  reg init_set;
 
   reg next_reg;
   reg next_new;
-  reg next_we;
-  reg next_set;
-
-  reg error_reg;
-  reg error_new;
-  reg error_we;
 
   reg encdec_reg;
   reg keylen_reg;
   reg config_we;
 
-  reg [31 : 0] block0_reg;
-  reg          block0_we;
-  reg [31 : 0] block1_reg;
-  reg          block1_we;
-  reg [31 : 0] block2_reg;
-  reg          block2_we;
-  reg [31 : 0] block3_reg;
-  reg          block3_we;
-
-  reg [31 : 0] key0_reg;
-  reg          key0_we;
-  reg [31 : 0] key1_reg;
-  reg          key1_we;
-  reg [31 : 0] key2_reg;
-  reg          key2_we;
-  reg [31 : 0] key3_reg;
-  reg          key3_we;
-  reg [31 : 0] key4_reg;
-  reg          key4_we;
-  reg [31 : 0] key5_reg;
-  reg          key5_we;
-  reg [31 : 0] key6_reg;
-  reg          key6_we;
-  reg [31 : 0] key7_reg;
-  reg          key7_we;
+  reg [31 : 0] block_reg [0 : 3];
+  reg          block_we;
+
+  reg [31 : 0] key_reg [0 : 7];
+  reg          key_we;
 
   reg [127 : 0] result_reg;
   reg           valid_reg;
@@ -169,10 +131,11 @@ module aes(
   //----------------------------------------------------------------
   assign read_data = tmp_read_data;
 
-  assign core_key = {key0_reg, key1_reg, key2_reg, key3_reg,
-                     key4_reg, key5_reg, key6_reg, key7_reg};
+  assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
+                     key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
 
-  assign core_block  = {block0_reg, block1_reg, block2_reg, block3_reg};
+  assign core_block  = {block_reg[0], block_reg[1],
+                        block_reg[2], block_reg[3]};
   assign core_init   = init_reg;
   assign core_next   = next_reg;
   assign core_encdec = encdec_reg;
@@ -207,48 +170,33 @@ module aes(
   // active low reset.
   //----------------------------------------------------------------
   always @ (posedge clk or negedge reset_n)
-    begin
+    begin : reg_update
+      integer i;
+
       if (!reset_n)
         begin
-          block0_reg <= 32'h00000000;
-          block1_reg <= 32'h00000000;
-          block2_reg <= 32'h00000000;
-          block3_reg <= 32'h00000000;
-
-          key0_reg   <= 32'h00000000;
-          key1_reg   <= 32'h00000000;
-          key2_reg   <= 32'h00000000;
-          key3_reg   <= 32'h00000000;
-          key4_reg   <= 32'h00000000;
-          key5_reg   <= 32'h00000000;
-          key6_reg   <= 32'h00000000;
-          key7_reg   <= 32'h00000000;
-
-          init_reg   <= 0;
-          next_reg   <= 0;
-          encdec_reg <= 0;
-          keylen_reg <= 0;
-
-          error_reg  <= 0;
-
-          result_reg <= 128'h00000000000000000000000000000000;
-          valid_reg  <= 0;
-          ready_reg  <= 0;
-        end
-      else
-        begin
-          ready_reg      <= core_ready;
-          valid_reg      <= core_valid;
-          result_reg     <= core_result;
+          for (i = 0 ; i < 4 ; i = i + 1)
+            block_reg[i] <= 32'h0;
 
-          if (error_we)
-            error_reg <= error_new;
+          for (i = 0 ; i < 8 ; i = i + 1)
+            key_reg[i] <= 32'h0;
 
-          if (init_we)
-            init_reg <= init_new;
+          init_reg   <= 1'b0;
+          next_reg   <= 1'b0;
+          encdec_reg <= 1'b0;
+          keylen_reg <= 1'b0;
 
-          if (next_we)
-            next_reg <= next_new;
+          result_reg <= 128'h0;
+          valid_reg  <= 1'b0;
+          ready_reg  <= 1'b0;
+        end
+      else
+        begin
+          ready_reg  <= core_ready;
+          valid_reg  <= core_valid;
+          result_reg <= core_result;
+          init_reg   <= init_new;
+          next_reg   <= next_new;
 
           if (config_we)
             begin
@@ -256,245 +204,65 @@ module aes(
               keylen_reg <= write_data[CTRL_KEYLEN_BIT];
             end
 
-          if (key0_we)
-            key0_reg <= write_data;
-
-          if (key1_we)
-            key1_reg <= write_data;
-
-          if (key2_we)
-            key2_reg <= write_data;
-
-          if (key3_we)
-            key3_reg <= write_data;
-
-          if (key4_we)
-            key4_reg <= write_data;
-
-          if (key5_we)
-            key5_reg <= write_data;
-
-          if (key6_we)
-            key6_reg <= write_data;
-
-          if (key7_we)
-            key7_reg <= write_data;
-
-          if (block0_we)
-            block0_reg <= write_data;
-
-          if (block1_we)
-            block1_reg <= write_data;
-
-          if (block2_we)
-            block2_reg <= write_data;
+          if (key_we)
+            key_reg[address[2 : 0]] <= write_data;
 
-          if (block3_we)
-            block3_reg <= write_data;
+          if (block_we)
+            block_reg[address[1 : 0]] <= write_data;
         end
     end // reg_update
 
 
   //----------------------------------------------------------------
-  // flag_ctrl
-  //
-  // Logic to set and automatically reset init- and next
-  // flags that has been set.
-  //----------------------------------------------------------------
-  always @*
-    begin : flag_reset
-      init_new = 0;
-      init_we  = 0;
-      next_new = 0;
-      next_we  = 0;
-
-      if (init_set)
-        begin
-          init_new = 1;
-          init_we  = 1;
-        end
-      else if (init_reg)
-        begin
-          init_new = 0;
-          init_we  = 1;
-        end
-
-      if (next_set)
-        begin
-          next_new = 1;
-          next_we  = 1;
-        end
-      else if (next_reg)
-        begin
-          next_new = 0;
-          next_we  = 1;
-        end
-    end
-
-
-  //----------------------------------------------------------------
   // api
   //
   // The interface command decoding logic.
   //----------------------------------------------------------------
   always @*
     begin : api
-      init_set      = 0;
-      next_set      = 0;
-      config_we     = 0;
-      error_new     = 0;
-      error_we      = 0;
-      key0_we       = 0;
-      key1_we       = 0;
-      key2_we       = 0;
-      key3_we       = 0;
-      key4_we       = 0;
-      key5_we       = 0;
-      key6_we       = 0;
-      key7_we       = 0;
-      block0_we     = 0;
-      block1_we     = 0;
-      block2_we     = 0;
-      block3_we     = 0;
-      tmp_read_data = 32'h00000000;
+      init_new      = 1'b0;
+      next_new      = 1'b0;
+      config_we     = 1'b0;
+      key_we        = 1'b0;
+      block_we      = 1'b0;
+      tmp_read_data = 32'h0;
 
       if (cs)
         begin
           if (we)
             begin
-              case (address)
-                ADDR_CTRL:
-                  begin
-                    init_set = write_data[CTRL_INIT_BIT];
-                    next_set = write_data[CTRL_NEXT_BIT];
-                  end
+              if (address == ADDR_CTRL)
+                begin
+                  init_new = write_data[CTRL_INIT_BIT];
+                  next_new = write_data[CTRL_NEXT_BIT];
+                end
 
-                ADDR_STATUS:
-                  begin
-                    error_new = 0;
-                    error_we  = 1;
-                  end
-
-                ADDR_CONFIG:
-                  config_we = 1;
-
-                ADDR_KEY0:
-                  key0_we = 1;
-
-                ADDR_KEY1:
-                  key1_we = 1;
-
-                ADDR_KEY2:
-                  key2_we = 1;
-
-                ADDR_KEY3:
-                  key3_we = 1;
-
-                ADDR_KEY4:
-                  key4_we = 1;
-
-                ADDR_KEY5:
-                  key5_we = 1;
-
-                ADDR_KEY6:
-                  key6_we = 1;
+              if (address == ADDR_CONFIG)
+                config_we = 1'b1;
 
-                ADDR_KEY7:
-                  key7_we = 1;
+              if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
+                key_we = 1'b1;
 
-                ADDR_BLOCK0:
-                  block0_we = 1;
-
-                ADDR_BLOCK1:
-                  block1_we = 1;
-
-                ADDR_BLOCK2:
-                  block2_we = 1;
-
-                ADDR_BLOCK3:
-                  block3_we = 1;
-
-                default:
-                  begin
-                    error_new = 1;
-                    error_we  = 1;
-                  end
-              endcase // case (address)
+              if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
+                block_we = 1'b1;
             end // if (we)
 
           else
             begin
               case (address)
-                ADDR_NAME0:
-                  tmp_read_data = CORE_NAME0;
-
-                ADDR_NAME1:
-                  tmp_read_data = CORE_NAME1;
-
-                ADDR_VERSION:
-                  tmp_read_data = CORE_VERSION;
-
-                ADDR_CTRL:
-                  tmp_read_data = {28'h0000000, keylen_reg, encdec_reg,
-                                     next_reg, init_reg};
-
-                ADDR_STATUS:
-                  tmp_read_data = {29'h00000000, error_reg, valid_reg, ready_reg};
-
-                ADDR_KEY0:
-                  tmp_read_data = key0_reg;
-
-                ADDR_KEY1:
-                  tmp_read_data = key1_reg;
-
-                ADDR_KEY2:
-                  tmp_read_data = key2_reg;
-
-                ADDR_KEY3:
-                  tmp_read_data = key3_reg;
-
-                ADDR_KEY4:
-                  tmp_read_data = key4_reg;
-
-                ADDR_KEY5:
-                  tmp_read_data = key5_reg;
-
-                ADDR_KEY6:
-                  tmp_read_data = key6_reg;
-
-                ADDR_KEY7:
-                  tmp_read_data = key7_reg;
-
-                ADDR_BLOCK0:
-                  tmp_read_data = block0_reg;
-
-                ADDR_BLOCK1:
-                  tmp_read_data = block1_reg;
-
-                ADDR_BLOCK2:
-                  tmp_read_data = block2_reg;
-
-                ADDR_BLOCK3:
-                  tmp_read_data = block3_reg;
-
-                ADDR_RESULT0:
-                  tmp_read_data = result_reg[127 : 96];
-
-                ADDR_RESULT1:
-                  tmp_read_data = result_reg[95 : 64];
-
-                ADDR_RESULT2:
-                  tmp_read_data = result_reg[63 : 32];
-
-                ADDR_RESULT3:
-                  tmp_read_data = result_reg[31 : 0];
+                ADDR_NAME0:   tmp_read_data = CORE_NAME0;
+                ADDR_NAME1:   tmp_read_data = CORE_NAME1;
+                ADDR_VERSION: tmp_read_data = CORE_VERSION;
+                ADDR_CTRL:    tmp_read_data = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg};
+                ADDR_STATUS:  tmp_read_data = {30'h0, valid_reg, ready_reg};
 
                 default:
                   begin
-                    error_new = 1;
-                    error_we  = 1;
                   end
               endcase // case (address)
+
+              if ((address >= ADDR_RESULT0) && (address <= ADDR_RESULT3))
+                tmp_read_data = result_reg[(3 - (address - ADDR_RESULT0)) * 32 +: 32];
             end
         end
     end // addr_decoder
diff --git a/src/rtl/aes_core.v b/src/rtl/aes_core.v
index c43c943..d06f6ea 100644
--- a/src/rtl/aes_core.v
+++ b/src/rtl/aes_core.v
@@ -60,9 +60,9 @@ module aes_core(
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
-  parameter CTRL_IDLE  = 2'h0;
-  parameter CTRL_INIT  = 2'h1;
-  parameter CTRL_NEXT  = 2'h2;
+  localparam CTRL_IDLE  = 2'h0;
+  localparam CTRL_INIT  = 2'h1;
+  localparam CTRL_NEXT  = 2'h2;
 
 
   //----------------------------------------------------------------
@@ -165,7 +165,7 @@ module aes_core(
                     );
 
 
-  aes_sbox sbox(.sboxw(muxed_sboxw), .new_sboxw(new_sboxw));
+  aes_sbox sbox_inst(.sboxw(muxed_sboxw), .new_sboxw(new_sboxw));
 
 
   //----------------------------------------------------------------
@@ -194,19 +194,13 @@ module aes_core(
       else
         begin
           if (result_valid_we)
-            begin
-              result_valid_reg <= result_valid_new;
-            end
+            result_valid_reg <= result_valid_new;
 
           if (ready_we)
-            begin
-              ready_reg <= ready_new;
-            end
+            ready_reg <= ready_new;
 
           if (aes_core_ctrl_we)
-            begin
-              aes_core_ctrl_reg <= aes_core_ctrl_new;
-            end
+            aes_core_ctrl_reg <= aes_core_ctrl_new;
         end
     end // reg_update
 
@@ -238,8 +232,8 @@ module aes_core(
   //----------------------------------------------------------------
   always @*
     begin : encdec_mux
-      enc_next = 0;
-      dec_next = 0;
+      enc_next = 1'b0;
+      dec_next = 1'b0;
 
       if (encdec)
         begin
@@ -269,64 +263,64 @@ module aes_core(
   //----------------------------------------------------------------
   always @*
     begin : aes_core_ctrl
-      init_state        = 0;
-      ready_new         = 0;
-      ready_we          = 0;
-      result_valid_new  = 0;
-      result_valid_we   = 0;
+      init_state        = 1'b0;
+      ready_new         = 1'b0;
+      ready_we          = 1'b0;
+      result_valid_new  = 1'b0;
+      result_valid_we   = 1'b0;
       aes_core_ctrl_new = CTRL_IDLE;
-      aes_core_ctrl_we  = 0;
+      aes_core_ctrl_we  = 1'b0;
 
       case (aes_core_ctrl_reg)
         CTRL_IDLE:
           begin
             if (init)
               begin
-                init_state        = 1;
-                ready_new         = 0;
-                ready_we          = 1;
-                result_valid_new  = 0;
-                result_valid_we   = 1;
+                init_state        = 1'b1;
+                ready_new         = 1'b0;
+                ready_we          = 1'b1;
+                result_valid_new  = 1'b0;
+                result_valid_we   = 1'b1;
                 aes_core_ctrl_new = CTRL_INIT;
-                aes_core_ctrl_we  = 1;
+                aes_core_ctrl_we  = 1'b1;
               end
             else if (next)
               begin
-                init_state        = 0;
-                ready_new         = 0;
-                ready_we          = 1;
-                result_valid_new  = 0;
-                result_valid_we   = 1;
+                init_state        = 1'b0;
+                ready_new         = 1'b0;
+                ready_we          = 1'b1;
+                result_valid_new  = 1'b0;
+                result_valid_we   = 1'b1;
                 aes_core_ctrl_new = CTRL_NEXT;
-                aes_core_ctrl_we  = 1;
+                aes_core_ctrl_we  = 1'b1;
               end
           end
 
         CTRL_INIT:
           begin
-            init_state = 1;
+            init_state = 1'b1;
 
             if (key_ready)
               begin
-                ready_new         = 1;
-                ready_we          = 1;
+                ready_new         = 1'b1;
+                ready_we          = 1'b1;
                 aes_core_ctrl_new = CTRL_IDLE;
-                aes_core_ctrl_we  = 1;
+                aes_core_ctrl_we  = 1'b1;
               end
           end
 
         CTRL_NEXT:
           begin
-            init_state = 0;
+            init_state = 1'b0;
 
             if (muxed_ready)
               begin
-                ready_new         = 1;
-                ready_we          = 1;
-                result_valid_new  = 1;
-                result_valid_we   = 1;
+                ready_new         = 1'b1;
+                ready_we          = 1'b1;
+                result_valid_new  = 1'b1;
+                result_valid_we   = 1'b1;
                 aes_core_ctrl_new = CTRL_IDLE;
-                aes_core_ctrl_we  = 1;
+                aes_core_ctrl_we  = 1'b1;
              end
           end
 
diff --git a/src/rtl/aes_decipher_block.v b/src/rtl/aes_decipher_block.v
index ebcd164..58e0e46 100644
--- a/src/rtl/aes_decipher_block.v
+++ b/src/rtl/aes_decipher_block.v
@@ -57,23 +57,23 @@ module aes_decipher_block(
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
-  parameter AES_128_BIT_KEY = 1'h0;
-  parameter AES_256_BIT_KEY = 1'h1;
+  localparam AES_128_BIT_KEY = 1'h0;
+  localparam AES_256_BIT_KEY = 1'h1;
 
-  parameter AES128_ROUNDS = 4'ha;
-  parameter AES256_ROUNDS = 4'he;
+  localparam AES128_ROUNDS = 4'ha;
+  localparam AES256_ROUNDS = 4'he;
 
-  parameter NO_UPDATE    = 3'h0;
-  parameter INIT_UPDATE  = 3'h1;
-  parameter SBOX_UPDATE  = 3'h2;
-  parameter MAIN_UPDATE  = 3'h3;
-  parameter FINAL_UPDATE = 3'h4;
+  localparam NO_UPDATE    = 3'h0;
+  localparam INIT_UPDATE  = 3'h1;
+  localparam SBOX_UPDATE  = 3'h2;
+  localparam MAIN_UPDATE  = 3'h3;
+  localparam FINAL_UPDATE = 3'h4;
 
-  parameter CTRL_IDLE  = 3'h0;
-  parameter CTRL_INIT  = 3'h1;
-  parameter CTRL_SBOX  = 3'h2;
-  parameter CTRL_MAIN  = 3'h3;
-  parameter CTRL_FINAL = 3'h4;
+  localparam CTRL_IDLE  = 3'h0;
+  localparam CTRL_INIT  = 3'h1;
+  localparam CTRL_SBOX  = 3'h2;
+  localparam CTRL_MAIN  = 3'h3;
+  localparam CTRL_FINAL = 3'h4;
 
 
   //----------------------------------------------------------------
@@ -228,13 +228,12 @@ module aes_decipher_block(
   reg [31 : 0]  tmp_sboxw;
   wire [31 : 0] new_sboxw;
   reg [2 : 0]   update_type;
-  reg [3 : 0]   num_rounds;
 
 
   //----------------------------------------------------------------
   // Instantiations.
   //----------------------------------------------------------------
-  aes_inv_sbox inv_sbox(.sword(tmp_sboxw), .new_sword(new_sboxw));
+  aes_inv_sbox inv_sbox_inst(.sword(tmp_sboxw), .new_sword(new_sboxw));
 
 
   //----------------------------------------------------------------
@@ -256,56 +255,40 @@ module aes_decipher_block(
     begin: reg_update
       if (!reset_n)
         begin
-          block_w0_reg  <= 32'h00000000;
-          block_w1_reg  <= 32'h00000000;
-          block_w2_reg  <= 32'h00000000;
-          block_w3_reg  <= 32'h00000000;
+          block_w0_reg  <= 32'h0;
+          block_w1_reg  <= 32'h0;
+          block_w2_reg  <= 32'h0;
+          block_w3_reg  <= 32'h0;
           sword_ctr_reg <= 2'h0;
           round_ctr_reg <= 4'h0;
-          ready_reg     <= 1;
+          ready_reg     <= 1'b1;
           dec_ctrl_reg  <= CTRL_IDLE;
         end
       else
         begin
           if (block_w0_we)
-            begin
-              block_w0_reg <= block_new[127 : 096];
-            end
+            block_w0_reg <= block_new[127 : 096];
 
           if (block_w1_we)
-            begin
-              block_w1_reg <= block_new[095 : 064];
-            end
+            block_w1_reg <= block_new[095 : 064];
 
           if (block_w2_we)
-            begin
-              block_w2_reg <= block_new[063 : 032];
-            end
+            block_w2_reg <= block_new[063 : 032];
 
           if (block_w3_we)
-            begin
-              block_w3_reg <= block_new[031 : 000];
-            end
+            block_w3_reg <= block_new[031 : 000];
 
           if (sword_ctr_we)
-            begin
-              sword_ctr_reg <= sword_ctr_new;
-            end
+            sword_ctr_reg <= sword_ctr_new;
 
           if (round_ctr_we)
-            begin
-              round_ctr_reg <= round_ctr_new;
-            end
+            round_ctr_reg <= round_ctr_new;
 
           if (ready_we)
-            begin
-              ready_reg <= ready_new;
-            end
+            ready_reg <= ready_new;
 
           if (dec_ctrl_we)
-            begin
-              dec_ctrl_reg <= dec_ctrl_new;
-            end
+            dec_ctrl_reg <= dec_ctrl_new;
         end
     end // reg_update
 
@@ -320,15 +303,15 @@ module aes_decipher_block(
       reg [127 : 0] old_block, inv_shiftrows_block, inv_mixcolumns_block;
       reg [127 : 0] addkey_block;
 
-      inv_shiftrows_block  = 128'h00000000000000000000000000000000;
-      inv_mixcolumns_block = 128'h00000000000000000000000000000000;
-      addkey_block         = 128'h00000000000000000000000000000000;
-      block_new            = 128'h00000000000000000000000000000000;
-      tmp_sboxw            = 32'h00000000;
-      block_w0_we          = 0;
-      block_w1_we          = 0;
-      block_w2_we          = 0;
-      block_w3_we          = 0;
+      inv_shiftrows_block  = 128'h0;
+      inv_mixcolumns_block = 128'h0;
+      addkey_block         = 128'h0;
+      block_new            = 128'h0;
+      tmp_sboxw            = 32'h0;
+      block_w0_we          = 1'b0;
+      block_w1_we          = 1'b0;
+      block_w2_we          = 1'b0;
+      block_w3_we          = 1'b0;
 
       old_block            = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
 
@@ -341,10 +324,10 @@ module aes_decipher_block(
             addkey_block        = addroundkey(old_block, round_key);
             inv_shiftrows_block = inv_shiftrows(addkey_block);
             block_new           = inv_shiftrows_block;
-            block_w0_we         = 1;
-            block_w1_we         = 1;
-            block_w2_we         = 1;
-            block_w3_we         = 1;
+            block_w0_we         = 1'b1;
+            block_w1_we         = 1'b1;
+            block_w2_we         = 1'b1;
+            block_w3_we         = 1'b1;
           end
 
         SBOX_UPDATE:
@@ -355,25 +338,25 @@ module aes_decipher_block(
               2'h0:
                 begin
                   tmp_sboxw   = block_w0_reg;
-                  block_w0_we = 1;
+                  block_w0_we = 1'b1;
                 end
 
               2'h1:
                 begin
                   tmp_sboxw   = block_w1_reg;
-                  block_w1_we = 1;
+                  block_w1_we = 1'b1;
                 end
 
               2'h2:
                 begin
                   tmp_sboxw   = block_w2_reg;
-                  block_w2_we = 1;
+                  block_w2_we = 1'b1;
                 end
 
               2'h3:
                 begin
                   tmp_sboxw   = block_w3_reg;
-                  block_w3_we = 1;
+                  block_w3_we = 1'b1;
                 end
             endcase // case (sbox_mux_ctrl_reg)
           end
@@ -384,19 +367,19 @@ module aes_decipher_block(
             inv_mixcolumns_block = inv_mixcolumns(addkey_block);
             inv_shiftrows_block  = inv_shiftrows(inv_mixcolumns_block);
             block_new            = inv_shiftrows_block;
-            block_w0_we          = 1;
-            block_w1_we          = 1;
-            block_w2_we          = 1;
-            block_w3_we          = 1;
+            block_w0_we          = 1'b1;
+            block_w1_we          = 1'b1;
+            block_w2_we          = 1'b1;
+            block_w3_we          = 1'b1;
           end
 
         FINAL_UPDATE:
           begin
             block_new    = addroundkey(old_block, round_key);
-            block_w0_we  = 1;
-            block_w1_we  = 1;
-            block_w2_we  = 1;
-            block_w3_we  = 1;
+            block_w0_we  = 1'b1;
+            block_w1_we  = 1'b1;
+            block_w2_we  = 1'b1;
+            block_w3_we  = 1'b1;
           end
 
         default:
@@ -466,65 +449,65 @@ module aes_decipher_block(
   //----------------------------------------------------------------
   always @*
     begin: decipher_ctrl
-      sword_ctr_inc = 0;
-      sword_ctr_rst = 0;
-      round_ctr_dec = 0;
-      round_ctr_set = 0;
-      ready_new     = 0;
-      ready_we      = 0;
+      sword_ctr_inc = 1'b0;
+      sword_ctr_rst = 1'b0;
+      round_ctr_dec = 1'b0;
+      round_ctr_set = 1'b0;
+      ready_new     = 1'b0;
+      ready_we      = 1'b0;
       update_type   = NO_UPDATE;
       dec_ctrl_new  = CTRL_IDLE;
-      dec_ctrl_we   = 0;
+      dec_ctrl_we   = 1'b0;
 
       case(dec_ctrl_reg)
         CTRL_IDLE:
           begin
             if (next)
               begin
-                round_ctr_set = 1;
-                ready_new     = 0;
-                ready_we      = 1;
+                round_ctr_set = 1'b1;
+                ready_new     = 1'b0;
+                ready_we      = 1'b1;
                 dec_ctrl_new  = CTRL_INIT;
-                dec_ctrl_we   = 1;
+                dec_ctrl_we   = 1'b1;
               end
           end
 
         CTRL_INIT:
           begin
-            sword_ctr_rst = 1;
+            sword_ctr_rst = 1'b1;
             update_type   = INIT_UPDATE;
             dec_ctrl_new  = CTRL_SBOX;
-            dec_ctrl_we   = 1;
+            dec_ctrl_we   = 1'b1;
           end
 
         CTRL_SBOX:
           begin
-            sword_ctr_inc = 1;
+            sword_ctr_inc = 1'b1;
             update_type   = SBOX_UPDATE;
             if (sword_ctr_reg == 2'h3)
               begin
-                round_ctr_dec = 1;
+                round_ctr_dec = 1'b1;
                 dec_ctrl_new  = CTRL_MAIN;
-                dec_ctrl_we   = 1;
+                dec_ctrl_we   = 1'b1;
               end
           end
 
         CTRL_MAIN:
           begin
-            sword_ctr_rst = 1;
+            sword_ctr_rst = 1'b1;
             if (round_ctr_reg > 0)
               begin
                 update_type   = MAIN_UPDATE;
                 dec_ctrl_new  = CTRL_SBOX;
-                dec_ctrl_we   = 1;
+                dec_ctrl_we   = 1'b1;
               end
             else
               begin
                 update_type  = FINAL_UPDATE;
-                ready_new    = 1;
-                ready_we     = 1;
+                ready_new    = 1'b1;
+                ready_we     = 1'b1;
                 dec_ctrl_new = CTRL_IDLE;
-                dec_ctrl_we  = 1;
+                dec_ctrl_we  = 1'b1;
               end
           end
 
diff --git a/src/rtl/aes_encipher_block.v b/src/rtl/aes_encipher_block.v
index 2761d5b..14c79b2 100644
--- a/src/rtl/aes_encipher_block.v
+++ b/src/rtl/aes_encipher_block.v
@@ -60,23 +60,23 @@ module aes_encipher_block(
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
-  parameter AES_128_BIT_KEY = 1'h0;
-  parameter AES_256_BIT_KEY = 1'h1;
+  localparam AES_128_BIT_KEY = 1'h0;
+  localparam AES_256_BIT_KEY = 1'h1;
 
-  parameter AES128_ROUNDS = 4'ha;
-  parameter AES256_ROUNDS = 4'he;
+  localparam AES128_ROUNDS = 4'ha;
+  localparam AES256_ROUNDS = 4'he;
 
-  parameter NO_UPDATE    = 3'h0;
-  parameter INIT_UPDATE  = 3'h1;
-  parameter SBOX_UPDATE  = 3'h2;
-  parameter MAIN_UPDATE  = 3'h3;
-  parameter FINAL_UPDATE = 3'h4;
+  localparam NO_UPDATE    = 3'h0;
+  localparam INIT_UPDATE  = 3'h1;
+  localparam SBOX_UPDATE  = 3'h2;
+  localparam MAIN_UPDATE  = 3'h3;
+  localparam FINAL_UPDATE = 3'h4;
 
-  parameter CTRL_IDLE  = 3'h0;
-  parameter CTRL_INIT  = 3'h1;
-  parameter CTRL_SBOX  = 3'h2;
-  parameter CTRL_MAIN  = 3'h3;
-  parameter CTRL_FINAL = 3'h4;
+  localparam CTRL_IDLE  = 3'h0;
+  localparam CTRL_INIT  = 3'h1;
+  localparam CTRL_SBOX  = 3'h2;
+  localparam CTRL_MAIN  = 3'h3;
+  localparam CTRL_FINAL = 3'h4;
 
 
   //----------------------------------------------------------------
@@ -216,56 +216,40 @@ module aes_encipher_block(
     begin: reg_update
       if (!reset_n)
         begin
-          block_w0_reg  <= 32'h00000000;
-          block_w1_reg  <= 32'h00000000;
-          block_w2_reg  <= 32'h00000000;
-          block_w3_reg  <= 32'h00000000;
+          block_w0_reg  <= 32'h0;
+          block_w1_reg  <= 32'h0;
+          block_w2_reg  <= 32'h0;
+          block_w3_reg  <= 32'h0;
           sword_ctr_reg <= 2'h0;
           round_ctr_reg <= 4'h0;
-          ready_reg     <= 1;
+          ready_reg     <= 1'b1;
           enc_ctrl_reg  <= CTRL_IDLE;
         end
       else
         begin
           if (block_w0_we)
-            begin
-              block_w0_reg <= block_new[127 : 096];
-            end
+            block_w0_reg <= block_new[127 : 096];
 
           if (block_w1_we)
-            begin
-              block_w1_reg <= block_new[095 : 064];
-            end
+            block_w1_reg <= block_new[095 : 064];
 
           if (block_w2_we)
-            begin
-              block_w2_reg <= block_new[063 : 032];
-            end
+            block_w2_reg <= block_new[063 : 032];
 
           if (block_w3_we)
-            begin
-              block_w3_reg <= block_new[031 : 000];
-            end
+            block_w3_reg <= block_new[031 : 000];
 
           if (sword_ctr_we)
-            begin
-              sword_ctr_reg <= sword_ctr_new;
-            end
+            sword_ctr_reg <= sword_ctr_new;
 
           if (round_ctr_we)
-            begin
-              round_ctr_reg <= round_ctr_new;
-            end
+            round_ctr_reg <= round_ctr_new;
 
           if (ready_we)
-            begin
-              ready_reg <= ready_new;
-            end
+            ready_reg <= ready_new;
 
           if (enc_ctrl_we)
-            begin
-              enc_ctrl_reg <= enc_ctrl_new;
-            end
+            enc_ctrl_reg <= enc_ctrl_new;
         end
     end // reg_update
 
@@ -280,12 +264,12 @@ module aes_encipher_block(
       reg [127 : 0] old_block, shiftrows_block, mixcolumns_block;
       reg [127 : 0] addkey_init_block, addkey_main_block, addkey_final_block;
 
-      block_new    = 128'h00000000000000000000000000000000;
-      muxed_sboxw  = 32'h00000000;
-      block_w0_we  = 0;
-      block_w1_we  = 0;
-      block_w2_we  = 0;
-      block_w3_we  = 0;
+      block_new   = 128'h0;
+      muxed_sboxw = 32'h0;
+      block_w0_we = 1'b0;
+      block_w1_we = 1'b0;
+      block_w2_we = 1'b0;
+      block_w3_we = 1'b0;
 
       old_block          = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
       shiftrows_block    = shiftrows(old_block);
@@ -298,10 +282,10 @@ module aes_encipher_block(
         INIT_UPDATE:
           begin
             block_new    = addkey_init_block;
-            block_w0_we  = 1;
-            block_w1_we  = 1;
-            block_w2_we  = 1;
-            block_w3_we  = 1;
+            block_w0_we  = 1'b1;
+            block_w1_we  = 1'b1;
+            block_w2_we  = 1'b1;
+            block_w3_we  = 1'b1;
           end
 
         SBOX_UPDATE:
@@ -312,25 +296,25 @@ module aes_encipher_block(
               2'h0:
                 begin
                   muxed_sboxw = block_w0_reg;
-                  block_w0_we = 1;
+                  block_w0_we = 1'b1;
                 end
 
               2'h1:
                 begin
                   muxed_sboxw = block_w1_reg;
-                  block_w1_we = 1;
+                  block_w1_we = 1'b1;
                 end
 
               2'h2:
                 begin
                   muxed_sboxw = block_w2_reg;
-                  block_w2_we = 1;
+                  block_w2_we = 1'b1;
                 end
 
               2'h3:
                 begin
                   muxed_sboxw = block_w3_reg;
-                  block_w3_we = 1;
+                  block_w3_we = 1'b1;
                 end
             endcase // case (sbox_mux_ctrl_reg)
           end
@@ -338,19 +322,19 @@ module aes_encipher_block(
         MAIN_UPDATE:
           begin
             block_new    = addkey_main_block;
-            block_w0_we  = 1;
-            block_w1_we  = 1;
-            block_w2_we  = 1;
-            block_w3_we  = 1;
+            block_w0_we  = 1'b1;
+            block_w1_we  = 1'b1;
+            block_w2_we  = 1'b1;
+            block_w3_we  = 1'b1;
           end
 
         FINAL_UPDATE:
           begin
             block_new    = addkey_final_block;
-            block_w0_we  = 1;
-            block_w1_we  = 1;
-            block_w2_we  = 1;
-            block_w3_we  = 1;
+            block_w0_we  = 1'b1;
+            block_w1_we  = 1'b1;
+            block_w2_we  = 1'b1;
+            block_w3_we  = 1'b1;
           end
 
         default:
@@ -424,66 +408,66 @@ module aes_encipher_block(
           num_rounds = AES128_ROUNDS;
         end
 
-      sword_ctr_inc = 0;
-      sword_ctr_rst = 0;
-      round_ctr_inc = 0;
-      round_ctr_rst = 0;
-      ready_new     = 0;
-      ready_we      = 0;
+      sword_ctr_inc = 1'b0;
+      sword_ctr_rst = 1'b0;
+      round_ctr_inc = 1'b0;
+      round_ctr_rst = 1'b0;
+      ready_new     = 1'b0;
+      ready_we      = 1'b0;
       update_type   = NO_UPDATE;
       enc_ctrl_new  = CTRL_IDLE;
-      enc_ctrl_we   = 0;
+      enc_ctrl_we   = 1'b0;
 
       case(enc_ctrl_reg)
         CTRL_IDLE:
           begin
             if (next)
               begin
-                round_ctr_rst = 1;
-                ready_new     = 0;
-                ready_we      = 1;
+                round_ctr_rst = 1'b1;
+                ready_new     = 1'b0;
+                ready_we      = 1'b1;
                 enc_ctrl_new  = CTRL_INIT;
-                enc_ctrl_we   = 1;
+                enc_ctrl_we   = 1'b1;
               end
           end
 
         CTRL_INIT:
           begin
-            round_ctr_inc = 1;
-            sword_ctr_rst = 1;
+            round_ctr_inc = 1'b1;
+            sword_ctr_rst = 1'b1;
             update_type   = INIT_UPDATE;
             enc_ctrl_new  = CTRL_SBOX;
-            enc_ctrl_we   = 1;
+            enc_ctrl_we   = 1'b1;
           end
 
         CTRL_SBOX:
           begin
-            sword_ctr_inc = 1;
+            sword_ctr_inc = 1'b1;
             update_type   = SBOX_UPDATE;
             if (sword_ctr_reg == 2'h3)
               begin
                 enc_ctrl_new  = CTRL_MAIN;
-                enc_ctrl_we   = 1;
+                enc_ctrl_we   = 1'b1;
               end
           end
 
         CTRL_MAIN:
           begin
-            sword_ctr_rst = 1;
-            round_ctr_inc = 1;
+            sword_ctr_rst = 1'b1;
+            round_ctr_inc = 1'b1;
             if (round_ctr_reg < num_rounds)
               begin
                 update_type   = MAIN_UPDATE;
                 enc_ctrl_new  = CTRL_SBOX;
-                enc_ctrl_we   = 1;
+                enc_ctrl_we   = 1'b1;
               end
             else
               begin
                 update_type  = FINAL_UPDATE;
-                ready_new    = 1;
-                ready_we     = 1;
+                ready_new    = 1'b1;
+                ready_we     = 1'b1;
                 enc_ctrl_new = CTRL_IDLE;
-                enc_ctrl_we  = 1;
+                enc_ctrl_we  = 1'b1;
               end
           end
 
diff --git a/src/rtl/aes_key_mem.v b/src/rtl/aes_key_mem.v
index e681c93..3a4c855 100644
--- a/src/rtl/aes_key_mem.v
+++ b/src/rtl/aes_key_mem.v
@@ -2,7 +2,7 @@
 //
 // aes_key_mem.v
 // -------------
-// The AES key memort including round key generator.
+// The AES key memory including round key generator.
 //
 //
 // Author: Joachim Strombergson
@@ -57,16 +57,16 @@ module aes_key_mem(
   //----------------------------------------------------------------
   // Parameters.
   //----------------------------------------------------------------
-  parameter AES_128_BIT_KEY = 1'h0;
-  parameter AES_256_BIT_KEY = 1'h1;
+  localparam AES_128_BIT_KEY = 1'h0;
+  localparam AES_256_BIT_KEY = 1'h1;
 
-  parameter AES_128_NUM_ROUNDS = 4'ha;
-  parameter AES_256_NUM_ROUNDS = 4'he;
+  localparam AES_128_NUM_ROUNDS = 4'ha;
+  localparam AES_256_NUM_ROUNDS = 4'he;
 
-  parameter CTRL_IDLE     = 3'h0;
-  parameter CTRL_INIT     = 3'h1;
-  parameter CTRL_GENERATE = 3'h2;
-  parameter CTRL_DONE     = 3'h3;
+  localparam CTRL_IDLE     = 3'h0;
+  localparam CTRL_INIT     = 3'h1;
+  localparam CTRL_GENERATE = 3'h2;
+  localparam CTRL_DONE     = 3'h3;
 
 
   //----------------------------------------------------------------
@@ -133,66 +133,40 @@ module aes_key_mem(
   //----------------------------------------------------------------
   always @ (posedge clk or negedge reset_n)
     begin: reg_update
+      integer i;
+
       if (!reset_n)
         begin
-          key_mem [0]      <= 128'h00000000000000000000000000000000;
-          key_mem [1]      <= 128'h00000000000000000000000000000000;
-          key_mem [2]      <= 128'h00000000000000000000000000000000;
-          key_mem [3]      <= 128'h00000000000000000000000000000000;
-          key_mem [4]      <= 128'h00000000000000000000000000000000;
-          key_mem [5]      <= 128'h00000000000000000000000000000000;
-          key_mem [6]      <= 128'h00000000000000000000000000000000;
-          key_mem [7]      <= 128'h00000000000000000000000000000000;
-          key_mem [8]      <= 128'h00000000000000000000000000000000;
-          key_mem [9]      <= 128'h00000000000000000000000000000000;
-          key_mem [10]     <= 128'h00000000000000000000000000000000;
-          key_mem [11]     <= 128'h00000000000000000000000000000000;
-          key_mem [12]     <= 128'h00000000000000000000000000000000;
-          key_mem [13]     <= 128'h00000000000000000000000000000000;
-          key_mem [14]     <= 128'h00000000000000000000000000000000;
-          prev_key0_reg    <= 128'h00000000000000000000000000000000;
-          prev_key1_reg    <= 128'h00000000000000000000000000000000;
-          rcon_reg         <= 8'h00;
-          ready_reg        <= 0;
+          for (i = 0 ; i < 4 ; i = i + 1)
+            key_mem [i] <= 128'h0;
+
+          rcon_reg         <= 8'h0;
+          ready_reg        <= 1'b0;
           round_ctr_reg    <= 4'h0;
           key_mem_ctrl_reg <= CTRL_IDLE;
         end
       else
         begin
           if (round_ctr_we)
-            begin
-              round_ctr_reg <= round_ctr_new;
-            end
+            round_ctr_reg <= round_ctr_new;
 
           if (ready_we)
-            begin
-              ready_reg <= ready_new;
-            end
+            ready_reg <= ready_new;
 
           if (rcon_we)
-            begin
-              rcon_reg <= rcon_new;
-            end
+            rcon_reg <= rcon_new;
 
           if (key_mem_we)
-            begin
-              key_mem[round_ctr_reg] <= key_mem_new;
-            end
+            key_mem[round_ctr_reg] <= key_mem_new;
 
           if (prev_key0_we)
-            begin
-              prev_key0_reg <= prev_key0_new;
-            end
+            prev_key0_reg <= prev_key0_new;
 
           if (prev_key1_we)
-            begin
-              prev_key1_reg <= prev_key1_new;
-            end
+            prev_key1_reg <= prev_key1_new;
 
           if (key_mem_ctrl_we)
-            begin
-              key_mem_ctrl_reg <= key_mem_ctrl_new;
-            end
+            key_mem_ctrl_reg <= key_mem_ctrl_new;
         end
     end // reg_update
 
@@ -220,20 +194,20 @@ module aes_key_mem(
       reg [31 : 0] rconw, rotstw, tw, trw;
 
       // Default assignments.
-      key_mem_new   = 128'h00000000000000000000000000000000;
-      key_mem_we    = 0;
-      prev_key0_new = 128'h00000000000000000000000000000000;
-      prev_key0_we  = 0;
-      prev_key1_new = 128'h00000000000000000000000000000000;
-      prev_key1_we  = 0;
+      key_mem_new   = 128'h0;
+      key_mem_we    = 1'b0;
+      prev_key0_new = 128'h0;
+      prev_key0_we  = 1'b0;
+      prev_key1_new = 128'h0;
+      prev_key1_we  = 1'b0;
 
-      k0 = 32'h00000000;
-      k1 = 32'h00000000;
-      k2 = 32'h00000000;
-      k3 = 32'h00000000;
+      k0 = 32'h0;
+      k1 = 32'h0;
+      k2 = 32'h0;
+      k3 = 32'h0;
 
-      rcon_set   = 1;
-      rcon_next  = 0;
+      rcon_set   = 1'b1;
+      rcon_next  = 1'b0;
 
       // Extract words and calculate intermediate values.
       // Perform rotation of sbox word etc.
@@ -247,7 +221,7 @@ module aes_key_mem(
       w6 = prev_key1_reg[063 : 032];
       w7 = prev_key1_reg[031 : 000];
 
-      rconw = {rcon_reg, 24'h000000};
+      rconw = {rcon_reg, 24'h0};
       tmp_sboxw = w7;
       rotstw = {new_sboxw[23 : 00], new_sboxw[31 : 24]};
       trw = rotstw ^ rconw;
@@ -256,8 +230,8 @@ module aes_key_mem(
       // Generate the specific round keys.
       if (round_key_update)
         begin
-          rcon_set   = 0;
-          key_mem_we = 1;
+          rcon_set   = 1'b0;
+          key_mem_we = 1'b1;
           case (keylen)
             AES_128_BIT_KEY:
               begin
@@ -265,8 +239,8 @@ module aes_key_mem(
                   begin
                     key_mem_new   = key[255 : 128];
                     prev_key1_new = key[255 : 128];
-                    prev_key1_we  = 1;
-                    rcon_next     = 1;
+                    prev_key1_we  = 1'b1;
+                    rcon_next     = 1'b1;
                   end
                 else
                   begin
@@ -277,8 +251,8 @@ module aes_key_mem(
 
                     key_mem_new   = {k0, k1, k2, k3};
                     prev_key1_new = {k0, k1, k2, k3};
-                    prev_key1_we  = 1;
-                    rcon_next     = 1;
+                    prev_key1_we  = 1'b1;
+                    rcon_next     = 1'b1;
                   end
               end
 
@@ -288,14 +262,14 @@ module aes_key_mem(
                   begin
                     key_mem_new   = key[255 : 128];
                     prev_key0_new = key[255 : 128];
-                    prev_key0_we  = 1;
+                    prev_key0_we  = 1'b1;
                   end
                 else if (round_ctr_reg == 1)
                   begin
                     key_mem_new   = key[127 : 0];
                     prev_key1_new = key[127 : 0];
-                    prev_key1_we  = 1;
-                    rcon_next     = 1;
+                    prev_key1_we  = 1'b1;
+                    rcon_next     = 1'b1;
                   end
                 else
                   begin
@@ -312,15 +286,15 @@ module aes_key_mem(
                         k1 = w1 ^ w0 ^ tw;
                         k2 = w2 ^ w1 ^ w0 ^ tw;
                         k3 = w3 ^ w2 ^ w1 ^ w0 ^ tw;
-                        rcon_next = 1;
+                        rcon_next = 1'b1;
                       end
 
                     // Store the generated round keys.
                     key_mem_new   = {k0, k1, k2, k3};
                     prev_key1_new = {k0, k1, k2, k3};
-                    prev_key1_we  = 1;
+                    prev_key1_we  = 1'b1;
                     prev_key0_new = prev_key1_reg;
-                    prev_key0_we  = 1;
+                    prev_key0_we  = 1'b1;
                   end
               end
 
@@ -342,20 +316,20 @@ module aes_key_mem(
     begin : rcon_logic
       reg [7 : 0] tmp_rcon;
       rcon_new = 8'h00;
-      rcon_we  = 0;
+      rcon_we  = 1'b0;
 
       tmp_rcon = {rcon_reg[6 : 0], 1'b0} ^ (8'h1b & {8{rcon_reg[7]}});
 
       if (rcon_set)
         begin
           rcon_new = 8'h8d;
-          rcon_we  = 1;
+          rcon_we  = 1'b1;
         end
 
       if (rcon_next)
         begin
-          rcon_new  = tmp_rcon[7 : 0];
-          rcon_we  = 1;
+          rcon_new = tmp_rcon[7 : 0];
+          rcon_we  = 1'b1;
         end
     end
 
@@ -368,18 +342,18 @@ module aes_key_mem(
   always @*
     begin : round_ctr
       round_ctr_new = 4'h0;
-      round_ctr_we  = 0;
+      round_ctr_we  = 1'b0;
 
       if (round_ctr_rst)
         begin
           round_ctr_new = 4'h0;
-          round_ctr_we  = 1;
+          round_ctr_we  = 1'b1;
         end
 
       else if (round_ctr_inc)
         begin
           round_ctr_new = round_ctr_reg + 1'b1;
-          round_ctr_we  = 1;
+          round_ctr_we  = 1'b1;
         end
     end
 
@@ -420,50 +394,50 @@ module aes_key_mem(
   always @*
     begin: key_mem_ctrl
       // Default assignments.
-      ready_new        = 0;
-      ready_we         = 0;
-      round_key_update = 0;
-      round_ctr_rst    = 0;
-      round_ctr_inc    = 0;
+      ready_new        = 1'b0;
+      ready_we         = 1'b0;
+      round_key_update = 1'b0;
+      round_ctr_rst    = 1'b0;
+      round_ctr_inc    = 1'b0;
       key_mem_ctrl_new = CTRL_IDLE;
-      key_mem_ctrl_we  = 0;
+      key_mem_ctrl_we  = 1'b0;
 
       case(key_mem_ctrl_reg)
         CTRL_IDLE:
           begin
             if (init)
               begin
-                ready_new        = 0;
-                ready_we         = 1;
+                ready_new        = 1'b0;
+                ready_we         = 1'b1;
                 key_mem_ctrl_new = CTRL_INIT;
-                key_mem_ctrl_we  = 1;
+                key_mem_ctrl_we  = 1'b1;
               end
           end
 
         CTRL_INIT:
           begin
-            round_ctr_rst    = 1;
+            round_ctr_rst    = 1'b1;
             key_mem_ctrl_new = CTRL_GENERATE;
-            key_mem_ctrl_we  = 1;
+            key_mem_ctrl_we  = 1'b1;
           end
 
         CTRL_GENERATE:
           begin
-            round_ctr_inc    = 1;
-            round_key_update = 1;
+            round_ctr_inc    = 1'b1;
+            round_key_update = 1'b1;
             if (round_ctr_reg == num_rounds)
               begin
                 key_mem_ctrl_new = CTRL_DONE;
-                key_mem_ctrl_we  = 1;
+                key_mem_ctrl_we  = 1'b1;
               end
           end
 
         CTRL_DONE:
           begin
-            ready_new        = 1;
-            ready_we         = 1;
+            ready_new        = 1'b1;
+            ready_we         = 1'b1;
             key_mem_ctrl_new = CTRL_IDLE;
-            key_mem_ctrl_we  = 1;
+            key_mem_ctrl_we  = 1'b1;
           end
 
         default:
diff --git a/src/tb/tb_aes.v b/src/tb/tb_aes.v
index 377ed76..cb42010 100644
--- a/src/tb/tb_aes.v
+++ b/src/tb/tb_aes.v
@@ -37,12 +37,6 @@
 //======================================================================
 
 //------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
-
-//------------------------------------------------------------------
 // Test module.
 //------------------------------------------------------------------
 module tb_aes();
@@ -50,52 +44,52 @@ module tb_aes();
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
-  localparam DEBUG     = 0;
+  parameter DEBUG     = 0;
 
-  localparam CLK_HALF_PERIOD = 1;
-  localparam CLK_PERIOD      = 2 * CLK_HALF_PERIOD;
+  parameter CLK_HALF_PERIOD = 1;
+  parameter CLK_PERIOD      = 2 * CLK_HALF_PERIOD;
 
   // The DUT address map.
-  localparam ADDR_NAME0       = 8'h00;
-  localparam ADDR_NAME1       = 8'h01;
-  localparam ADDR_VERSION     = 8'h02;
+  parameter ADDR_NAME0       = 8'h00;
+  parameter ADDR_NAME1       = 8'h01;
+  parameter ADDR_VERSION     = 8'h02;
 
-  localparam ADDR_CTRL        = 8'h08;
-  localparam CTRL_INIT_BIT    = 0;
-  localparam CTRL_NEXT_BIT    = 1;
+  parameter ADDR_CTRL        = 8'h08;
+  parameter CTRL_INIT_BIT    = 0;
+  parameter CTRL_NEXT_BIT    = 1;
+  parameter CTRL_ENCDEC_BIT  = 2;
+  parameter CTRL_KEYLEN_BIT  = 3;
 
-  localparam ADDR_STATUS      = 8'h09;
-  localparam STATUS_READY_BIT = 0;
-  localparam STATUS_VALID_BIT = 1;
+  parameter ADDR_STATUS      = 8'h09;
+  parameter STATUS_READY_BIT = 0;
+  parameter STATUS_VALID_BIT = 1;
 
-  localparam ADDR_CONFIG      = 8'h0a;
-  localparam CTRL_ENCDEC_BIT  = 2;
-  localparam CTRL_KEYLEN_BIT  = 3;
+  parameter ADDR_CONFIG      = 8'h0a;
 
-  localparam ADDR_KEY0        = 8'h10;
-  localparam ADDR_KEY1        = 8'h11;
-  localparam ADDR_KEY2        = 8'h12;
-  localparam ADDR_KEY3        = 8'h13;
-  localparam ADDR_KEY4        = 8'h14;
-  localparam ADDR_KEY5        = 8'h15;
-  localparam ADDR_KEY6        = 8'h16;
-  localparam ADDR_KEY7        = 8'h17;
+  parameter ADDR_KEY0        = 8'h10;
+  parameter ADDR_KEY1        = 8'h11;
+  parameter ADDR_KEY2        = 8'h12;
+  parameter ADDR_KEY3        = 8'h13;
+  parameter ADDR_KEY4        = 8'h14;
+  parameter ADDR_KEY5        = 8'h15;
+  parameter ADDR_KEY6        = 8'h16;
+  parameter ADDR_KEY7        = 8'h17;
 
-  localparam ADDR_BLOCK0      = 8'h20;
-  localparam ADDR_BLOCK1      = 8'h21;
-  localparam ADDR_BLOCK2      = 8'h22;
-  localparam ADDR_BLOCK3      = 8'h23;
+  parameter ADDR_BLOCK0      = 8'h20;
+  parameter ADDR_BLOCK1      = 8'h21;
+  parameter ADDR_BLOCK2      = 8'h22;
+  parameter ADDR_BLOCK3      = 8'h23;
 
-  localparam ADDR_RESULT0     = 8'h30;
-  localparam ADDR_RESULT1     = 8'h31;
-  localparam ADDR_RESULT2     = 8'h32;
-  localparam ADDR_RESULT3     = 8'h33;
+  parameter ADDR_RESULT0     = 8'h30;
+  parameter ADDR_RESULT1     = 8'h31;
+  parameter ADDR_RESULT2     = 8'h32;
+  parameter ADDR_RESULT3     = 8'h33;
 
-  localparam AES_128_BIT_KEY = 0;
-  localparam AES_256_BIT_KEY = 1;
+  parameter AES_128_BIT_KEY = 0;
+  parameter AES_256_BIT_KEY = 1;
 
-  localparam AES_DECIPHER = 1'b0;
-  localparam AES_ENCIPHER = 1'b1;
+  parameter AES_DECIPHER = 1'b0;
+  parameter AES_ENCIPHER = 1'b1;
 
 
   //----------------------------------------------------------------
@@ -132,11 +126,6 @@ module tb_aes();
 
 
   //----------------------------------------------------------------
-  // Concurrent assignments.
-  //----------------------------------------------------------------
-
-
-  //----------------------------------------------------------------
   // clk_gen
   //
   // Always running clock generator process.
@@ -172,7 +161,7 @@ module tb_aes();
   //
   // Dump the state of the dump when needed.
   //----------------------------------------------------------------
-  task dump_dut_state();
+  task dump_dut_state;
     begin
       $display("cycle: 0x%016x", cycle_ctr);
       $display("State of DUT");
@@ -182,7 +171,7 @@ module tb_aes();
       $display("");
 
       $display("block: 0x%08x, 0x%08x, 0x%08x, 0x%08x",
-               dut.block0_reg, dut.block1_reg, dut.block2_reg, dut.block3_reg);
+               dut.block_reg[0], dut.block_reg[1], dut.block_reg[2], dut.block_reg[3]);
       $display("");
 
     end
@@ -194,7 +183,7 @@ module tb_aes();
   //
   // Toggle reset to put the DUT into a well known state.
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -211,7 +200,7 @@ module tb_aes();
   //
   // Display the accumulated test results.
   //----------------------------------------------------------------
-  task display_test_results();
+  task display_test_results;
     begin
       if (error_ctr == 0)
         begin
@@ -232,19 +221,19 @@ module tb_aes();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
-      cycle_ctr          = 0;
-      error_ctr          = 0;
-      tc_ctr             = 0;
+      cycle_ctr     = 0;
+      error_ctr     = 0;
+      tc_ctr        = 0;
 
-      tb_clk             = 0;
-      tb_reset_n         = 1;
+      tb_clk        = 0;
+      tb_reset_n    = 1;
 
-      tb_cs              = 0;
-      tb_we              = 0;
-      tb_address         = 8'h00;
-      tb_write_data      = 32'h00000000;
+      tb_cs         = 0;
+      tb_we         = 0;
+      tb_address    = 8'h0;
+      tb_write_data = 32'h0;
     end
   endtask // init_sim
 
@@ -254,7 +243,7 @@ module tb_aes();
   //
   // Write the given word to the DUT using the DUT interface.
   //----------------------------------------------------------------
-  task write_word(input [11 : 0]  address,
+  task write_word(input [11 : 0] address,
                   input [31 : 0] word);
     begin
       if (DEBUG)
@@ -319,7 +308,7 @@ module tb_aes();
   //
   // Read the result block in the dut.
   //----------------------------------------------------------------
-  task read_result();
+  task read_result;
     begin
       read_word(ADDR_RESULT0);
       result_data[127 : 096] = read_data;
@@ -385,12 +374,13 @@ module tb_aes();
                                   input [127 : 0] expected);
     begin
       $display("*** TC %0d ECB mode test started.", tc_number);
+      tc_ctr = tc_ctr + 1;
 
       init_key(key, key_length);
       write_block(block);
       dump_dut_state();
 
-      write_word(ADDR_CONFIG, (8'h00 + (key_length << 1) + encdec));
+      write_word(ADDR_CONFIG, (8'h00 + (key_length << 1)+ encdec));
       write_word(ADDR_CTRL, 8'h02);
 
       #(100 * CLK_PERIOD);
@@ -399,7 +389,6 @@ module tb_aes();
 
       if (result_data == expected)
         begin
-          tc_ctr = tc_ctr  + 1;
           $display("*** TC %0d successful.", tc_number);
           $display("");
         end
@@ -421,7 +410,7 @@ module tb_aes();
   //
   // Main test task will perform complete NIST test of AES.
   //----------------------------------------------------------------
-  task aes_test();
+  task aes_test;
     reg [255 : 0] nist_aes128_key;
     reg [255 : 0] nist_aes256_key;
 
@@ -526,7 +515,6 @@ module tb_aes();
   //----------------------------------------------------------------
   initial
     begin : main
-
       $display("   -= Testbench for AES started =-");
       $display("    ==============================");
       $display("");
diff --git a/src/tb/tb_aes_core.v b/src/tb/tb_aes_core.v
index 426e817..7f6791e 100644
--- a/src/tb/tb_aes_core.v
+++ b/src/tb/tb_aes_core.v
@@ -37,12 +37,6 @@
 //======================================================================
 
 //------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
-
-//------------------------------------------------------------------
 // Test module.
 //------------------------------------------------------------------
 module tb_aes_core();
@@ -137,7 +131,7 @@ module tb_aes_core();
   //
   // Dump the state of the dump when needed.
   //----------------------------------------------------------------
-  task dump_dut_state();
+  task dump_dut_state;
     begin
       $display("State of DUT");
       $display("------------");
@@ -164,7 +158,7 @@ module tb_aes_core();
   //
   // Dump the keys in the key memory of the dut.
   //----------------------------------------------------------------
-  task dump_keys();
+  task dump_keys;
     begin
       $display("State of key memory in DUT:");
       $display("key[00] = 0x%016x", dut.keymem.key_mem[00]);
@@ -192,7 +186,7 @@ module tb_aes_core();
   //
   // Toggle reset to put the DUT into a well known state.
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -208,7 +202,7 @@ module tb_aes_core();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
       cycle_ctr = 0;
       error_ctr = 0;
@@ -232,7 +226,7 @@ module tb_aes_core();
   //
   // Display the accumulated test results.
   //----------------------------------------------------------------
-  task display_test_result();
+  task display_test_result;
     begin
       if (error_ctr == 0)
         begin
@@ -256,7 +250,7 @@ module tb_aes_core();
   // when the dut is actively processing and will in fact at some
   // point set the flag.
   //----------------------------------------------------------------
-  task wait_ready();
+  task wait_ready;
     begin
       while (!tb_ready)
         begin
@@ -279,7 +273,7 @@ module tb_aes_core();
   // when the dut is actively processing a block and will in fact
   // at some point set the flag.
   //----------------------------------------------------------------
-  task wait_valid();
+  task wait_valid;
     begin
       while (!tb_result_valid)
         begin
diff --git a/src/tb/tb_aes_decipher_block.v b/src/tb/tb_aes_decipher_block.v
index 5a89102..8d125f6 100644
--- a/src/tb/tb_aes_decipher_block.v
+++ b/src/tb/tb_aes_decipher_block.v
@@ -37,12 +37,6 @@
 //======================================================================
 
 //------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
-
-//------------------------------------------------------------------
 // Test module.
 //------------------------------------------------------------------
 module tb_aes_decipher_block();
@@ -144,7 +138,7 @@ module tb_aes_decipher_block();
   //
   // Dump the state of the dump when needed.
   //----------------------------------------------------------------
-  task dump_dut_state();
+  task dump_dut_state;
     begin
       $display("State of DUT");
       $display("------------");
@@ -184,7 +178,7 @@ module tb_aes_decipher_block();
   //
   // Toggle reset to put the DUT into a well known state.
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -200,7 +194,7 @@ module tb_aes_decipher_block();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
       cycle_ctr    = 0;
       error_ctr    = 0;
@@ -222,7 +216,7 @@ module tb_aes_decipher_block();
   //
   // Display the accumulated test results.
   //----------------------------------------------------------------
-  task display_test_result();
+  task display_test_result;
     begin
       if (error_ctr == 0)
         begin
@@ -246,7 +240,7 @@ module tb_aes_decipher_block();
   // when the dut is actively processing and will in fact at some
   // point set the flag.
   //----------------------------------------------------------------
-  task wait_ready();
+  task wait_ready;
     begin
       while (!tb_ready)
         begin
diff --git a/src/tb/tb_aes_encipher_block.v b/src/tb/tb_aes_encipher_block.v
index 39d7c26..c471bb5 100644
--- a/src/tb/tb_aes_encipher_block.v
+++ b/src/tb/tb_aes_encipher_block.v
@@ -37,12 +37,6 @@
 //======================================================================
 
 //------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
-
-//------------------------------------------------------------------
 // Test module.
 //------------------------------------------------------------------
 module tb_aes_encipher_block();
@@ -158,7 +152,7 @@ module tb_aes_encipher_block();
   //
   // Dump the state of the dump when needed.
   //----------------------------------------------------------------
-  task dump_dut_state();
+  task dump_dut_state;
     begin
       $display("State of DUT");
       $display("------------");
@@ -200,7 +194,7 @@ module tb_aes_encipher_block();
   //
   // Toggle reset to put the DUT into a well known state.
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -216,7 +210,7 @@ module tb_aes_encipher_block();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
       cycle_ctr    = 0;
       error_ctr    = 0;
@@ -238,7 +232,7 @@ module tb_aes_encipher_block();
   //
   // Display the accumulated test results.
   //----------------------------------------------------------------
-  task display_test_result();
+  task display_test_result;
     begin
       if (error_ctr == 0)
         begin
@@ -262,7 +256,7 @@ module tb_aes_encipher_block();
   // when the dut is actively processing and will in fact at some
   // point set the flag.
   //----------------------------------------------------------------
-  task wait_ready();
+  task wait_ready;
     begin
       while (!tb_ready)
         begin
diff --git a/src/tb/tb_aes_key_mem.v b/src/tb/tb_aes_key_mem.v
index 748ae3f..3e23616 100644
--- a/src/tb/tb_aes_key_mem.v
+++ b/src/tb/tb_aes_key_mem.v
@@ -37,12 +37,6 @@
 //======================================================================
 
 //------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
-
-//------------------------------------------------------------------
 // Test module.
 //------------------------------------------------------------------
 module tb_aes_key_mem();
@@ -144,7 +138,7 @@ module tb_aes_key_mem();
   //
   // Dump the state of the dump when needed.
   //----------------------------------------------------------------
-  task dump_dut_state();
+  task dump_dut_state;
     begin
       $display("State of DUT");
       $display("------------");
@@ -196,7 +190,7 @@ module tb_aes_key_mem();
   //
   // Toggle reset to put the DUT into a well known state.
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -212,7 +206,7 @@ module tb_aes_key_mem();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
       cycle_ctr = 0;
       error_ctr = 0;
@@ -237,7 +231,7 @@ module tb_aes_key_mem();
   // when the dut is actively processing and will in fact at some
   // point set the flag.
   //----------------------------------------------------------------
-  task wait_ready();
+  task wait_ready;
     begin
       while (!tb_ready)
         begin
@@ -382,7 +376,7 @@ module tb_aes_key_mem();
   //
   // Display the accumulated test results.
   //----------------------------------------------------------------
-  task display_test_result();
+  task display_test_result;
     begin
       if (error_ctr == 0)
         begin
diff --git a/toolruns/Makefile b/toolruns/Makefile
index e37b2e0..ec2b413 100755
--- a/toolruns/Makefile
+++ b/toolruns/Makefile
@@ -51,6 +51,7 @@ TB_ENCIPHER_SRC =../src/tb/tb_aes_encipher_block.v
 TB_DECIPHER_SRC =../src/tb/tb_aes_decipher_block.v
 
 CC=iverilog
+LINT=verilator
 
 
 all: top.sim core.sim keymem.sim encipher.sim decipher.sim
@@ -95,6 +96,10 @@ sim-top: top.sim
 	./top.sim
 
 
+lint:
+	verilator +1364-2001ext+ --lint-only -Wall $(TOP_SRC)
+
+
 clean:
 	rm -f decipher.sim
 	rm -f encipher.sim
@@ -109,6 +114,7 @@ help:
 	@echo "Supported targets:"
 	@echo "------------------"
 	@echo "all:          Build all simulation targets."
+	@echo "lint:         Lint all rtl source files."
 	@echo "top.sim:      Build top level simulation target."
 	@echo "core.sim:     Build core level simulation target."
 	@echo "keymem.sim:   Build key memory simulation target."