core/cipher/aes - Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard)

Branch	Commit message	Author	Age
aes_speed	Adding restriction to the API to only allow writes to controlling registers. ...	Joachim Strömbergson	6 years
api_error_fix	Synced AES repo. This commit fixes many nits such as: (1) Silence warnings on...	Joachim Strömbergson	6 years
master	Clarified the cycle times that was confusing regarding key expansion. Fixed m...	Joachim Strömbergson	5 years


Age	Commit message	Author
2017-12-06	Synced AES repo. This commit fixes many nits such as: (1) Silence warnings on...api_error_fix	Joachim Strömbergson
2016-03-10	Fixed minor nits in names of config bits.	Joachim Strömbergson
2015-10-02	Removed unnedded code blocks.	Joachim Strömbergson
2015-10-02	Removed api error port and added error bit in status register that is set whe...	Joachim Strömbergson
2015-10-02	Fixing text error in comment.	Joachim Strömbergson
2015-07-17	fix CORE_VERSION to match what we think it should be	Paul Selkirk
2015-05-28	Corrected where config bits are.	Joachim Strömbergson
2015-05-16	(1) Changed name and version to reflect that it is not only AES-128 and that ...	Joachim Strömbergson
2015-05-04	(1) Changed ordet of status and config addresses to conform to what we have i...	Joachim Strömbergson
2014-11-28	Reworked the sbox and inverse sbox. Slighly smaller design and much shorter s...	Joachim Strömbergson
[...]

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https://git.cryptech.is/core/cipher/aes