core/cipher/aes - Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard)

Branch	Commit message	Author	Age
aes_speed	Adding restriction to the API to only allow writes to controlling registers. ...	Joachim Strömbergson	6 years
api_error_fix	Synced AES repo. This commit fixes many nits such as: (1) Silence warnings on...	Joachim Strömbergson	7 years
master	Clarified the cycle times that was confusing regarding key expansion. Fixed m...	Joachim Strömbergson	5 years


Age	Commit message	Author
2019-06-09	Clarified the cycle times that was confusing regarding key expansion. Fixed m...HEAD master	Joachim Strömbergson
2019-02-08	spaces/tabs. Grrr.	Joachim Strömbergson
2019-02-08	Added missing flags for building and linting.	Joachim Strömbergson
2019-01-15	Bump the version number, because new code.	Paul Selkirk
2019-01-09	Clean-up ill-advised fork of core/cipher/aes.	Rob Austein
2018-10-23	For completeness sake added API hardening to the aes core too. The AES core h...	Joachim Strömbergson
2018-10-16	Added the regs missing in reset also in the old aes core.	Joachim Strömbergson
2018-10-03	Adding restriction to the API to only allow writes to controlling registers. ...	Joachim Strömbergson
2018-10-03	Adding testcase that tests the mangling of aes operations by switching from e...	Joachim Strömbergson
2018-10-02	Reading AES result will be zero when ready is not set.	Joachim Strömbergson
[...]

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