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authorJoachim StroĢˆmbergson <joachim@secworks.se>2018-10-03 09:15:14 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2018-10-03 09:15:14 +0200
commit833921d5f0f2c7a62594b134e6d756abd5ec012e (patch)
tree05ba16c8ffb3b76943a40486d9603e87c46b0f79
parent00f01ac229e822f1fd6577c27b0e3012983368b0 (diff)
Adding restriction to the API to only allow writes to controlling registers. This fixes CT-01-002 FPGA.
-rw-r--r--src/rtl/aes.v23
1 files changed, 13 insertions, 10 deletions
diff --git a/src/rtl/aes.v b/src/rtl/aes.v
index 48a7735..492ba56 100644
--- a/src/rtl/aes.v
+++ b/src/rtl/aes.v
@@ -225,20 +225,23 @@ module aes(
begin
if (we)
begin
- if (address == ADDR_CTRL)
+ if (core_ready)
begin
- init_new = write_data[CTRL_INIT_BIT];
- next_new = write_data[CTRL_NEXT_BIT];
- end
+ if (address == ADDR_CTRL)
+ begin
+ init_new = write_data[CTRL_INIT_BIT];
+ next_new = write_data[CTRL_NEXT_BIT];
+ end
- if (address == ADDR_CONFIG)
- config_we = 1'b1;
+ if (address == ADDR_CONFIG)
+ config_we = 1'b1;
- if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
- key_we = 1'b1;
+ if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
+ key_we = 1'b1;
- if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
- block_we = 1'b1;
+ if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
+ block_we = 1'b1;
+ end
end // if (we)
else