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-rw-r--r--src/rtl/aes.v360
1 files changed, 64 insertions, 296 deletions
diff --git a/src/rtl/aes.v b/src/rtl/aes.v
index d79fe06..57c649f 100644
--- a/src/rtl/aes.v
+++ b/src/rtl/aes.v
@@ -51,7 +51,6 @@ module aes(
output wire [31 : 0] read_data
);
-
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
@@ -66,24 +65,15 @@ module aes(
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
- localparam STATUS_ERROR_BIT = 2;
- localparam ADDR_CONFIG = 8'h0a;
- localparam CONFIG_ENCDEC_BIT = 0;
- localparam CONFIG_KEYLEN_BIT = 1;
+ localparam ADDR_CONFIG = 8'h0a;
+ localparam CTRL_ENCDEC_BIT = 0;
+ localparam CTRL_KEYLEN_BIT = 1;
localparam ADDR_KEY0 = 8'h10;
- localparam ADDR_KEY1 = 8'h11;
- localparam ADDR_KEY2 = 8'h12;
- localparam ADDR_KEY3 = 8'h13;
- localparam ADDR_KEY4 = 8'h14;
- localparam ADDR_KEY5 = 8'h15;
- localparam ADDR_KEY6 = 8'h16;
localparam ADDR_KEY7 = 8'h17;
localparam ADDR_BLOCK0 = 8'h20;
- localparam ADDR_BLOCK1 = 8'h21;
- localparam ADDR_BLOCK2 = 8'h22;
localparam ADDR_BLOCK3 = 8'h23;
localparam ADDR_RESULT0 = 8'h30;
@@ -93,7 +83,7 @@ module aes(
localparam CORE_NAME0 = 32'h61657320; // "aes "
localparam CORE_NAME1 = 32'h20202020; // " "
- localparam CORE_VERSION = 32'h302e3831; // "0.81"
+ localparam CORE_VERSION = 32'h302e3630; // "0.60"
//----------------------------------------------------------------
@@ -101,47 +91,19 @@ module aes(
//----------------------------------------------------------------
reg init_reg;
reg init_new;
- reg init_we;
- reg init_set;
reg next_reg;
reg next_new;
- reg next_we;
- reg next_set;
-
- reg error_reg;
- reg error_new;
- reg error_we;
reg encdec_reg;
reg keylen_reg;
reg config_we;
- reg [31 : 0] block0_reg;
- reg block0_we;
- reg [31 : 0] block1_reg;
- reg block1_we;
- reg [31 : 0] block2_reg;
- reg block2_we;
- reg [31 : 0] block3_reg;
- reg block3_we;
-
- reg [31 : 0] key0_reg;
- reg key0_we;
- reg [31 : 0] key1_reg;
- reg key1_we;
- reg [31 : 0] key2_reg;
- reg key2_we;
- reg [31 : 0] key3_reg;
- reg key3_we;
- reg [31 : 0] key4_reg;
- reg key4_we;
- reg [31 : 0] key5_reg;
- reg key5_we;
- reg [31 : 0] key6_reg;
- reg key6_we;
- reg [31 : 0] key7_reg;
- reg key7_we;
+ reg [31 : 0] block_reg [0 : 3];
+ reg block_we;
+
+ reg [31 : 0] key_reg [0 : 7];
+ reg key_we;
reg [127 : 0] result_reg;
reg valid_reg;
@@ -169,10 +131,11 @@ module aes(
//----------------------------------------------------------------
assign read_data = tmp_read_data;
- assign core_key = {key0_reg, key1_reg, key2_reg, key3_reg,
- key4_reg, key5_reg, key6_reg, key7_reg};
+ assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
+ key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
- assign core_block = {block0_reg, block1_reg, block2_reg, block3_reg};
+ assign core_block = {block_reg[0], block_reg[1],
+ block_reg[2], block_reg[3]};
assign core_init = init_reg;
assign core_next = next_reg;
assign core_encdec = encdec_reg;
@@ -207,48 +170,33 @@ module aes(
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
- begin
+ begin : reg_update
+ integer i;
+
if (!reset_n)
begin
- block0_reg <= 32'h00000000;
- block1_reg <= 32'h00000000;
- block2_reg <= 32'h00000000;
- block3_reg <= 32'h00000000;
-
- key0_reg <= 32'h00000000;
- key1_reg <= 32'h00000000;
- key2_reg <= 32'h00000000;
- key3_reg <= 32'h00000000;
- key4_reg <= 32'h00000000;
- key5_reg <= 32'h00000000;
- key6_reg <= 32'h00000000;
- key7_reg <= 32'h00000000;
-
- init_reg <= 0;
- next_reg <= 0;
- encdec_reg <= 0;
- keylen_reg <= 0;
-
- error_reg <= 0;
-
- result_reg <= 128'h00000000000000000000000000000000;
- valid_reg <= 0;
- ready_reg <= 0;
- end
- else
- begin
- ready_reg <= core_ready;
- valid_reg <= core_valid;
- result_reg <= core_result;
+ for (i = 0 ; i < 4 ; i = i + 1)
+ block_reg[i] <= 32'h0;
- if (error_we)
- error_reg <= error_new;
+ for (i = 0 ; i < 8 ; i = i + 1)
+ key_reg[i] <= 32'h0;
- if (init_we)
- init_reg <= init_new;
+ init_reg <= 1'b0;
+ next_reg <= 1'b0;
+ encdec_reg <= 1'b0;
+ keylen_reg <= 1'b0;
- if (next_we)
- next_reg <= next_new;
+ result_reg <= 128'h0;
+ valid_reg <= 1'b0;
+ ready_reg <= 1'b0;
+ end
+ else
+ begin
+ ready_reg <= core_ready;
+ valid_reg <= core_valid;
+ result_reg <= core_result;
+ init_reg <= init_new;
+ next_reg <= next_new;
if (config_we)
begin
@@ -256,245 +204,65 @@ module aes(
keylen_reg <= write_data[CTRL_KEYLEN_BIT];
end
- if (key0_we)
- key0_reg <= write_data;
-
- if (key1_we)
- key1_reg <= write_data;
-
- if (key2_we)
- key2_reg <= write_data;
-
- if (key3_we)
- key3_reg <= write_data;
-
- if (key4_we)
- key4_reg <= write_data;
-
- if (key5_we)
- key5_reg <= write_data;
-
- if (key6_we)
- key6_reg <= write_data;
-
- if (key7_we)
- key7_reg <= write_data;
-
- if (block0_we)
- block0_reg <= write_data;
-
- if (block1_we)
- block1_reg <= write_data;
-
- if (block2_we)
- block2_reg <= write_data;
+ if (key_we)
+ key_reg[address[2 : 0]] <= write_data;
- if (block3_we)
- block3_reg <= write_data;
+ if (block_we)
+ block_reg[address[1 : 0]] <= write_data;
end
end // reg_update
//----------------------------------------------------------------
- // flag_ctrl
- //
- // Logic to set and automatically reset init- and next
- // flags that has been set.
- //----------------------------------------------------------------
- always @*
- begin : flag_reset
- init_new = 0;
- init_we = 0;
- next_new = 0;
- next_we = 0;
-
- if (init_set)
- begin
- init_new = 1;
- init_we = 1;
- end
- else if (init_reg)
- begin
- init_new = 0;
- init_we = 1;
- end
-
- if (next_set)
- begin
- next_new = 1;
- next_we = 1;
- end
- else if (next_reg)
- begin
- next_new = 0;
- next_we = 1;
- end
- end
-
-
- //----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
- init_set = 0;
- next_set = 0;
- config_we = 0;
- error_new = 0;
- error_we = 0;
- key0_we = 0;
- key1_we = 0;
- key2_we = 0;
- key3_we = 0;
- key4_we = 0;
- key5_we = 0;
- key6_we = 0;
- key7_we = 0;
- block0_we = 0;
- block1_we = 0;
- block2_we = 0;
- block3_we = 0;
- tmp_read_data = 32'h00000000;
+ init_new = 1'b0;
+ next_new = 1'b0;
+ config_we = 1'b0;
+ key_we = 1'b0;
+ block_we = 1'b0;
+ tmp_read_data = 32'h0;
if (cs)
begin
if (we)
begin
- case (address)
- ADDR_CTRL:
- begin
- init_set = write_data[CTRL_INIT_BIT];
- next_set = write_data[CTRL_NEXT_BIT];
- end
+ if (address == ADDR_CTRL)
+ begin
+ init_new = write_data[CTRL_INIT_BIT];
+ next_new = write_data[CTRL_NEXT_BIT];
+ end
- ADDR_STATUS:
- begin
- error_new = 0;
- error_we = 1;
- end
-
- ADDR_CONFIG:
- config_we = 1;
-
- ADDR_KEY0:
- key0_we = 1;
-
- ADDR_KEY1:
- key1_we = 1;
-
- ADDR_KEY2:
- key2_we = 1;
-
- ADDR_KEY3:
- key3_we = 1;
-
- ADDR_KEY4:
- key4_we = 1;
-
- ADDR_KEY5:
- key5_we = 1;
-
- ADDR_KEY6:
- key6_we = 1;
+ if (address == ADDR_CONFIG)
+ config_we = 1'b1;
- ADDR_KEY7:
- key7_we = 1;
+ if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
+ key_we = 1'b1;
- ADDR_BLOCK0:
- block0_we = 1;
-
- ADDR_BLOCK1:
- block1_we = 1;
-
- ADDR_BLOCK2:
- block2_we = 1;
-
- ADDR_BLOCK3:
- block3_we = 1;
-
- default:
- begin
- error_new = 1;
- error_we = 1;
- end
- endcase // case (address)
+ if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
+ block_we = 1'b1;
end // if (we)
else
begin
case (address)
- ADDR_NAME0:
- tmp_read_data = CORE_NAME0;
-
- ADDR_NAME1:
- tmp_read_data = CORE_NAME1;
-
- ADDR_VERSION:
- tmp_read_data = CORE_VERSION;
-
- ADDR_CTRL:
- tmp_read_data = {28'h0000000, keylen_reg, encdec_reg,
- next_reg, init_reg};
-
- ADDR_STATUS:
- tmp_read_data = {29'h00000000, error_reg, valid_reg, ready_reg};
-
- ADDR_KEY0:
- tmp_read_data = key0_reg;
-
- ADDR_KEY1:
- tmp_read_data = key1_reg;
-
- ADDR_KEY2:
- tmp_read_data = key2_reg;
-
- ADDR_KEY3:
- tmp_read_data = key3_reg;
-
- ADDR_KEY4:
- tmp_read_data = key4_reg;
-
- ADDR_KEY5:
- tmp_read_data = key5_reg;
-
- ADDR_KEY6:
- tmp_read_data = key6_reg;
-
- ADDR_KEY7:
- tmp_read_data = key7_reg;
-
- ADDR_BLOCK0:
- tmp_read_data = block0_reg;
-
- ADDR_BLOCK1:
- tmp_read_data = block1_reg;
-
- ADDR_BLOCK2:
- tmp_read_data = block2_reg;
-
- ADDR_BLOCK3:
- tmp_read_data = block3_reg;
-
- ADDR_RESULT0:
- tmp_read_data = result_reg[127 : 96];
-
- ADDR_RESULT1:
- tmp_read_data = result_reg[95 : 64];
-
- ADDR_RESULT2:
- tmp_read_data = result_reg[63 : 32];
-
- ADDR_RESULT3:
- tmp_read_data = result_reg[31 : 0];
+ ADDR_NAME0: tmp_read_data = CORE_NAME0;
+ ADDR_NAME1: tmp_read_data = CORE_NAME1;
+ ADDR_VERSION: tmp_read_data = CORE_VERSION;
+ ADDR_CTRL: tmp_read_data = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg};
+ ADDR_STATUS: tmp_read_data = {30'h0, valid_reg, ready_reg};
default:
begin
- error_new = 1;
- error_we = 1;
end
endcase // case (address)
+
+ if ((address >= ADDR_RESULT0) && (address <= ADDR_RESULT3))
+ tmp_read_data = result_reg[(3 - (address - ADDR_RESULT0)) * 32 +: 32];
end
end
end // addr_decoder
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