| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-12-19 | Use primitives from core/libHEADmaster | Pavel V. Shatov (Meister) | |
| 2017-07-04 | Fixed generic/vendor low-level primitives switch. | Pavel V. Shatov (Meister) | |
| 2017-07-01 | Cleaned up Verilog sources | Pavel V. Shatov (Meister) | |
| 2017-07-01 | Added 512-bit test vector | Pavel V. Shatov (Meister) | |
| Cleaned up Verilog a bit | |||
| 2017-07-01 | Finished modulus-dependent coefficient calculation module: | Pavel V. Shatov (Meister) | |
| * fixed bug with latency compensation * cleaned up Verilog source * added 512-bit testbench * works in simulator * synthesizes without warnings Changes: * made latency of generic processing element configurable | |||
| 2017-06-27 | Added Montgomery modulus-dependent coefficient calculation block | Pavel V. Shatov (Meister) | |
| * work in progress | |||
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index : core/math/modexpa7 | |
| Modular exponentiation using the Artix-7 FPGA | git repositories |
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