Cleaned up Verilog sources

1 files changed, 2 insertions, 1 deletions

diff --git a/src/rtl/modexpa7_n_coeff.v b/src/rtl/modexpa7_n_coeff.v
index 2bed5cd..d416898 100644
--- a/src/rtl/modexpa7_n_coeff.v
+++ b/src/rtl/modexpa7_n_coeff.v
@@ -153,6 +153,7 @@ module modexpa7_n_coeff #
 		 * further investigation...

 		 *

 		 */

+		 

 	reg	[OPERAND_ADDR_WIDTH+4:0]	cyc_cnt;

 		

 	wire	[OPERAND_ADDR_WIDTH+4:0]	cyc_cnt_zero = {{OPERAND_ADDR_WIDTH{1'b0}}, {5{1'b0}}};

@@ -271,7 +272,7 @@ module modexpa7_n_coeff #
 	wire	rb_addr_done			= (rb_addr      == bram_addr_last) ? 1'b1 : 1'b0;

 	wire	n_coeff_addr_done		= (n_coeff_addr == bram_addr_last) ? 1'b1 : 1'b0;

 	

-		/* map top-level ports to internal register */

+		/* map top-level ports to internal registers */

 	assign n_bram_addr			= n_addr;

 	assign n_coeff_bram_addr	= n_coeff_addr;

 	assign n_coeff_bram_in		= n_coeff_data_in;