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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2017-07-04 16:33:04 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2017-07-04 16:33:04 +0300
commit0da71205b28d07cc832732b28e8893c46fbf6cad (patch)
tree3c579d8e21da677168d9b221ba7ce6bc9a605432 /src/rtl/modexpa7_n_coeff.v
parentb3f9191bc6c42a8c3cef6b14a9db444af56df5e8 (diff)
Fixed generic/vendor low-level primitives switch.
Diffstat (limited to 'src/rtl/modexpa7_n_coeff.v')
-rw-r--r--src/rtl/modexpa7_n_coeff.v8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/rtl/modexpa7_n_coeff.v b/src/rtl/modexpa7_n_coeff.v
index d416898..c2d7c9d 100644
--- a/src/rtl/modexpa7_n_coeff.v
+++ b/src/rtl/modexpa7_n_coeff.v
@@ -315,10 +315,10 @@ module modexpa7_n_coeff #
/* delay carry masking flag by one clock cycle (used later) */
always @(posedge clk) add1_c_in_mask_dly <= add1_c_in_mask;
- modexpa7_pe_add add1_inst
+ modexpa7_adder32 add1_inst
(
.clk (clk), //
- .ce (1'b1),
+ .ce (1'b1), //
.a (~n_bram_out), // ~N
.b ({{31{1'b0}}, add1_b_lsb}), // 1
.c_in (add1_c_in), //
@@ -339,7 +339,7 @@ module modexpa7_n_coeff #
reg add2_c_in; // carry input
wire add2_c_out; // carry output
- modexpa7_pe_add add2_inst
+ modexpa7_adder32 add2_inst
(
.clk (clk),
.ce (1'b1),
@@ -367,7 +367,7 @@ module modexpa7_n_coeff #
wire [31: 0] pe_p;
wire [31: 0] pe_c_out;
- modexpa7_pe_mul pe_mul_inst
+ modexpa7_systolic_pe pe_mul_inst
(
.clk (clk),
.a (pe_a),