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| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-07-01 18:47:05 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-07-01 18:47:05 +0300 |
| commit | a69a5308958c667e61cd90de51f64f9f4e0fcead (patch) | |
| tree | 2a7d884296c04b61cd6ad357488dce4e818a5510 /src/rtl/modexpa7_n_coeff.v | |
| parent | 1fd8037d41be46d24b3610c89f781fe85def4317 (diff) | |
Added 512-bit test vector
Cleaned up Verilog a bit
Diffstat (limited to 'src/rtl/modexpa7_n_coeff.v')
| -rw-r--r-- | src/rtl/modexpa7_n_coeff.v | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/rtl/modexpa7_n_coeff.v b/src/rtl/modexpa7_n_coeff.v index cba59e2..2bed5cd 100644 --- a/src/rtl/modexpa7_n_coeff.v +++ b/src/rtl/modexpa7_n_coeff.v @@ -145,6 +145,14 @@ module modexpa7_n_coeff # //
// Cycle Counters
//
+
+ /*
+ * Maybe we can cheat and skip calculation of entire T every time.
+ * During the first 32 cycles we only need the first word of T,
+ * during the following 64 cycles the secord word, etc. Needs
+ * further investigation...
+ *
+ */
reg [OPERAND_ADDR_WIDTH+4:0] cyc_cnt;
wire [OPERAND_ADDR_WIDTH+4:0] cyc_cnt_zero = {{OPERAND_ADDR_WIDTH{1'b0}}, {5{1'b0}}};
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