diff options
Diffstat (limited to 'src/rtl/modexpa7_n_coeff.v')
| -rw-r--r-- | src/rtl/modexpa7_n_coeff.v | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/src/rtl/modexpa7_n_coeff.v b/src/rtl/modexpa7_n_coeff.v index c2d7c9d..1ddb282 100644 --- a/src/rtl/modexpa7_n_coeff.v +++ b/src/rtl/modexpa7_n_coeff.v @@ -63,7 +63,13 @@ module modexpa7_n_coeff # input [OPERAND_ADDR_WIDTH-1:0] n_num_words // number of words in modulus
);
-
+
+ // + // Settings + // + `include "cryptech_primitive_switch.vh"
+
+
//
// FSM Declaration
//
@@ -315,10 +321,9 @@ module modexpa7_n_coeff # /* delay carry masking flag by one clock cycle (used later) */
always @(posedge clk) add1_c_in_mask_dly <= add1_c_in_mask;
- modexpa7_adder32 add1_inst
+ `CRYPTECH_PRIMITIVE_ADD32 add1_inst
(
.clk (clk), //
- .ce (1'b1), //
.a (~n_bram_out), // ~N
.b ({{31{1'b0}}, add1_b_lsb}), // 1
.c_in (add1_c_in), //
@@ -339,10 +344,9 @@ module modexpa7_n_coeff # reg add2_c_in; // carry input
wire add2_c_out; // carry output
- modexpa7_adder32 add2_inst
+ `CRYPTECH_PRIMITIVE_ADD32 add2_inst
(
.clk (clk),
- .ce (1'b1),
.a (r_data_out),
.b (b_data_in),
.c_in (add2_c_in),
@@ -367,7 +371,7 @@ module modexpa7_n_coeff # wire [31: 0] pe_p;
wire [31: 0] pe_c_out;
- modexpa7_systolic_pe pe_mul_inst
+ `CRYPTECH_PRIMITIVE_MODEXP_SYSTOLIC_PE pe_mul_inst
(
.clk (clk),
.a (pe_a),
|