Age | Commit message (Collapse) | Author |
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This update changes the ADDR_CTRL API register since it adds a mode bit. The version major number has been bumped to reflect this API change. The top level testbench contains tests for SHA224 as well as old tests for SHA256. The core level tb still only tests SHA256.
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case to really test the core. Added data valid task.
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superflous. Captain slow.
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write interface to a common data port.
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state. The state addresses are still readable though.
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from the API. (2) Bumped version to reflect the changes to the API. (3) Added ports for state access in the core module and connected them in the top level wrapper.
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with 1000 blocks.
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with huge message. Disabling verbose mode.
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flags. Fixing clock parameter naming.
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tasks. Now simumaltion with ModelSim works.
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implementation results.
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integration in the core.
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memory like interface.
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