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AgeCommit message (Expand)Author
2020-05-12Adding the functionality to extractd and set the intrnal hash state. Note: Th...HEADmasterJoachim Strömbergson
2020-05-12Minor change. variable names are easier to read.Joachim Strömbergson
2018-10-16Added width definition to reset values as part of checking that all registers...Joachim Strömbergson
2018-10-03Restricted write access for control bits to when the core is ready.Joachim Strömbergson
2018-04-27Removed obsolete defines.Joachim Strömbergson
2018-04-27Removed redundant FSM from the W memory.Joachim Strömbergson
2017-12-15Removing stale wires.Joachim Strömbergson
2017-12-08Syncecd SHA-1 core to github repo. No functional changes, but more compact co...Joachim Strömbergson
2015-12-13whack copyrightsPaul Selkirk
2015-03-31Revert streamlined wrapper, and don't delay register reads.Paul Selkirk
2015-03-17Rearrange cores.Paul Selkirk
2014-12-05There is an END to this, according to Paul.Joachim Strömbergson
2014-12-05Adding a separate digiest update state.Joachim Strömbergson
2014-11-07Changed to asynch reset.Joachim Strömbergson
2014-11-06(1) Minor fixes of nits found by the verilator linter. (2) Removed trailing w...Joachim Strömbergson
2014-03-17Removed redundant flag reset wires.Joachim Strömbergson
2014-03-14Updating interface. Addding self resetting control regs. Fixing missing input...Joachim Strömbergson
2014-02-23Updated W memory module with new sliding window version. Updated README with ...Joachim Strömbergson
2014-02-21Adding all rtl source files for the sha-1 core.Joachim Strömbergson