Syncecd SHA-1 core to github repo. No functional changes, but more compact code and a lot of minor fixes to silence warnings.

3 files changed, 130 insertions, 560 deletions

diff --git a/src/rtl/sha1.v b/src/rtl/sha1.v
index 835cadf..40d13bc 100644
--- a/src/rtl/sha1.v
+++ b/src/rtl/sha1.v
@@ -57,44 +57,27 @@ module sha1(
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
-  parameter ADDR_NAME0       = 8'h00;
-  parameter ADDR_NAME1       = 8'h01;
-  parameter ADDR_VERSION     = 8'h02;
-
-  parameter ADDR_CTRL        = 8'h08;
-  parameter CTRL_INIT_BIT    = 0;
-  parameter CTRL_NEXT_BIT    = 1;
-
-  parameter ADDR_STATUS      = 8'h09;
-  parameter STATUS_READY_BIT = 0;
-  parameter STATUS_VALID_BIT = 1;
-
-  parameter ADDR_BLOCK0    = 8'h10;
-  parameter ADDR_BLOCK1    = 8'h11;
-  parameter ADDR_BLOCK2    = 8'h12;
-  parameter ADDR_BLOCK3    = 8'h13;
-  parameter ADDR_BLOCK4    = 8'h14;
-  parameter ADDR_BLOCK5    = 8'h15;
-  parameter ADDR_BLOCK6    = 8'h16;
-  parameter ADDR_BLOCK7    = 8'h17;
-  parameter ADDR_BLOCK8    = 8'h18;
-  parameter ADDR_BLOCK9    = 8'h19;
-  parameter ADDR_BLOCK10   = 8'h1a;
-  parameter ADDR_BLOCK11   = 8'h1b;
-  parameter ADDR_BLOCK12   = 8'h1c;
-  parameter ADDR_BLOCK13   = 8'h1d;
-  parameter ADDR_BLOCK14   = 8'h1e;
-  parameter ADDR_BLOCK15   = 8'h1f;
-
-  parameter ADDR_DIGEST0   = 8'h20;
-  parameter ADDR_DIGEST1   = 8'h21;
-  parameter ADDR_DIGEST2   = 8'h22;
-  parameter ADDR_DIGEST3   = 8'h23;
-  parameter ADDR_DIGEST4   = 8'h24;
-
-  parameter CORE_NAME0     = 32'h73686131; // "sha1"
-  parameter CORE_NAME1     = 32'h20202020; // "    "
-  parameter CORE_VERSION   = 32'h302e3530; // "0.50"
+  localparam ADDR_NAME0       = 8'h00;
+  localparam ADDR_NAME1       = 8'h01;
+  localparam ADDR_VERSION     = 8'h02;
+
+  localparam ADDR_CTRL        = 8'h08;
+  localparam CTRL_INIT_BIT    = 0;
+  localparam CTRL_NEXT_BIT    = 1;
+
+  localparam ADDR_STATUS      = 8'h09;
+  localparam STATUS_READY_BIT = 0;
+  localparam STATUS_VALID_BIT = 1;
+
+  localparam ADDR_BLOCK0    = 8'h10;
+  localparam ADDR_BLOCK15   = 8'h1f;
+
+  localparam ADDR_DIGEST0   = 8'h20;
+  localparam ADDR_DIGEST4   = 8'h24;
+
+  localparam CORE_NAME0     = 32'h73686131; // "sha1"
+  localparam CORE_NAME1     = 32'h20202020; // "    "
+  localparam CORE_VERSION   = 32'h302e3630; // "0.60"
 
 
   //----------------------------------------------------------------
@@ -102,48 +85,14 @@ module sha1(
   //----------------------------------------------------------------
   reg init_reg;
   reg init_new;
-  reg init_we;
-  reg init_set;
 
   reg next_reg;
   reg next_new;
-  reg next_we;
-  reg next_set;
 
   reg ready_reg;
 
-  reg [31 : 0] block0_reg;
-  reg          block0_we;
-  reg [31 : 0] block1_reg;
-  reg          block1_we;
-  reg [31 : 0] block2_reg;
-  reg          block2_we;
-  reg [31 : 0] block3_reg;
-  reg          block3_we;
-  reg [31 : 0] block4_reg;
-  reg          block4_we;
-  reg [31 : 0] block5_reg;
-  reg          block5_we;
-  reg [31 : 0] block6_reg;
-  reg          block6_we;
-  reg [31 : 0] block7_reg;
-  reg          block7_we;
-  reg [31 : 0] block8_reg;
-  reg          block8_we;
-  reg [31 : 0] block9_reg;
-  reg          block9_we;
-  reg [31 : 0] block10_reg;
-  reg          block10_we;
-  reg [31 : 0] block11_reg;
-  reg          block11_we;
-  reg [31 : 0] block12_reg;
-  reg          block12_we;
-  reg [31 : 0] block13_reg;
-  reg          block13_we;
-  reg [31 : 0] block14_reg;
-  reg          block14_we;
-  reg [31 : 0] block15_reg;
-  reg          block15_we;
+  reg [31 : 0] block_reg [0 : 15];
+  reg          block_we;
 
   reg [159 : 0] digest_reg;
 
@@ -167,36 +116,32 @@ module sha1(
   //----------------------------------------------------------------
   // Concurrent connectivity for ports etc.
   //----------------------------------------------------------------
-  assign core_init = init_reg;
-
-  assign core_next = next_reg;
-
-  assign core_block = {block0_reg, block1_reg, block2_reg, block3_reg,
-                       block4_reg, block5_reg, block6_reg, block7_reg,
-                       block8_reg, block9_reg, block10_reg, block11_reg,
-                       block12_reg, block13_reg, block14_reg, block15_reg};
+  assign core_block = {block_reg[00], block_reg[01], block_reg[02], block_reg[03],
+                       block_reg[04], block_reg[05], block_reg[06], block_reg[07],
+                       block_reg[08], block_reg[09], block_reg[10], block_reg[11],
+                       block_reg[12], block_reg[13], block_reg[14], block_reg[15]};
 
   assign read_data = tmp_read_data;
-  assign error    = tmp_error;
+  assign error     = tmp_error;
 
 
   //----------------------------------------------------------------
   // core instantiation.
   //----------------------------------------------------------------
   sha1_core core(
-                   .clk(clk),
-                   .reset_n(reset_n),
+                 .clk(clk),
+                 .reset_n(reset_n),
 
-                   .init(core_init),
-                   .next(core_next),
+                 .init(init_reg),
+                 .next(next_reg),
 
-                   .block(core_block),
+                 .block(core_block),
 
-                   .ready(core_ready),
+                 .ready(core_ready),
 
-                   .digest(core_digest),
-                   .digest_valid(core_digest_valid)
-                  );
+                 .digest(core_digest),
+                 .digest_valid(core_digest_valid)
+                );
 
 
   //----------------------------------------------------------------
@@ -206,171 +151,35 @@ module sha1(
   // asynchronous active low reset.
   //----------------------------------------------------------------
   always @ (posedge clk or negedge reset_n)
-    begin
+    begin : reg_update
+      integer i;
+
       if (!reset_n)
         begin
           init_reg         <= 0;
           next_reg         <= 0;
           ready_reg        <= 0;
-          digest_reg       <= 160'h0000000000000000000000000000000000000000;
+          digest_reg       <= 160'h0;
           digest_valid_reg <= 0;
-          block0_reg       <= 32'h00000000;
-          block1_reg       <= 32'h00000000;
-          block2_reg       <= 32'h00000000;
-          block3_reg       <= 32'h00000000;
-          block4_reg       <= 32'h00000000;
-          block5_reg       <= 32'h00000000;
-          block6_reg       <= 32'h00000000;
-          block7_reg       <= 32'h00000000;
-          block8_reg       <= 32'h00000000;
-          block9_reg       <= 32'h00000000;
-          block10_reg      <= 32'h00000000;
-          block11_reg      <= 32'h00000000;
-          block12_reg      <= 32'h00000000;
-          block13_reg      <= 32'h00000000;
-          block14_reg      <= 32'h00000000;
-          block15_reg      <= 32'h00000000;
+
+          for (i = 0 ; i < 16 ; i = i + 1)
+            block_reg[i] <= 32'h0;
         end
       else
         begin
           ready_reg        <= core_ready;
           digest_valid_reg <= core_digest_valid;
+          init_reg         <= init_new;
+          next_reg         <= next_new;
 
-          if (init_we)
-            begin
-              init_reg <= init_new;
-            end
-
-          if (next_we)
-            begin
-              next_reg <= next_new;
-            end
+          if (block_we)
+            block_reg[address[3 : 0]] <= write_data;
 
           if (core_digest_valid)
-            begin
-              digest_reg <= core_digest;
-            end
-
-          if (block0_we)
-            begin
-              block0_reg <= write_data;
-            end
-
-          if (block1_we)
-            begin
-              block1_reg <= write_data;
-            end
-
-          if (block2_we)
-            begin
-              block2_reg <= write_data;
-            end
-
-          if (block3_we)
-            begin
-              block3_reg <= write_data;
-            end
-
-          if (block4_we)
-            begin
-              block4_reg <= write_data;
-            end
-
-          if (block5_we)
-            begin
-              block5_reg <= write_data;
-            end
-
-          if (block6_we)
-            begin
-              block6_reg <= write_data;
-            end
-
-          if (block7_we)
-            begin
-              block7_reg <= write_data;
-            end
-
-          if (block8_we)
-            begin
-              block8_reg <= write_data;
-            end
-
-          if (block9_we)
-            begin
-              block9_reg <= write_data;
-            end
-
-          if (block10_we)
-            begin
-              block10_reg <= write_data;
-            end
-
-          if (block11_we)
-            begin
-              block11_reg <= write_data;
-            end
-
-          if (block12_we)
-            begin
-              block12_reg <= write_data;
-            end
-
-          if (block13_we)
-            begin
-              block13_reg <= write_data;
-            end
-
-          if (block14_we)
-            begin
-              block14_reg <= write_data;
-            end
-
-          if (block15_we)
-            begin
-              block15_reg <= write_data;
-            end
-
+            digest_reg <= core_digest;
         end
     end // reg_update
 
-
-  //----------------------------------------------------------------
-  // flag_reset
-  //
-  // Logic to reset init and next flags that has been set.
-  //----------------------------------------------------------------
-  always @*
-    begin : flag_reset
-      init_new = 0;
-      init_we  = 0;
-      next_new = 0;
-      next_we  = 0;
-
-      if (init_set)
-        begin
-          init_new = 1;
-          init_we  = 1;
-        end
-      else if (init_reg)
-        begin
-          init_new = 0;
-          init_we  = 1;
-        end
-
-      if (next_set)
-        begin
-          next_new = 1;
-          next_we  = 1;
-        end
-      else if (next_reg)
-        begin
-          next_new = 0;
-          next_we  = 1;
-        end
-    end
-
-
   //----------------------------------------------------------------
   // api
   //
@@ -378,259 +187,49 @@ module sha1(
   //----------------------------------------------------------------
   always @*
     begin : api
-      init_set      = 0;
-      next_set      = 0;
-      block0_we     = 0;
-      block1_we     = 0;
-      block2_we     = 0;
-      block3_we     = 0;
-      block4_we     = 0;
-      block5_we     = 0;
-      block6_we     = 0;
-      block7_we     = 0;
-      block8_we     = 0;
-      block9_we     = 0;
-      block10_we    = 0;
-      block11_we    = 0;
-      block12_we    = 0;
-      block13_we    = 0;
-      block14_we    = 0;
-      block15_we    = 0;
-      tmp_read_data = 32'h00000000;
+      init_new      = 0;
+      next_new      = 0;
+      block_we      = 0;
+      tmp_read_data = 32'h0;
       tmp_error     = 0;
 
       if (cs)
         begin
           if (we)
             begin
-              case (address)
-                // Write operations.
-                ADDR_CTRL:
-                  begin
-                    init_set = write_data[CTRL_INIT_BIT];
-                    next_set = write_data[CTRL_NEXT_BIT];
-                  end
-
-                ADDR_BLOCK0:
-                  begin
-                    block0_we = 1;
-                   end
-
-                ADDR_BLOCK1:
-                  begin
-                    block1_we = 1;
-                  end
-
-                ADDR_BLOCK2:
-                  begin
-                    block2_we = 1;
-                  end
-
-                ADDR_BLOCK3:
-                  begin
-                    block3_we = 1;
-                  end
-
-                ADDR_BLOCK4:
-                  begin
-                    block4_we = 1;
-                  end
-
-                ADDR_BLOCK5:
-                  begin
-                    block5_we = 1;
-                  end
-
-                ADDR_BLOCK6:
-                  begin
-                    block6_we = 1;
-                  end
-
-                ADDR_BLOCK7:
-                  begin
-                    block7_we = 1;
-                  end
-
-                ADDR_BLOCK8:
-                  begin
-                    block8_we = 1;
-                  end
-
-                ADDR_BLOCK9:
-                  begin
-                    block9_we = 1;
-                  end
-
-                ADDR_BLOCK10:
-                  begin
-                    block10_we = 1;
-                  end
-
-                ADDR_BLOCK11:
-                  begin
-                    block11_we = 1;
-                  end
+              if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15))
+                block_we = 1;
 
-                ADDR_BLOCK12:
-                  begin
-                    block12_we = 1;
-                  end
-
-                ADDR_BLOCK13:
-                  begin
-                    block13_we = 1;
-                  end
-
-                ADDR_BLOCK14:
-                  begin
-                    block14_we = 1;
-                  end
-
-                ADDR_BLOCK15:
-                  begin
-                    block15_we = 1;
-                  end
-
-                default:
-                  begin
-                    tmp_error = 1;
-                  end
-              endcase // case (addr)
+              if (address == ADDR_CTRL)
+                begin
+                  init_new = write_data[CTRL_INIT_BIT];
+                  next_new = write_data[CTRL_NEXT_BIT];
+                end
             end // if (write_read)
-
           else
             begin
+              if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15))
+                tmp_read_data = block_reg[address[3 : 0]];
+
+              if ((address >= ADDR_DIGEST0) && (address <= ADDR_DIGEST4))
+                tmp_read_data = digest_reg[(4 - (address - ADDR_DIGEST0)) * 32 +: 32];
+
               case (address)
                 // Read operations.
                 ADDR_NAME0:
-                  begin
-                    tmp_read_data = CORE_NAME0;
-                  end
+                  tmp_read_data = CORE_NAME0;
 
                 ADDR_NAME1:
-                  begin
-                    tmp_read_data = CORE_NAME1;
-                  end
+                  tmp_read_data = CORE_NAME1;
 
                 ADDR_VERSION:
-                  begin
-                    tmp_read_data = CORE_VERSION;
-                  end
+                  tmp_read_data = CORE_VERSION;
 
                 ADDR_CTRL:
-                  begin
-                    tmp_read_data = {28'h0000000, 2'b00, next_reg, init_reg};
-                  end
+                  tmp_read_data = {30'h0, next_reg, init_reg};
 
                 ADDR_STATUS:
-                  begin
-                    tmp_read_data = {28'h0000000, 2'b00, digest_valid_reg, ready_reg};
-                  end
-
-                ADDR_BLOCK0:
-                  begin
-                    tmp_read_data = block0_reg;
-                  end
-
-                ADDR_BLOCK1:
-                  begin
-                    tmp_read_data = block1_reg;
-                  end
-
-                ADDR_BLOCK2:
-                  begin
-                    tmp_read_data = block2_reg;
-                  end
-
-                ADDR_BLOCK3:
-                  begin
-                    tmp_read_data = block3_reg;
-                  end
-
-                ADDR_BLOCK4:
-                  begin
-                    tmp_read_data = block4_reg;
-                  end
-
-                ADDR_BLOCK5:
-                  begin
-                    tmp_read_data = block5_reg;
-                  end
-
-                ADDR_BLOCK6:
-                  begin
-                    tmp_read_data = block6_reg;
-                  end
-
-                ADDR_BLOCK7:
-                  begin
-                    tmp_read_data = block7_reg;
-                  end
-
-                ADDR_BLOCK8:
-                  begin
-                    tmp_read_data = block8_reg;
-                  end
-
-                ADDR_BLOCK9:
-                  begin
-                    tmp_read_data = block9_reg;
-                  end
-
-                ADDR_BLOCK10:
-                  begin
-                    tmp_read_data = block10_reg;
-                  end
-
-                ADDR_BLOCK11:
-                  begin
-                    tmp_read_data = block11_reg;
-                  end
-
-                ADDR_BLOCK12:
-                  begin
-                    tmp_read_data = block12_reg;
-                  end
-
-                ADDR_BLOCK13:
-                  begin
-                    tmp_read_data = block13_reg;
-                  end
-
-                ADDR_BLOCK14:
-                  begin
-                    tmp_read_data = block14_reg;
-                  end
-
-                ADDR_BLOCK15:
-                  begin
-                    tmp_read_data = block15_reg;
-                  end
-
-                ADDR_DIGEST0:
-                  begin
-                    tmp_read_data = digest_reg[159 : 128];
-                  end
-
-                ADDR_DIGEST1:
-                  begin
-                    tmp_read_data = digest_reg[127 :  96];
-                  end
-
-                ADDR_DIGEST2:
-                  begin
-                    tmp_read_data = digest_reg[95  :  64];
-                  end
-
-                ADDR_DIGEST3:
-                  begin
-                    tmp_read_data = digest_reg[63  :  32];
-                  end
-
-                ADDR_DIGEST4:
-                  begin
-                    tmp_read_data = digest_reg[31  :   0];
-                  end
+                  tmp_read_data = {30'h0, digest_valid_reg, ready_reg};
 
                 default:
                   begin
diff --git a/src/rtl/sha1_core.v b/src/rtl/sha1_core.v
index beb0cbd..e38da3b 100644
--- a/src/rtl/sha1_core.v
+++ b/src/rtl/sha1_core.v
@@ -67,8 +67,7 @@ module sha1_core(
 
   parameter CTRL_IDLE   = 0;
   parameter CTRL_ROUNDS = 1;
-  parameter CTRL_DIGEST = 2;
-  parameter CTRL_DONE   = 3;
+  parameter CTRL_DONE   = 2;
 
 
   //----------------------------------------------------------------
@@ -161,18 +160,18 @@ module sha1_core(
     begin : reg_update
       if (!reset_n)
         begin
-          a_reg            <= 32'h00000000;
-          b_reg            <= 32'h00000000;
-          c_reg            <= 32'h00000000;
-          d_reg            <= 32'h00000000;
-          e_reg            <= 32'h00000000;
-          H0_reg           <= 32'h00000000;
-          H1_reg           <= 32'h00000000;
-          H2_reg           <= 32'h00000000;
-          H3_reg           <= 32'h00000000;
-          H4_reg           <= 32'h00000000;
+          a_reg            <= 32'h0;
+          b_reg            <= 32'h0;
+          c_reg            <= 32'h0;
+          d_reg            <= 32'h0;
+          e_reg            <= 32'h0;
+          H0_reg           <= 32'h0;
+          H1_reg           <= 32'h0;
+          H2_reg           <= 32'h0;
+          H3_reg           <= 32'h0;
+          H4_reg           <= 32'h0;
           digest_valid_reg <= 0;
-          round_ctr_reg    <= 7'b0000000;
+          round_ctr_reg    <= 7'b0;
           sha1_ctrl_reg    <= CTRL_IDLE;
         end
       else
@@ -196,19 +195,13 @@ module sha1_core(
             end
 
           if (round_ctr_we)
-            begin
-              round_ctr_reg <= round_ctr_new;
-            end
+            round_ctr_reg <= round_ctr_new;
 
           if (digest_valid_we)
-            begin
-              digest_valid_reg <= digest_valid_new;
-            end
+            digest_valid_reg <= digest_valid_new;
 
           if (sha1_ctrl_we)
-            begin
-              sha1_ctrl_reg <= sha1_ctrl_new;
-            end
+            sha1_ctrl_reg <= sha1_ctrl_new;
         end
     end // reg_update
 
@@ -220,11 +213,11 @@ module sha1_core(
   //----------------------------------------------------------------
   always @*
     begin : digest_logic
-      H0_new = 32'h00000000;
-      H1_new = 32'h00000000;
-      H2_new = 32'h00000000;
-      H3_new = 32'h00000000;
-      H4_new = 32'h00000000;
+      H0_new = 32'h0;
+      H1_new = 32'h0;
+      H2_new = 32'h0;
+      H3_new = 32'h0;
+      H4_new = 32'h0;
       H_we = 0;
 
       if (digest_init)
@@ -262,15 +255,15 @@ module sha1_core(
       reg [31 : 0] k;
       reg [31 : 0] t;
 
-      a5     = 32'h00000000;
-      f      = 32'h00000000;
-      k      = 32'h00000000;
-      t      = 32'h00000000;
-      a_new  = 32'h00000000;
-      b_new  = 32'h00000000;
-      c_new  = 32'h00000000;
-      d_new  = 32'h00000000;
-      e_new  = 32'h00000000;
+      a5     = 32'h0;
+      f      = 32'h0;
+      k      = 32'h0;
+      t      = 32'h0;
+      a_new  = 32'h0;
+      b_new  = 32'h0;
+      c_new  = 32'h0;
+      d_new  = 32'h0;
+      e_new  = 32'h0;
       a_e_we = 0;
 
       if (state_init)
@@ -416,20 +409,15 @@ module sha1_core(
 
             if (round_ctr_reg == SHA1_ROUNDS)
               begin
-                sha1_ctrl_new = CTRL_DIGEST;
+                sha1_ctrl_new = CTRL_DONE;
                 sha1_ctrl_we  = 1;
               end
           end
 
-        CTRL_DIGEST:
-          begin
-            digest_update = 1;
-            sha1_ctrl_new = CTRL_DONE;
-            sha1_ctrl_we  = 1;
-          end
 
         CTRL_DONE:
           begin
+            digest_update    = 1;
             digest_valid_new = 1;
             digest_valid_we  = 1;
             sha1_ctrl_new    = CTRL_IDLE;
diff --git a/src/rtl/sha1_w_mem.v b/src/rtl/sha1_w_mem.v
index 4bc307d..f50741e 100644
--- a/src/rtl/sha1_w_mem.v
+++ b/src/rtl/sha1_w_mem.v
@@ -116,25 +116,13 @@ module sha1_w_mem(
   //----------------------------------------------------------------
   always @ (posedge clk or negedge reset_n)
     begin : reg_update
+      integer i;
+
       if (!reset_n)
         begin
-          w_mem[00]           <= 32'h00000000;
-          w_mem[01]           <= 32'h00000000;
-          w_mem[02]           <= 32'h00000000;
-          w_mem[03]           <= 32'h00000000;
-          w_mem[04]           <= 32'h00000000;
-          w_mem[05]           <= 32'h00000000;
-          w_mem[06]           <= 32'h00000000;
-          w_mem[07]           <= 32'h00000000;
-          w_mem[08]           <= 32'h00000000;
-          w_mem[09]           <= 32'h00000000;
-          w_mem[10]           <= 32'h00000000;
-          w_mem[11]           <= 32'h00000000;
-          w_mem[12]           <= 32'h00000000;
-          w_mem[13]           <= 32'h00000000;
-          w_mem[14]           <= 32'h00000000;
-          w_mem[15]           <= 32'h00000000;
-          w_ctr_reg           <= 7'h00;
+          for (i = 0 ; i < 16 ; i = i + 1)
+            w_mem[i] <= 32'h0;
+
           sha1_w_mem_ctrl_reg <= CTRL_IDLE;
         end
       else
@@ -160,15 +148,10 @@ module sha1_w_mem(
             end
 
           if (w_ctr_we)
-            begin
-              w_ctr_reg <= w_ctr_new;
-            end
+            w_ctr_reg <= w_ctr_new;
 
           if (sha1_w_mem_ctrl_we)
-            begin
-              sha1_w_mem_ctrl_reg <= sha1_w_mem_ctrl_new;
-            end
-
+            sha1_w_mem_ctrl_reg <= sha1_w_mem_ctrl_new;
         end
     end // reg_update
 
@@ -180,7 +163,7 @@ module sha1_w_mem(
   // memory or the next w value calculated.
   //----------------------------------------------------------------
   always @*
-    begin : w_schedule
+    begin : select_w
       if (w_ctr_reg < 16)
         begin
           w_tmp = w_mem[w_ctr_reg[3 : 0]];
@@ -189,7 +172,7 @@ module sha1_w_mem(
         begin
           w_tmp = w_new;
         end
-    end // w_schedule
+    end // select_w
 
 
   //----------------------------------------------------------------
@@ -206,22 +189,22 @@ module sha1_w_mem(
       reg [31 : 0] w_13;
       reg [31 : 0] w_16;
 
-      w_mem00_new = 32'h00000000;
-      w_mem01_new = 32'h00000000;
-      w_mem02_new = 32'h00000000;
-      w_mem03_new = 32'h00000000;
-      w_mem04_new = 32'h00000000;
-      w_mem05_new = 32'h00000000;
-      w_mem06_new = 32'h00000000;
-      w_mem07_new = 32'h00000000;
-      w_mem08_new = 32'h00000000;
-      w_mem09_new = 32'h00000000;
-      w_mem10_new = 32'h00000000;
-      w_mem11_new = 32'h00000000;
-      w_mem12_new = 32'h00000000;
-      w_mem13_new = 32'h00000000;
-      w_mem14_new = 32'h00000000;
-      w_mem15_new = 32'h00000000;
+      w_mem00_new = 32'h0;
+      w_mem01_new = 32'h0;
+      w_mem02_new = 32'h0;
+      w_mem03_new = 32'h0;
+      w_mem04_new = 32'h0;
+      w_mem05_new = 32'h0;
+      w_mem06_new = 32'h0;
+      w_mem07_new = 32'h0;
+      w_mem08_new = 32'h0;
+      w_mem09_new = 32'h0;
+      w_mem10_new = 32'h0;
+      w_mem11_new = 32'h0;
+      w_mem12_new = 32'h0;
+      w_mem13_new = 32'h0;
+      w_mem14_new = 32'h0;
+      w_mem15_new = 32'h0;
       w_mem_we    = 0;
 
       w_0   = w_mem[0];
@@ -283,12 +266,12 @@ module sha1_w_mem(
   //----------------------------------------------------------------
   always @*
     begin : w_ctr
-      w_ctr_new = 7'h00;
+      w_ctr_new = 7'h0;
       w_ctr_we  = 0;
 
       if (w_ctr_rst)
         begin
-          w_ctr_new = 7'h00;
+          w_ctr_new = 7'h0;
           w_ctr_we  = 1;
         end
 
@@ -337,7 +320,7 @@ module sha1_w_mem(
               end
           end
       endcase // case (sha1_ctrl_reg)
-    end // sha1_ctrl_fsm
+    end // sha1_w_mem_fsm
 endmodule // sha1_w_mem
 
 //======================================================================