Adding the functionality to extractd and set the intrnal hash state. Note: The functionality has not yet been debugged. Need to add test case.HEADmaster

2 files changed, 60 insertions, 1 deletions

diff --git a/src/rtl/sha1.v b/src/rtl/sha1.v
index 16b565e..4e57a29 100644
--- a/src/rtl/sha1.v
+++ b/src/rtl/sha1.v
@@ -64,6 +64,7 @@ module sha1(
   localparam ADDR_CTRL        = 8'h08;
   localparam CTRL_INIT_BIT    = 0;
   localparam CTRL_NEXT_BIT    = 1;
+  localparam CTRL_SET_BIT     = 2;
 
   localparam ADDR_STATUS      = 8'h09;
   localparam STATUS_READY_BIT = 0;
@@ -75,9 +76,12 @@ module sha1(
   localparam ADDR_DIGEST0   = 8'h20;
   localparam ADDR_DIGEST4   = 8'h24;
 
+  localparam ADDR_STATE0    = 8'h30;
+  localparam ADDR_STATE4    = 8'h34;
+
   localparam CORE_NAME0     = 32'h73686131; // "sha1"
   localparam CORE_NAME1     = 32'h20202020; // "    "
-  localparam CORE_VERSION   = 32'h302e3630; // "0.60"
+  localparam CORE_VERSION   = 32'h302e3730; // "0.70"
 
 
   //----------------------------------------------------------------
@@ -89,11 +93,17 @@ module sha1(
   reg next_reg;
   reg next_new;
 
+  reg set_reg;
+  reg set_new;
+
   reg ready_reg;
 
   reg [31 : 0] block_reg [0 : 15];
   reg          block_we;
 
+  reg [31 : 0] state_reg [0 : 4];
+  reg          state_we;
+
   reg [159 : 0] digest_reg;
 
   reg digest_valid_reg;
@@ -105,6 +115,8 @@ module sha1(
   wire           core_ready;
   wire [511 : 0] core_block;
   wire [159 : 0] core_digest;
+  wire [159 : 0] core_state_in;
+  wire [159 : 0] core_state_out;
   wire           core_digest_valid;
 
   reg [31 : 0]   tmp_read_data;
@@ -114,6 +126,9 @@ module sha1(
   //----------------------------------------------------------------
   // Concurrent connectivity for ports etc.
   //----------------------------------------------------------------
+  assign core_state_in = {state_reg[4], state_reg[3], state_reg[2],
+                          state_reg[1],state_reg[0]};
+
   assign core_block = {block_reg[00], block_reg[01], block_reg[02], block_reg[03],
                        block_reg[04], block_reg[05], block_reg[06], block_reg[07],
                        block_reg[08], block_reg[09], block_reg[10], block_reg[11],
@@ -132,9 +147,13 @@ module sha1(
 
                  .init(init_reg),
                  .next(next_reg),
+                 .set(set_reg),
 
                  .block(core_block),
 
+                 .state_in(core_state_in),
+                 .state_out(core_state_out),
+
                  .ready(core_ready),
 
                  .digest(core_digest),
@@ -156,12 +175,16 @@ module sha1(
         begin
           init_reg         <= 1'h0;
           next_reg         <= 1'h0;
+          set_reg          <= 1'h0;
           ready_reg        <= 1'h0;
           digest_reg       <= 160'h0;
           digest_valid_reg <= 1'h0;
 
           for (i = 0 ; i < 16 ; i = i + 1)
             block_reg[i] <= 32'h0;
+
+          for (i = 0 ; i < 5 ; i = i + 1)
+            state_reg[i] <= 32'h0;
         end
       else
         begin
@@ -169,6 +192,10 @@ module sha1(
           digest_valid_reg <= core_digest_valid;
           init_reg         <= init_new;
           next_reg         <= next_new;
+          set_reg          <= set_new;
+
+          if (state_we)
+            state_reg[address[2 : 0]] <= write_data;
 
           if (block_we)
             block_reg[address[3 : 0]] <= write_data;
@@ -187,7 +214,9 @@ module sha1(
     begin : api
       init_new      = 0;
       next_new      = 0;
+      set_new       = 1'h0;
       block_we      = 0;
+      state_we      = 0;
       tmp_read_data = 32'h0;
       tmp_error     = 0;
 
@@ -200,10 +229,14 @@ module sha1(
                   if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15))
                     block_we = 1;
 
+                  if ((address >= ADDR_STATE0) && (address <= ADDR_STATE4))
+                    state_we = 1;
+
                   if (address == ADDR_CTRL)
                     begin
                       init_new = write_data[CTRL_INIT_BIT];
                       next_new = write_data[CTRL_NEXT_BIT];
+                      set_new  = write_data[CTRL_SET_BIT];
                     end
                 end
             end // if (write_read)
@@ -212,6 +245,10 @@ module sha1(
               if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15))
                 tmp_read_data = block_reg[address[3 : 0]];
 
+              if ((address >= ADDR_STATE0) && (address <= ADDR_STATE4))
+                if (core_ready)
+                  tmp_read_data = core_state_out[(4 - (address - ADDR_STATE0)) * 32 +: 32];
+
               if ((address >= ADDR_DIGEST0) && (address <= ADDR_DIGEST4))
                 if (core_ready)
                   tmp_read_data = digest_reg[(4 - (address - ADDR_DIGEST0)) * 32 +: 32];
diff --git a/src/rtl/sha1_core.v b/src/rtl/sha1_core.v
index d055467..9078018 100644
--- a/src/rtl/sha1_core.v
+++ b/src/rtl/sha1_core.v
@@ -44,9 +44,13 @@ module sha1_core(
 
                  input wire            init,
                  input wire            next,
+                 input wire            set,
 
                  input wire [511 : 0]  block,
 
+                 input wire [159 : 0]  state_in,
+                 output wire [159 : 0] state_out,
+
                  output wire           ready,
 
                  output wire [159 : 0] digest,
@@ -119,6 +123,7 @@ module sha1_core(
   reg           digest_update;
   reg           init_state;
   reg           update_state;
+  reg           set_state;
   reg           first_block;
   reg           ready_flag;
   reg           w_init;
@@ -146,6 +151,7 @@ module sha1_core(
   // Concurrent connectivity for ports etc.
   //----------------------------------------------------------------
   assign ready        = ready_flag;
+  assign state_out    = {e_reg, d_reg, c_reg, b_reg, a_reg};
   assign digest       = {H0_reg, H1_reg, H2_reg, H3_reg, H4_reg};
   assign digest_valid = digest_valid_reg;
 
@@ -321,6 +327,16 @@ module sha1_core(
           e_new  = d_reg;
           a_e_we = 1;
         end
+
+      if (set_state)
+        begin
+          a_new  = state_in[031 : 000];
+          b_new  = state_in[063 : 032];
+          c_new  = state_in[095 : 064];
+          d_new  = state_in[127 : 096];
+          e_new  = state_in[159 : 128];
+          a_e_we = 1;
+        end
     end // state_logic
 
 
@@ -359,6 +375,7 @@ module sha1_core(
       digest_update    = 0;
       init_state       = 0;
       update_state     = 0;
+      set_state        = 0;
       first_block      = 0;
       ready_flag       = 0;
       w_init           = 0;
@@ -375,6 +392,11 @@ module sha1_core(
           begin
             ready_flag = 1;
 
+            if (set)
+              begin
+                set_state = 1'h1;
+              end
+
             if (init)
               begin
                 digest_init      = 1;