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authorJoachim StroĢˆmbergson <joachim@secworks.se>2018-10-03 11:28:18 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2018-10-03 11:28:18 +0200
commit9daf474ac53397fbe8c427493f619b89917fc8fa (patch)
treeac9898fd3156aad4920f924c1742440a859bfb0f /src/rtl
parent93802b80c67136a5f01192c17e3d1c8d2668d861 (diff)
Restricted write access for control bits to when the core is ready.
Diffstat (limited to 'src/rtl')
-rw-r--r--src/rtl/sha1.v18
1 files changed, 11 insertions, 7 deletions
diff --git a/src/rtl/sha1.v b/src/rtl/sha1.v
index 9a112b0..c1fd8ec 100644
--- a/src/rtl/sha1.v
+++ b/src/rtl/sha1.v
@@ -195,13 +195,16 @@ module sha1(
begin
if (we)
begin
- if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15))
- block_we = 1;
-
- if (address == ADDR_CTRL)
+ if (core_ready)
begin
- init_new = write_data[CTRL_INIT_BIT];
- next_new = write_data[CTRL_NEXT_BIT];
+ if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15))
+ block_we = 1;
+
+ if (address == ADDR_CTRL)
+ begin
+ init_new = write_data[CTRL_INIT_BIT];
+ next_new = write_data[CTRL_NEXT_BIT];
+ end
end
end // if (write_read)
else
@@ -210,7 +213,8 @@ module sha1(
tmp_read_data = block_reg[address[3 : 0]];
if ((address >= ADDR_DIGEST0) && (address <= ADDR_DIGEST4))
- tmp_read_data = digest_reg[(4 - (address - ADDR_DIGEST0)) * 32 +: 32];
+ if (core_ready)
+ tmp_read_data = digest_reg[(4 - (address - ADDR_DIGEST0)) * 32 +: 32];
case (address)
// Read operations.