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authorJoachim StroĢˆmbergson <joachim@secworks.se>2014-03-17 09:07:53 +0100
committerJoachim StroĢˆmbergson <joachim@secworks.se>2014-03-17 09:07:53 +0100
commited0edb437fe02c44e555ab8396e53fd081d72a15 (patch)
tree19e50f5bcac0a1c47f2f24630da7b198507c51bd /src/rtl
parentaf4e88047d524f2d0b43402e51476fa1932efe95 (diff)
Removed redundant flag reset wires.
Diffstat (limited to 'src/rtl')
-rw-r--r--src/rtl/sha1.v24
1 files changed, 3 insertions, 21 deletions
diff --git a/src/rtl/sha1.v b/src/rtl/sha1.v
index 6033672..d4ed620 100644
--- a/src/rtl/sha1.v
+++ b/src/rtl/sha1.v
@@ -103,13 +103,11 @@ module sha1(
reg init_new;
reg init_we;
reg init_set;
- reg init_rst;
reg next_reg;
reg next_new;
reg next_we;
reg next_set;
- reg next_rst;
reg ready_reg;
@@ -370,6 +368,7 @@ module sha1(
next_we = 1;
end
end
+
//----------------------------------------------------------------
// api
@@ -379,9 +378,7 @@ module sha1(
always @*
begin : api
init_set = 0;
- init_rst = 0;
next_set = 0;
- next_rst = 0;
block0_we = 0;
block1_we = 0;
block2_we = 0;
@@ -409,23 +406,8 @@ module sha1(
// Write operations.
ADDR_CTRL:
begin
- if (write_data[CTRL_INIT_BIT])
- begin
- init_set = 1;
- end
- else
- begin
- init_rst = 1;
- end
-
- if (write_data[CTRL_NEXT_BIT])
- begin
- next_set = 1;
- end
- else
- begin
- next_rst = 1;
- end
+ init_set = write_data[CTRL_INIT_BIT];
+ next_set = write_data[CTRL_NEXT_BIT];
end
ADDR_BLOCK0: