core/cipher/chacha - Verilog 2001 implementation of the ChaCha stream cipher

Age	Commit message (Collapse)	Author
2019-02-08	(1) Removed reset input port from qr module, qr module instances and qr ↵HEAD master	Joachim Strömbergson
	module tb. (2) Fixed non blocking assigment erroneously used in comboinational process.
2019-02-07	Change reset to asynch assert. This matches comment. It also matches what is ↵	Joachim Strömbergson
	used in the TRNG core where the chacha core is instantiated. Also removed reset from the pipeline registers.
2018-10-23	Hardening the API to block writes to contol signals when core is performing ↵	Joachim Strömbergson
	operations. Also blocking access to data out when core is busy. Minor cleanup of defines. Changed init and next flags to automatically toggle back to zero.
2018-10-16	Adding width specification, fixed order and other nits as part of ceckning ↵	Joachim Strömbergson
	that all registers are properly reset.
2016-12-28	(1) Cleanup of top an core code with no functional changes. The code is now ↵cleanup	Joachim Strömbergson
	much more compact. (2) Fixed how the QR modules are used in parallel to actually work in parallel. This increases performance. (3) Changed registers into arrays and cleaned up how operands and data are accessed. This decreased total design size.
2015-04-30	(1) Added api addresses and constants for core name and version. (2) Changed ↵	Joachim Strömbergson
	addresses for control, status and config to match the ct standard. (3) Updated the testbench to use the changed addresses.
2014-11-06	Fixes to nits found using the verilator linter.	Joachim Strömbergson

2014-09-26	Update of ChaCha with fixes found during synthesis.	Joachim Strömbergson

2014-09-03	Adding RTL code for the ChaCha stream cipher.	Joachim Strömbergson