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author | Joachim StroĢmbergson <joachim@assured.se> | 2019-02-07 14:30:01 +0100 |
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committer | Joachim StroĢmbergson <joachim@assured.se> | 2019-02-07 14:30:01 +0100 |
commit | de3f38a835ad9ac5ad8b6153a6b363c23641a3f8 (patch) | |
tree | d0f41bbfab2ac98ae59012d294e15bd71317491e /src/rtl/chacha.v | |
parent | 447efe94126531908899a0749a21766534d78965 (diff) |
Change reset to asynch assert. This matches comment. It also matches what is used in the TRNG core where the chacha core is instantiated. Also removed reset from the pipeline registers.
Diffstat (limited to 'src/rtl/chacha.v')
-rw-r--r-- | src/rtl/chacha.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/rtl/chacha.v b/src/rtl/chacha.v index 360ff1a..435555b 100644 --- a/src/rtl/chacha.v +++ b/src/rtl/chacha.v @@ -170,7 +170,7 @@ module chacha( // All registers are positive edge triggered with asynchronous // active low reset. All registers have write enable. //---------------------------------------------------------------- - always @ (posedge clk) + always @ (posedge clk or negedge reset_n) begin : reg_update integer i; if (!reset_n) |