3 files changed, 7 insertions, 15 deletions
diff --git a/src/rtl/chacha.v b/src/rtl/chacha.v
index 360ff1a..435555b 100644
--- a/src/rtl/chacha.v
+++ b/src/rtl/chacha.v
@@ -170,7 +170,7 @@ module chacha(
   // All registers are positive edge triggered with asynchronous
   // active low reset. All registers have write enable.
   //----------------------------------------------------------------
-  always @ (posedge clk)
+  always @ (posedge clk or negedge reset_n)
     begin : reg_update
      integer i;
       if (!reset_n)
diff --git a/src/rtl/chacha_core.v b/src/rtl/chacha_core.v
index cc91327..20aecec 100644
--- a/src/rtl/chacha_core.v
+++ b/src/rtl/chacha_core.v
@@ -269,7 +269,7 @@ module chacha_core(
   // All registers are positive edge triggered with synchronous
   // active low reset. All registers have write enable.
   //----------------------------------------------------------------
-  always @ (posedge clk)
+  always @ (posedge clk or negedge reset_n)
     begin : reg_update
      integer i;
 
diff --git a/src/rtl/chacha_qr.v b/src/rtl/chacha_qr.v
index ec29c70..02fe59b 100644
--- a/src/rtl/chacha_qr.v
+++ b/src/rtl/chacha_qr.v
@@ -85,22 +85,14 @@ module chacha_qr(
 
   //----------------------------------------------------------------
   // reg_update
+  //
+  // Pipeline registers. Does not need reset.
   //----------------------------------------------------------------
   always @ (posedge clk)
     begin : reg_update
-      if (!reset_n)
-        begin
-          a0_reg <= 32'h0;
-          a1_reg <= 32'h0;
-          c0_reg <= 32'h0;
-        end
-
-      else
-        begin
-          a0_reg <= a0_new;
-          a1_reg <= a1_new;
-          c0_reg <= c0_new;
-        end
+      a0_reg <= a0_new;
+      a1_reg <= a1_new;
+      c0_reg <= c0_new;
     end // reg_update