test/novena_base - Cryptech Novena FPGA baseline

Age	Commit message (Expand)	Author
2015-02-12	Fix command-line build to support explicit path to ucf file.HEAD master	Paul Selkirk
2015-02-12	Merge branch 'coretest_hashes' of git.cryptech.is:test/novena_base into master	Paul Selkirk
2015-02-10	Reformat verilog code for readability.	Paul Selkirk
2015-02-10	First stage of integration cleanup.	Paul Selkirk
2015-02-10	Updates from Pavel with new mux.	Paul Selkirk
2015-02-06	Adding ports for the core selector to include Cryptech ports. Moving the Cryp...	Joachim Strömbergson
2015-02-06	Made sure that we name the ports the same as in the ucf.	Joachim Strömbergson
2015-02-06	Adding a bit of test logic to see that the noise board is properly connected.	Joachim Strömbergson
2015-02-05	add all SHA cores (hello coretest_hashes)	Paul Selkirk
2015-02-05	Removed space between text and semicolon.	Joachim Strömbergson
2015-02-05	Adding ports for cryptech noise sources.	Joachim Strömbergson
2015-02-05	Adding pins for the LEDs on the Cryptech avalanche noise board.	Joachim Strömbergson
2015-02-03	(1) Updated core selector with logic to connect sha256. (2) Adding test sw th...	Joachim Strömbergson
2015-02-03	More attempts at getting the addresss decoder to work...	Joachim Strömbergson
2015-02-02	add a command-line build, for those who like that sort of thing	Paul Selkirk
2015-02-02	update project file paths to .v and .ucf files	Paul Selkirk
2015-02-02	Passes build without any warnings.	Joachim Strömbergson
2015-02-02	Added real prefix detection of sha255 core.	Joachim Strömbergson
2015-02-02	Changed core_selector to instead use the cryptech sha256 core.	Joachim Strömbergson
2015-02-02	Changing to Verilog 2001 style interface. Changed port names to not have inpo...	Joachim Strömbergson
2015-02-01	Changed to Verilog 2001 interface. Added ports for Cryptech avalanche noise b...	Joachim Strömbergson
2015-02-01	Added header with license and info to the constraint file.	Joachim Strömbergson
2015-02-01	Added proper file headers to all verilog source files.	Joachim Strömbergson
2015-02-01	Removed trailing whitespace and ^M.	Joachim Strömbergson
2015-02-01	Updated the dcm to generate sys_clk at 50 MHz. Added Pavels project files.	Joachim Strömbergson
2015-02-01	Removed trailing whitespace and DOS ^M.	Joachim Strömbergson
2015-01-31	Adding all main hw source files and constraints.	Joachim Strömbergson