add all SHA cores (hello coretest_hashes)

8 files changed, 564 insertions, 137 deletions

diff --git a/rtl/build/.gitignore b/rtl/build/.gitignore
new file mode 100644
index 0000000..e60e316
--- /dev/null
+++ b/rtl/build/.gitignore
@@ -0,0 +1,52 @@
+*.xrpt
+_xmsgs
+default.xreport
+netlist.lst
+novena_baseline_top.bgn
+novena_baseline_top.bit
+novena_baseline_top.bld
+novena_baseline_top.cfi
+novena_baseline_top.drc
+novena_baseline_top.lso
+novena_baseline_top.lso
+novena_baseline_top.map
+novena_baseline_top.mcs
+novena_baseline_top.mrp
+novena_baseline_top.ncd
+novena_baseline_top.ngc
+novena_baseline_top.ngd
+novena_baseline_top.ngm
+novena_baseline_top.pcf
+novena_baseline_top.post_map.twr
+novena_baseline_top.post_map.twx
+novena_baseline_top.prj
+novena_baseline_top.prm
+novena_baseline_top.psr
+novena_baseline_top.scr
+novena_baseline_top.srp
+novena_baseline_top.twr
+novena_baseline_top.twx
+novena_baseline_top_bd.bmm
+novena_baseline_top_bitgen.xwb
+novena_baseline_top_bitgen.xwbt
+novena_baseline_top_err.twr
+novena_baseline_top_err.twx
+novena_baseline_top_par.grf
+novena_baseline_top_par.ncd
+novena_baseline_top_par.pad
+novena_baseline_top_par.par
+novena_baseline_top_par.ptwx
+novena_baseline_top_par.unroutes
+novena_baseline_top_par.xpi
+novena_baseline_top_par_pad.csv
+novena_baseline_top_par_pad.txt
+novena_baseline_top_summary.xml
+novena_baseline_top_usage.xml
+par_usage_statistics.html
+smartguide.ncd
+smartpreview.twr
+smartpreview.twr
+usage_statistics_webtalk.html
+webtalk.log
+xlnx_auto*
+xst
diff --git a/rtl/build/Makefile b/rtl/build/Makefile
new file mode 100644
index 0000000..ec03197
--- /dev/null
+++ b/rtl/build/Makefile
@@ -0,0 +1,32 @@
+project = novena_baseline_top
+vendor = xilinx
+family = spartan6
+part = xc6slx45csg324-3
+top_module = novena_baseline_top
+isedir = /opt/Xilinx/14.7/ISE_DS
+xil_env = . $(isedir)/settings64.sh
+
+vfiles = \
+	../src/verilog/novena_baseline_top.v \
+	../src/verilog/novena_clkmgr.v \
+	../src/verilog/cdc_bus_pulse.v \
+	../src/verilog/eim_arbiter.v \
+	../src/verilog/eim_da_phy.v \
+	../src/verilog/eim_arbiter_cdc.v \
+	../src/verilog/core_selector.v \
+	../src/verilog/eim_indicator.v \
+	../src/ipcore/clkmgr_dcm.v \
+	../../../../core/sha256/src/rtl/sha256_core.v \
+	../../../../core/sha256/src/rtl/sha256_k_constants.v \
+	../../../../core/sha256/src/rtl/sha256.v \
+	../../../../core/sha256/src/rtl/sha256_w_mem.v \
+	../../../../core/sha1/src/rtl/sha1_core.v \
+	../../../../core/sha1/src/rtl/sha1.v \
+	../../../../core/sha1/src/rtl/sha1_w_mem.v \
+	../../../../core/sha512/src/rtl/sha512_core.v \
+	../../../../core/sha512/src/rtl/sha512_h_constants.v \
+	../../../../core/sha512/src/rtl/sha512_k_constants.v \
+	../../../../core/sha512/src/rtl/sha512.v \
+	../../../../core/sha512/src/rtl/sha512_w_mem.v
+
+include xilinx.mk
diff --git a/rtl/build/novena_baseline_top.bmm b/rtl/build/novena_baseline_top.bmm
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/rtl/build/novena_baseline_top.bmm
diff --git a/rtl/build/novena_baseline_top.ucf b/rtl/build/novena_baseline_top.ucf
new file mode 120000
index 0000000..fddd839
--- /dev/null
+++ b/rtl/build/novena_baseline_top.ucf
@@ -0,0 +1 @@
+../src/ucf/novena_baseline.ucf
\ No newline at end of file
diff --git a/rtl/build/xilinx.mk b/rtl/build/xilinx.mk
new file mode 100644
index 0000000..a3a0216
--- /dev/null
+++ b/rtl/build/xilinx.mk
@@ -0,0 +1,176 @@
+# The top level module should define the variables below then include
+# this file.  The files listed should be in the same directory as the
+# Makefile.  
+#
+#   variable	description
+#   ----------  -------------
+#   project	project name (top level module should match this name)
+#   top_module  top level module of the project
+#   libdir	path to library directory
+#   libs	library modules used
+#   vfiles	all local .v files
+#   xilinx_cores  all local .xco files
+#   vendor      vendor of FPGA (xilinx, altera, etc.)
+#   family      FPGA device family (spartan3e) 
+#   part        FPGA part name (xc4vfx12-10-sf363)
+#   flashsize   size of flash for mcs file (16384)
+#   optfile     (optional) xst extra opttions file to put in .scr
+#   map_opts    (optional) options to give to map
+#   par_opts    (optional) options to give to par
+#   intstyle    (optional) intstyle option to all tools
+#
+#   files 		description
+#   ----------  	------------
+#   $(project).ucf	ucf file
+#
+# Library modules should have a modules.mk in their root directory,
+# namely $(libdir)/<libname>/module.mk, that simply adds to the vfiles
+# and xilinx_cores variable.
+#
+# all the .xco files listed in xilinx_cores will be generated with core, with
+# the resulting .v and .ngc files placed back in the same directory as
+# the .xco file.
+#
+# TODO: .xco files are device dependant, should use a template based system
+
+coregen_work_dir ?= ./coregen-tmp
+map_opts ?= -timing -ol high -detail -pr b -register_duplication -w
+par_opts ?= -ol high
+isedir ?= /opt/Xilinx/13.3/ISE_DS
+xil_env ?= . $(isedir)/settings32.sh
+flashsize ?= 8192
+
+libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs)) 
+mkfiles = Makefile $(libmks) xilinx.mk
+include $(libmks)
+
+corengcs = $(foreach core,$(xilinx_cores),$(core:.xco=.ngc))
+local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc)))
+vfiles += $(foreach core,$(xilinx_cores),$(core:.xco=.v))
+junk += $(local_corengcs)
+
+.PHONY: default xilinx_cores clean twr etwr
+default: $(project).bit $(project).mcs
+xilinx_cores: $(corengcs)
+twr: $(project).twr
+etwr: $(project)_err.twr
+
+define cp_template
+$(2): $(1)
+	cp $(1) $(2)
+endef
+$(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc)))))
+
+%.ngc %.v: %.xco
+	@echo "=== rebuilding $@"
+	if [ -d $(coregen_work_dir) ]; then \
+		rm -rf $(coregen_work_dir)/*; \
+	else \
+		mkdir -p $(coregen_work_dir); \
+	fi
+	cd $(coregen_work_dir); \
+	$(xil_env); \
+	coregen -b $$OLDPWD/$<; \
+	cd -
+	xcodir=`dirname $<`; \
+	basename=`basename $< .xco`; \
+	if [ ! -r $(coregen_work_dir/$$basename.ngc) ]; then \
+		echo "'$@' wasn't created."; \
+		exit 1; \
+	else \
+		cp $(coregen_work_dir)/$$basename.v $(coregen_work_dir)/$$basename.ngc $$xcodir; \
+	fi
+junk += $(coregen_work_dir)
+
+date = $(shell date +%F-%H-%M)
+
+# some common junk
+junk += *.xrpt
+
+programming_files: $(project).bit $(project).mcs
+	mkdir -p $@/$(date)
+	mkdir -p $@/latest
+	for x in .bit .mcs .cfi _bd.bmm; do cp $(project)$$x $@/$(date)/$(project)$$x; cp $(project)$$x $@/latest/$(project)$$x; done
+	$(xil_env); xst -help | head -1 | sed 's/^/#/' | cat - $(project).scr > $@/$(date)/$(project).scr
+
+$(project).mcs: $(project).bit
+	$(xil_env); \
+	promgen -w -s $(flashsize) -p mcs -o $@ -u 0 $^
+junk += $(project).mcs $(project).cfi $(project).prm
+
+$(project).bit: $(project)_par.ncd
+	$(xil_env); \
+	bitgen $(intstyle) -g UnusedPin:Pullnone -g DriveDone:yes -g StartupClk:Cclk -w $(project)_par.ncd $(project).bit
+junk += $(project).bgn $(project).bit $(project).drc $(project)_bd.bmm
+
+
+$(project)_par.ncd: $(project).ncd
+	$(xil_env); \
+	if par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd; then \
+		:; \
+	else \
+		$(MAKE) etwr; \
+	fi 
+junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad 
+junk += $(project)_par_pad.csv $(project)_par_pad.txt 
+junk += $(project)_par.grf $(project)_par.ptwx
+junk += $(project)_par.unroutes $(project)_par.xpi
+
+$(project).ncd: $(project).ngd
+	if [ -r $(project)_par.ncd ]; then \
+		cp $(project)_par.ncd smartguide.ncd; \
+		smartguide="-smartguide smartguide.ncd"; \
+	else \
+		smartguide=""; \
+	fi; \
+	$(xil_env); \
+	map $(intstyle) $(map_opts) $$smartguide $<
+junk += $(project).ncd $(project).pcf $(project).ngm $(project).mrp $(project).map
+junk += smartguide.ncd $(project).psr 
+junk += $(project)_summary.xml $(project)_usage.xml
+
+$(project).ngd: $(project).ngc $(project).ucf $(project).bmm
+	$(xil_env); ngdbuild $(intstyle) $(project).ngc -bm $(project).bmm
+junk += $(project).ngd $(project).bld
+
+$(project).ngc: $(vfiles) $(local_corengcs) $(project).scr $(project).prj
+	$(xil_env); xst $(intstyle) -ifn $(project).scr
+junk += xlnx_auto* $(top_module).lso $(project).srp 
+junk += netlist.lst xst $(project).ngc
+
+$(project).prj: $(vfiles) $(mkfiles)
+	for src in $(vfiles); do echo "verilog work $$src" >> $(project).tmpprj; done
+	sort -u $(project).tmpprj > $(project).prj
+	rm -f $(project).tmpprj
+junk += $(project).prj
+
+optfile += $(wildcard $(project).opt)
+top_module ?= $(project)
+$(project).scr: $(optfile) $(mkfiles) ./xilinx.opt
+	echo "run" > $@
+	echo "-p $(part)" >> $@
+	echo "-top $(top_module)" >> $@
+	echo "-ifn $(project).prj" >> $@
+	echo "-ofn $(project).ngc" >> $@
+	cat ./xilinx.opt $(optfile) >> $@
+junk += $(project).scr
+
+$(project).post_map.twr: $(project).ncd
+	$(xil_env); trce -e 10 $< $(project).pcf -o $@
+junk += $(project).post_map.twr $(project).post_map.twx smartpreview.twr
+
+$(project).twr: $(project)_par.ncd
+	$(xil_env); trce $< $(project).pcf -o $(project).twr
+junk += $(project).twr $(project).twx smartpreview.twr
+
+$(project)_err.twr: $(project)_par.ncd
+	$(xil_env); trce -e 10 $< $(project).pcf -o $(project)_err.twr
+junk += $(project)_err.twr $(project)_err.twx
+junk += $(project).lso $(project)_bitgen.xwb $(project)_bitgen.xwbt
+junk += usage_statistics_webtalk.html par_usage_statistics.html webtalk.log _xmsgs default.xreport
+
+.gitignore: $(mkfiles)
+	echo programming_files $(junk) | sed 's, ,\n,g' > .gitignore
+
+clean::
+	rm -rf $(junk)
diff --git a/rtl/build/xilinx.opt b/rtl/build/xilinx.opt
new file mode 100644
index 0000000..7fe9d8b
--- /dev/null
+++ b/rtl/build/xilinx.opt
@@ -0,0 +1,42 @@
+-ifmt mixed
+-ofmt NGC
+-opt_mode speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy no
+-netlist_hierarchy as_optimized
+-rtlview no
+-glob_opt AllClockNets
+-read_cores yes
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+#-dsp_utilization_ratio 100
+-safe_implementation No
+-fsm_extract YES
+-fsm_encoding Auto
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-rom_style Auto
+-shreg_extract YES
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+#-use_dsp48 auto
+-iobuf YES
+-max_fanout 500
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/rtl/iseconfig/novena_baseline.xise b/rtl/iseconfig/novena_baseline.xise
index a270ac9..10c31e5 100644
--- a/rtl/iseconfig/novena_baseline.xise
+++ b/rtl/iseconfig/novena_baseline.xise
@@ -15,56 +15,104 @@
   <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
 
   <files>
-    <file xil_pn:name="src/verilog/novena_baseline_top.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../src/verilog/novena_baseline_top.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     </file>
-    <file xil_pn:name="src/verilog/novena_clkmgr.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../src/verilog/novena_clkmgr.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
-    <file xil_pn:name="src/ipcore/clkmgr_dcm.xco" xil_pn:type="FILE_COREGEN">
+    <file xil_pn:name="../src/ipcore/clkmgr_dcm.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
-    <file xil_pn:name="src/verilog/cdc_bus_pulse.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../src/verilog/cdc_bus_pulse.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
-    <file xil_pn:name="src/verilog/eim_arbiter.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../src/verilog/eim_arbiter.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     </file>
-    <file xil_pn:name="src/verilog/demo_adder.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../src/verilog/demo_adder.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="src/verilog/eim_da_phy.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../src/verilog/eim_da_phy.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
-    <file xil_pn:name="src/verilog/eim_arbiter_cdc.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../src/verilog/eim_arbiter_cdc.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
-    <file xil_pn:name="src/ucf/novena_baseline.ucf" xil_pn:type="FILE_UCF">
+    <file xil_pn:name="../src/ucf/novena_baseline.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="src/verilog/core_selector.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
-    </file>
-    <file xil_pn:name="src/testbench/tb_demo_adder.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../src/testbench/tb_demo_adder.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="71"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="71"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="71"/>
     </file>
-    <file xil_pn:name="src/verilog/eim_indicator.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../src/verilog/eim_indicator.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+    </file>
+    <file xil_pn:name="../src/verilog/core_selector.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+    </file>
+    <file xil_pn:name="../../../../core/sha1/src/rtl/sha1_core.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+    </file>
+    <file xil_pn:name="../../../../core/sha1/src/rtl/sha1_w_mem.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+    </file>
+    <file xil_pn:name="../../../../core/sha1/src/rtl/sha1.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+    </file>
+    <file xil_pn:name="../../../../core/sha256/src/rtl/sha256_core.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+    </file>
+    <file xil_pn:name="../../../../core/sha256/src/rtl/sha256_k_constants.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+    </file>
+    <file xil_pn:name="../../../../core/sha256/src/rtl/sha256_w_mem.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+    </file>
+    <file xil_pn:name="../../../../core/sha256/src/rtl/sha256.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+    </file>
+    <file xil_pn:name="../../../../core/sha512/src/rtl/sha512_core.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+    </file>
+    <file xil_pn:name="../../../../core/sha512/src/rtl/sha512_h_constants.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+    </file>
+    <file xil_pn:name="../../../../core/sha512/src/rtl/sha512_k_constants.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="../../../../core/sha512/src/rtl/sha512_w_mem.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="../../../../core/sha512/src/rtl/sha512.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
-    <file xil_pn:name="src/ipcore/clkmgr_dcm.xise" xil_pn:type="FILE_COREGENISE">
+    <file xil_pn:name="../src/ipcore/clkmgr_dcm.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
   </files>
@@ -103,7 +151,7 @@
     <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
     <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
     <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -194,7 +242,7 @@
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Implementation Top" xil_pn:value="Module|novena_baseline_top" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="src/verilog/novena_baseline_top.v" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../src/verilog/novena_baseline_top.v" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/novena_baseline_top" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v
index 3f74a26..7479848 100644
--- a/rtl/src/verilog/core_selector.v
+++ b/rtl/src/verilog/core_selector.v
@@ -1,18 +1,21 @@
 //======================================================================
 //
-// core_selector.v
-// ---------------
-// Core selector Cryptech Novena FPGA framework.
+// coretest_hashes.v
+// -----------------
+// Top level wrapper that creates the Cryptech coretest system.
+// The wrapper contains instances of external interface, coretest
+// and the core to be tested. And if more than one core is
+// present the wrapper also includes address and data muxes.
 //
 //
-// Author: Pavel Shatov
-// Copyright (c) 2014, NORDUnet A/S All rights reserved.
-//
+// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov
+// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
+// 
 // Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-// - Redistributions of source code must retain the above copyright
-//   notice, this list of conditions and the following disclaimer.
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+//   this list of conditions and the following disclaimer.
 //
 // - Redistributions in binary form must reproduce the above copyright
 //   notice, this list of conditions and the following disclaimer in the
@@ -37,111 +40,184 @@
 //======================================================================
 
 module core_selector
-	(
-	 input wire           sys_clk,
+        (
+         input wire           sys_clk,
          input wire           sys_rst,
 
-	 input wire [13: 0]   sys_eim_addr,
+         input wire [13: 0]   sys_eim_addr,
          input wire           sys_eim_wr,
          input wire           sys_eim_rd,
          output wire [31 : 0] read_data,
-	 input wire [31 : 0]  write_data
-	);
-
-
-  //
-  // Parameters
-  //
-  localparam	ADDER_BASE_ADDR		= 6'h00;	// upper 6 bits of address
-  localparam	ADDER_OFFSET_X_REG	= 8'h00;	// X
-  localparam	ADDER_OFFSET_Y_REG	= 8'h01;	// Y
-
-
-  /* This flag detects whether adder core is being addressed. */
-  wire eim_access_adder	= (sys_eim_addr[13:8] == ADDER_BASE_ADDR) ? 1'b1 : 1'b0;
-
-  /* These flags detect whether write or read access is requested. */
-  wire eim_access_write	= sys_eim_wr & eim_access_adder;
-  wire eim_access_read	= sys_eim_rd & eim_access_adder;
-  wire select = eim_access_read | eim_access_write;
-
-//  reg [31 : 0] read_data_reg;
-//  reg [31 : 0] y_reg;
-//  reg [31 : 0] x_reg;
-//
-//  //
-//  // Write Request Handler
-//  //
-//  always @(posedge sys_clk)
-//    //
-//    if (sys_rst) begin
-//      x_reg <= 32'hdeaddead;
-//      y_reg <= 32'hbeefbeef;
-//  end
-//    else if (eim_access_write) begin
-//      case (sys_eim_addr[7:0])
-//        ADDER_OFFSET_X_REG:  x_reg <= write_data;
-//        ADDER_OFFSET_Y_REG:  y_reg <= write_data;
-//      endcase
-//    end
-//
-//
-//  //
-//  // Read Request Handler
-//  always @(posedge sys_clk)
-//    //
-//    if (sys_rst)
-//      read_data_reg <= 32'h00000000;
-//    //
-//    else if (eim_access_read) begin
-//      //
-//      case (sys_eim_addr[7:0])
-//	ADDER_OFFSET_X_REG:	read_data_reg	<= x_reg;
-//	ADDER_OFFSET_Y_REG:	read_data_reg	<= y_reg;
-//      endcase
-//      //
-//    end
-
-//    assign read_data = read_data_reg;
-
-
-    //  localparam SHA256_BASE_ADDR = 6'h14;
-    //
-    //  wire access_sha256 = (sys_eim_addr[13 : 8] == SHA256_BASE_ADDR) ? 1'b1 : 1'b0;
-    //  wire read_access   = sys_eim_rd & access_sha256;
-    //  wire write_access  = sys_eim_wr & access_sha256;
-    //  wire select        = read_access | write_access;
-
-//  reg [31 : 0] read_data_reg;
-//  wire  [31 : 0] sha_read_data;
-//
-//  assign read_data = read_data_reg;
-//
-//  always @ (posedge sys_clk)
-//    begin
-//      if (sys_rst)
-//        begin
-//          read_data_reg <= 32'h00000000;
-//        end
-//      else
-//        begin
-//          read_data_reg <= sha_read_data;
-//        end
-//    end
-
-
-  sha256 sha256_inst(
-                     .clk(sys_clk),
-                     .reset_n(1'b1),
-
-                     .cs(eim_access_adder),
-                     .we(sys_eim_wr),
-
-                     .address(sys_eim_addr[7 : 0]),
-                     .write_data(write_data),
-                     .read_data(read_data),
-                     .error()
-                    );
+         input wire [31 : 0]  write_data
+        );
+
+
+   //----------------------------------------------------------------
+   // Internal constant and parameter definitions.
+   //----------------------------------------------------------------
+   parameter SHA1_ADDR_PREFIX   = 6'b000100;	// 0x1000 - 0x13ff
+   parameter SHA256_ADDR_PREFIX = 6'b001000;	// 0x2000 - 0x23ff
+   parameter SHA512_ADDR_PREFIX = 6'b001100;	// 0x3000 - 0x33ff
+
+
+   //----------------------------------------------------------------
+   // Wires and registers
+   //----------------------------------------------------------------
+   wire                       clk = sys_clk;
+   wire                       reset_n = !sys_rst;
+   wire [13:0]                address = sys_eim_addr;
+   wire                       cs = sys_eim_wr | sys_eim_rd;
+   wire                       we = sys_eim_wr;
+
+   reg [31:0]                 read_reg;
+   reg                        error_reg;
+
+   // sha1 connections.
+   reg                        sha1_cs;
+   reg                        sha1_we;
+   reg [7:0]                  sha1_address;
+   reg [31:0]                 sha1_write_data;
+   wire [31:0]                sha1_read_data;
+   wire                       sha1_error;
+
+   // sha256 connections.
+   reg                        sha256_cs;
+   reg                        sha256_we;
+   reg [7:0]                  sha256_address;
+   reg [31:0]                 sha256_write_data;
+   wire [31:0]                sha256_read_data;
+   wire                       sha256_error;
+
+   // sha512 connections.
+   reg                        sha512_cs;
+   reg                        sha512_we;
+   reg [7:0]                  sha512_address;
+   reg [31:0]                 sha512_write_data;
+   wire [31:0]                sha512_read_data;
+   wire                       sha512_error;
+
+
+   //----------------------------------------------------------------
+   // Concurrent assignment.
+   //----------------------------------------------------------------
+   assign read_data = read_reg;
+
+   //----------------------------------------------------------------
+   // Core instantiations.
+   //----------------------------------------------------------------
+   sha1 sha1(
+             // Clock and reset.
+             .clk(clk),
+             .reset_n(reset_n),
+
+             // Control.
+             .cs(sha1_cs),
+             .we(sha1_we),
+
+             // Data ports.
+             .address(sha1_address),
+             .write_data(sha1_write_data),
+             .read_data(sha1_read_data),
+             .error(sha1_error)
+             );
+
+
+   sha256 sha256(
+                 // Clock and reset.
+                 .clk(clk),
+                 .reset_n(reset_n),
+
+                 // Control.
+                 .cs(sha256_cs),
+                 .we(sha256_we),
+
+                 // Data ports.
+                 .address(sha256_address),
+                 .write_data(sha256_write_data),
+                 .read_data(sha256_read_data),
+                 .error(sha256_error)
+                 );
+
+
+   sha512 sha512(
+                 // Clock and reset.
+                 .clk(clk),
+                 .reset_n(reset_n),
+
+                 // Control.
+                 .cs(sha512_cs),
+                 .we(sha512_we),
+
+                 // Data ports.
+                 .address(sha512_address),
+                 .write_data(sha512_write_data),
+                 .read_data(sha512_read_data),
+                 .error(sha512_error)
+                 );
+
+   //----------------------------------------------------------------
+   // address_mux
+   //
+   // Combinational data mux that handles addressing between
+   // cores using the 32-bit memory like interface.
+   //----------------------------------------------------------------
+   always @*
+     begin : address_mux
+        // Default assignments.
+        sha1_cs            = 0;
+        sha1_we            = 0;
+        sha1_address       = 8'h00;
+        sha1_write_data    = 32'h00000000;
+
+        sha256_cs          = 0;
+        sha256_we          = 0;
+        sha256_address     = 8'h00;
+        sha256_write_data  = 32'h00000000;
+
+        sha512_cs          = 0;
+        sha512_we          = 0;
+        sha512_address     = 8'h00;
+        sha512_write_data  = 32'h00000000;
+
+        // address mux
+        case (address[13:8])
+          SHA1_ADDR_PREFIX:
+            begin
+               sha1_cs            = 1;
+               sha1_we            = we;
+               sha1_address       = address[7:0];
+               sha1_write_data    = write_data;
+               read_reg           = sha1_read_data;
+               error_reg          = sha1_error;
+            end
+
+          SHA256_ADDR_PREFIX:
+            begin
+               sha256_cs          = 1;
+               sha256_we          = we;
+               sha256_address     = address[7:0];
+               sha256_write_data  = write_data;
+               read_reg           = sha256_read_data;
+               error_reg          = sha256_error;
+            end
+
+          SHA512_ADDR_PREFIX:
+            begin
+               sha512_cs          = 1;
+               sha512_we          = we;
+               sha512_address     = address[7:0];
+               sha512_write_data  = write_data;
+               read_reg           = sha512_read_data;
+               error_reg          = sha512_error;
+            end
+
+          default:
+            begin
+               read_reg           = 32'hZZZZ;
+            end
+        endcase
+
+     end // address_mux
 
 endmodule