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//======================================================================
//
// coretest_hashes.v
// -----------------
// Top level wrapper that creates the Cryptech coretest system.
// The wrapper contains instances of external interface, coretest
// and the core to be tested. And if more than one core is
// present the wrapper also includes address and data muxes.
//
//
// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov
// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module core_selector
(
input wire sys_clk,
input wire sys_rst,
input wire [13: 0] sys_eim_addr,
input wire sys_eim_wr,
input wire sys_eim_rd,
output wire [31 : 0] read_data,
input wire [31 : 0] write_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter SHA1_ADDR_PREFIX = 6'b000100; // 0x1000 - 0x13ff
parameter SHA256_ADDR_PREFIX = 6'b001000; // 0x2000 - 0x23ff
parameter SHA512_ADDR_PREFIX = 6'b001100; // 0x3000 - 0x33ff
//----------------------------------------------------------------
// Wires and registers
//----------------------------------------------------------------
wire clk = sys_clk;
wire reset_n = !sys_rst;
wire [13:0] address = sys_eim_addr;
wire cs = sys_eim_wr | sys_eim_rd;
wire we = sys_eim_wr;
reg [31:0] read_reg;
reg error_reg;
// sha1 connections.
reg sha1_cs;
reg sha1_we;
reg [7:0] sha1_address;
reg [31:0] sha1_write_data;
wire [31:0] sha1_read_data;
wire sha1_error;
// sha256 connections.
reg sha256_cs;
reg sha256_we;
reg [7:0] sha256_address;
reg [31:0] sha256_write_data;
wire [31:0] sha256_read_data;
wire sha256_error;
// sha512 connections.
reg sha512_cs;
reg sha512_we;
reg [7:0] sha512_address;
reg [31:0] sha512_write_data;
wire [31:0] sha512_read_data;
wire sha512_error;
//----------------------------------------------------------------
// Concurrent assignment.
//----------------------------------------------------------------
assign read_data = read_reg;
//----------------------------------------------------------------
// Core instantiations.
//----------------------------------------------------------------
sha1 sha1(
// Clock and reset.
.clk(clk),
.reset_n(reset_n),
// Control.
.cs(sha1_cs),
.we(sha1_we),
// Data ports.
.address(sha1_address),
.write_data(sha1_write_data),
.read_data(sha1_read_data),
.error(sha1_error)
);
sha256 sha256(
// Clock and reset.
.clk(clk),
.reset_n(reset_n),
// Control.
.cs(sha256_cs),
.we(sha256_we),
// Data ports.
.address(sha256_address),
.write_data(sha256_write_data),
.read_data(sha256_read_data),
.error(sha256_error)
);
sha512 sha512(
// Clock and reset.
.clk(clk),
.reset_n(reset_n),
// Control.
.cs(sha512_cs),
.we(sha512_we),
// Data ports.
.address(sha512_address),
.write_data(sha512_write_data),
.read_data(sha512_read_data),
.error(sha512_error)
);
//----------------------------------------------------------------
// address_mux
//
// Combinational data mux that handles addressing between
// cores using the 32-bit memory like interface.
//----------------------------------------------------------------
always @*
begin : address_mux
// Default assignments.
sha1_cs = 0;
sha1_we = 0;
sha1_address = 8'h00;
sha1_write_data = 32'h00000000;
sha256_cs = 0;
sha256_we = 0;
sha256_address = 8'h00;
sha256_write_data = 32'h00000000;
sha512_cs = 0;
sha512_we = 0;
sha512_address = 8'h00;
sha512_write_data = 32'h00000000;
// address mux
case (address[13:8])
SHA1_ADDR_PREFIX:
begin
sha1_cs = 1;
sha1_we = we;
sha1_address = address[7:0];
sha1_write_data = write_data;
read_reg = sha1_read_data;
error_reg = sha1_error;
end
SHA256_ADDR_PREFIX:
begin
sha256_cs = 1;
sha256_we = we;
sha256_address = address[7:0];
sha256_write_data = write_data;
read_reg = sha256_read_data;
error_reg = sha256_error;
end
SHA512_ADDR_PREFIX:
begin
sha512_cs = 1;
sha512_we = we;
sha512_address = address[7:0];
sha512_write_data = write_data;
read_reg = sha512_read_data;
error_reg = sha512_error;
end
default:
begin
read_reg = 32'hZZZZ;
end
endcase
end // address_mux
endmodule
//======================================================================
// EOF core_selector.v
//======================================================================
|
