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authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-02-01 20:36:22 +0100
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-02-01 20:36:22 +0100
commit7e6657d37db9742d3e6e943b3f01d781a7aa3538 (patch)
tree36f11942acc20428f3e99fc33130c3a06e6004dc /rtl
parent4b354f59754a373b8a92d8895f486834a8f7f059 (diff)
Changed to Verilog 2001 interface. Added ports for Cryptech avalanche noise board. Fixed layout.
Diffstat (limited to 'rtl')
-rw-r--r--rtl/src/verilog/novena_baseline_top.v258
1 files changed, 135 insertions, 123 deletions
diff --git a/rtl/src/verilog/novena_baseline_top.v b/rtl/src/verilog/novena_baseline_top.v
index 890b8bc..d265e67 100644
--- a/rtl/src/verilog/novena_baseline_top.v
+++ b/rtl/src/verilog/novena_baseline_top.v
@@ -40,132 +40,144 @@
module novena_baseline_top
(
- gclk_p_pin, gclk_n_pin,
-
- eim_bclk, eim_cs0_n, eim_da,
- eim_lba_n, eim_wr_n,
- eim_oe_n, eim_wait_n,
-
- reset_mcu_b_pin,
- apoptosis_pin,
- led_pin
- );
-
- //
- // Top-Levl Ports
- //
- input wire gclk_p_pin; // general-purpose 50 MHz LVDS clock
- input wire gclk_n_pin; //
-
- input wire eim_bclk; // burst clock from cpu
- input wire eim_cs0_n; // chip select (active low)
- inout wire [15: 0] eim_da; // bi-directional address/data bus
- input wire eim_lba_n; // latch address signal (active low)
- input wire eim_wr_n; // write enable signal (active low)
- input wire eim_oe_n; // output enable signal (active low)
- output wire eim_wait_n; // wait signal (active low)
-
- input wire reset_mcu_b_pin; // this must be configured as input w/pullup
- // not to kill the cpu after configuration
- output wire apoptosis_pin; // not used, tied to 0
- output wire led_pin; // visual activity indicator
-
-
- //
- // Clock Manager
- //
-
- /* Clock manager is used to buffer BCLK and also generate SYS_CLK from GCLK. */
-
- wire sys_clk;
- wire sys_rst;
-
- wire eim_bclk_buf;
-
- novena_clkmgr clkmgr
- (
- .gclk_p (gclk_p_pin),
- .gclk_n (gclk_n_pin),
-
- .reset_mcu_b (reset_mcu_b_pin),
-
- .sys_clk (sys_clk),
- .sys_rst (sys_rst),
-
- .bclk_in (eim_bclk),
- .bclk_out (eim_bclk_buf)
- );
-
-
- //
- // EIM Arbiter
- //
-
- /* EIM arbiter handles EIM access and transfers it into `sys_clk' clock domain. */
-
- wire [13: 0] sys_eim_addr;
- wire sys_eim_wr;
- wire sys_eim_rd;
- wire [31: 0] sys_eim_dout;
- wire [31: 0] sys_eim_din;
-
- eim_arbiter eim
- (
- .eim_bclk (eim_bclk_buf),
- .eim_cs0_n (eim_cs0_n),
- .eim_da (eim_da),
- .eim_lba_n (eim_lba_n),
- .eim_wr_n (eim_wr_n),
- .eim_oe_n (eim_oe_n),
- .eim_wait_n (eim_wait_n),
-
- .sys_clk (sys_clk),
-
- .sys_addr (sys_eim_addr),
- .sys_wren (sys_eim_wr),
- .sys_data_out (sys_eim_dout),
- .sys_rden (sys_eim_rd),
- .sys_data_in (sys_eim_din)
- );
-
-
- //
- // Core Selector (MUX)
- //
-
- /* This multiplexor is used to map demo adder registers somewhere into EIM address space. */
-
- core_selector mux
- (
- .sys_clk (sys_clk),
- .sys_rst (sys_rst),
-
- .sys_eim_addr (sys_eim_addr),
- .sys_eim_wr (sys_eim_wr),
- .sys_eim_rd (sys_eim_rd),
-
- .sys_eim_dout (sys_eim_dout),
- .sys_eim_din (sys_eim_din)
+ // Differential input for 50 MHz general clock.
+ input wire gclk_p_pin,
+ input wire gclk_n_pin,
+
+ // Reset controlled by the CPU.
+ // this must be configured as input w/pullup
+ input wire reset_mcu_b_pin,
+
+ // Cryptech avalanche noise board input and LED outputs
+ input wire ct_avalanche_noise,
+ output wire [07 : 0] ct_avalanche_led,
+
+ // EIM interface
+ input wire eim_bclk, // EIM burst clock. Started by the CPU.
+ input wire eim_cs0_n, // Chip select (active low).
+ inout wire [15 : 0] eim_da, // Bidirectional address and data port.
+ input wire eim_lba_n, // Latch address signal (active low).
+ input wire eim_wr_n, // write enable signal (active low).
+ input wire eim_oe_n, // output enable signal (active low).
+ output wire eim_wait_n, // Data wait signal (active low).
+
+ // Novena utility ports
+ apoptosis_pin, // Hold low to not restart after config.
+ led_pin // LED on edge close to the FPGA.
);
- //
- // LED Driver
- //
- eim_indicator led
- (
- .sys_clk (sys_clk),
- .sys_rst (sys_rst),
- .eim_active (sys_eim_wr | sys_eim_rd),
- .led_out (led_pin)
- );
-
-
- //
- // Unused
- //
- assign apoptosis_pin = 1'b0;
-
+ //----------------------------------------------------------------
+ // Clock Manager
+ //
+ // Clock manager is used to buffer BCLK, generate SYS_CLK
+ // from GCLK and implement the reset logic.
+ //----------------------------------------------------------------
+ wire sys_clk;
+ wire sys_rst;
+ wire eim_bclk_buf;
+
+ novena_clkmgr clkmgr
+ (
+ .gclk_p(gclk_p_pin),
+ .gclk_n(gclk_n_pin),
+
+ .reset_mcu_b(reset_mcu_b_pin),
+
+ .sys_clk(sys_clk),
+ .sys_rst(sys_rst),
+
+ .bclk_in(eim_bclk),
+ .bclk_out(eim_bclk_buf)
+ );
+
+
+ //----------------------------------------------------------------
+ // EIM Arbiter
+ //
+ // EIM arbiter handles EIM access and transfers it into
+ // `sys_clk' clock domain.
+ //----------------------------------------------------------------
+ wire [13: 0] sys_eim_addr;
+ wire sys_eim_wr;
+ wire sys_eim_rd;
+ wire [31: 0] sys_eim_dout;
+ wire [31: 0] sys_eim_din;
+
+ eim_arbiter eim
+ (
+ .eim_bclk(eim_bclk_buf),
+ .eim_cs0_n (eim_cs0_n),
+ .eim_da(eim_da),
+ .eim_lba_n (eim_lba_n),
+ .eim_wr_n(eim_wr_n),
+ .eim_oe_n(eim_oe_n),
+ .eim_wait_n(eim_wait_n),
+
+ .sys_clk(sys_clk),
+
+ .sys_addr(sys_eim_addr),
+ .sys_wren(sys_eim_wr),
+ .sys_data_out(sys_eim_dout),
+ .sys_rden(sys_eim_rd),
+ .sys_data_in(sys_eim_din)
+ );
+
+
+ //----------------------------------------------------------------
+ // Core Selector (MUX)
+ //
+ // This multiplexer is used to map ore registers into
+ // EIM address space and select which core to send EIM read and
+ // write operations to.
+ //----------------------------------------------------------------
+ core_selector mux
+ (
+ .sys_clk(sys_clk),
+ .sys_rst(sys_rst),
+
+ .sys_eim_addr(sys_eim_addr),
+ .sys_eim_wr(sys_eim_wr),
+ .sys_eim_rd(sys_eim_rd),
+
+ .sys_eim_dout(sys_eim_dout),
+ .sys_eim_din(sys_eim_din)
+ );
+
+
+ //----------------------------------------------------------------
+ // LED Driver
+ //
+ // A simple utility LED driver that turns on the Novena
+ // board LED when the EIM interface is active.
+ //----------------------------------------------------------------
+ eim_indicator led
+ (
+ .sys_clk(sys_clk),
+ .sys_rst(sys_rst),
+ .eim_active(sys_eim_wr | sys_eim_rd),
+ .led_out(led_pin)
+ );
+
+
+ //----------------------------------------------------------------
+ // Cryptech Logic
+ //
+ // Logic specific to the Cryptech use of the Novena.
+ // Currently we just hard wire the LED outputs.
+ //----------------------------------------------------------------
+ assign ct_avalanche_led = 8'h55;
+
+
+ //----------------------------------------------------------------
+ // Novena Patch
+ //
+ // Patch logic to keep the Novena board happy.
+ // The apoptosis_pin pin must be kept low or the whole board
+ // (more exactly the CPU) will be reset after the FPGA has
+ // been configured.
+ //----------------------------------------------------------------
+ assign apoptosis_pin = 1'b0;
endmodule