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authorPaul Selkirk <pselkirk@isc.org>2015-03-17 13:49:37 +0100
committerPaul Selkirk <pselkirk@isc.org>2015-03-17 13:49:37 +0100
commit3c36fb89e99931bc8134f072b4bca7ca526ab513 (patch)
treeff4a817ca696639022bb622b9b65274226722025 /toolruns/quartus/terasic_c5g/coretest_hashes.sdc
parente61ac3e6db2b8e8f162f75213038130209107328 (diff)
Rearrange cores.
Diffstat (limited to 'toolruns/quartus/terasic_c5g/coretest_hashes.sdc')
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1 files changed, 0 insertions, 40 deletions
diff --git a/toolruns/quartus/terasic_c5g/coretest_hashes.sdc b/toolruns/quartus/terasic_c5g/coretest_hashes.sdc
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-#************************************************************
-# THIS IS A WIZARD-GENERATED FILE.
-#
-# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition
-#
-#************************************************************
-
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-
-
-# Clock constraints
-
-create_clock -name "clk" -period 20.000ns [get_ports {clk}]
-
-
-# Automatically constrain PLL and other generated clocks
-derive_pll_clocks -create_base_clocks
-
-# Automatically calculate clock uncertainty to jitter and other effects.
-derive_clock_uncertainty
-
-# tsu/th constraints
-
-# tco constraints
-
-# tpd constraints
-