Rearrange cores.

12 files changed, 429 insertions, 514 deletions

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..8b46186
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,5 @@
+c5_pin_model_dump.txt
+db
+incremental_db
+output_files
+*.qws
diff --git a/README.md b/README.md
index 894b602..42a3eab 100644
--- a/README.md
+++ b/README.md
@@ -1,14 +1,16 @@
-coretest_hashes
-===============
+platform/terasic_c5g
+====================
 
-The coretest system combined with cryptographic hash functions.
+Platform-specific files for the TerasIC C5G development board.
 
 ## Introduction ##
-This is a HW subsystem that includes the coretest module connected to a
-uart for external access and to hash function cores. The first version
-includes the SHA-1 and SHA-256 cores.
+This includes the Verilog top-level files and build systems for Terasic
+with a UART interface.
 
 ## Status ##
+***(2015-03-16)***
+Reorganized. Built using Altera Quarus 14.1.
+
 ***(2014-03-07)***
 Initial version. Build using Altera Quarus 13.1.
 
@@ -16,6 +18,3 @@ Initial version. Build using Altera Quarus 13.1.
 - 2847 ALMs and
 - 3665 registers
 - 86 MHz
-
-
-
diff --git a/src/rtl/coretest_hashes.v b/src/rtl/coretest_hashes.v
deleted file mode 100644
index 34208c5..0000000
--- a/src/rtl/coretest_hashes.v
+++ /dev/null
@@ -1,315 +0,0 @@
-//======================================================================
-//
-// coretest_hashes.v
-// -----------------
-// Top level wrapper that creates the Cryptech coretest system.
-// The wrapper contains instances of external interface, coretest
-// and the core to be tested. And if more than one core is
-// present the wrapper also includes address and data muxes.
-//
-//
-// Author: Joachim Strombergson
-// Copyright (c) 2014, SUNET
-// All rights reserved.
-// 
-// Redistribution and use in source and binary forms, with or 
-// without modification, are permitted provided that the following 
-// conditions are met: 
-// 
-// 1. Redistributions of source code must retain the above copyright 
-//    notice, this list of conditions and the following disclaimer. 
-// 
-// 2. Redistributions in binary form must reproduce the above copyright 
-//    notice, this list of conditions and the following disclaimer in 
-//    the documentation and/or other materials provided with the 
-//    distribution. 
-// 
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
-// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
-// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
-// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//======================================================================
-
-module coretest_hashes(
-                       input wire          clk,
-                       input wire          reset_n,
-                       
-                       // External interface.
-                       input wire          rxd,
-                       output wire         txd,
-                       
-                       output wire [7 : 0] debug
-                      );
-
-  
-  //----------------------------------------------------------------
-  // Internal constant and parameter definitions.
-  //----------------------------------------------------------------
-  parameter UART_ADDR_PREFIX   = 8'h00;
-  parameter SHA1_ADDR_PREFIX   = 8'h10;
-  parameter SHA256_ADDR_PREFIX = 8'h20;
-  parameter SHA512_ADDR_PREFIX = 8'h30;
-  
-  
-  //----------------------------------------------------------------
-  // Wires.
-  //----------------------------------------------------------------
-  // Coretest connections.
-  wire          coretest_reset_n;
-  wire          coretest_cs;
-  wire          coretest_we;
-  wire [15 : 0] coretest_address;
-  wire [31 : 0] coretest_write_data;
-  reg [31 : 0]  coretest_read_data;
-  reg           coretest_error;
-
-  // uart connections
-  wire          uart_rxd_syn;
-  wire [7 : 0]  uart_rxd_data;
-  wire          uart_rxd_ack;
-  wire          uart_txd_syn;
-  wire [7 : 0]  uart_txd_data;
-  wire          uart_txd_ack;
-  reg           uart_cs;
-  reg           uart_we;
-  reg [7 : 0]   uart_address;
-  reg [31 : 0]  uart_write_data;
-  wire [31 : 0] uart_read_data;
-  wire          uart_error;
-  wire [7 : 0]  uart_debug;
-
-  // sha1 connections.
-  reg           sha1_cs;
-  reg           sha1_we;
-  reg [7 : 0]   sha1_address;
-  reg [31 : 0]  sha1_write_data;
-  wire [31 : 0] sha1_read_data;
-  wire          sha1_error;
-  wire [7 : 0]  sha1_debug;
-
-  // sha256 connections.
-  reg           sha256_cs;
-  reg           sha256_we;
-  reg [7 : 0]   sha256_address;
-  reg [31 : 0]  sha256_write_data;
-  wire [31 : 0] sha256_read_data;
-  wire          sha256_error;
-  wire [7 : 0]  sha256_debug;
-
-  // sha512 connections.
-  reg           sha512_cs;
-  reg           sha512_we;
-  reg [7 : 0]   sha512_address;
-  reg [31 : 0]  sha512_write_data;
-  wire [31 : 0] sha512_read_data;
-  wire          sha512_error;
-  wire [7 : 0]  sha512_debug;
-  
-  
-  //----------------------------------------------------------------
-  // Concurrent assignment.
-  //----------------------------------------------------------------
-  assign debug = uart_debug;
-  
-  
-  //----------------------------------------------------------------
-  // Core instantiations.
-  //----------------------------------------------------------------
-  coretest coretest(
-                    .clk(clk),
-                    .reset_n(reset_n),
-                         
-                    .rx_syn(uart_rxd_syn),
-                    .rx_data(uart_rxd_data),
-                    .rx_ack(uart_rxd_ack),
-                    
-                    .tx_syn(uart_txd_syn),
-                    .tx_data(uart_txd_data),
-                    .tx_ack(uart_txd_ack),
-                    
-                    // Interface to the core being tested.
-                    .core_reset_n(coretest_reset_n),
-                    .core_cs(coretest_cs),
-                    .core_we(coretest_we),
-                    .core_address(coretest_address),
-                    .core_write_data(coretest_write_data),
-                    .core_read_data(coretest_read_data),
-                    .core_error(coretest_error)
-                   );
-
-
-  uart uart(
-            .clk(clk),
-            .reset_n(reset_n),
-            
-            .rxd(rxd),
-            .txd(txd),
-
-            .rxd_syn(uart_rxd_syn),
-            .rxd_data(uart_rxd_data),
-            .rxd_ack(uart_rxd_ack),
-
-            .txd_syn(uart_txd_syn),
-            .txd_data(uart_txd_data),
-            .txd_ack(uart_txd_ack),
-            
-            .cs(uart_cs),
-            .we(uart_we),
-            .address(uart_address),
-            .write_data(uart_write_data),
-            .read_data(uart_read_data),
-            .error(uart_error),
-
-            .debug(uart_debug)
-           );
-
-  
-  sha1 sha1(
-            // Clock and reset.
-            .clk(clk),
-            .reset_n(reset_n),
-            
-            // Control.
-            .cs(sha1_cs),
-            .we(sha1_we),
-              
-            // Data ports.
-            .address(sha1_address),
-            .write_data(sha1_write_data),
-            .read_data(sha1_read_data),
-            .error(sha1_error)
-           );
-
-  
-  sha256 sha256(
-                // Clock and reset.
-                .clk(clk),
-                .reset_n(reset_n),
-                
-                // Control.
-                .cs(sha256_cs),
-                .we(sha256_we),
-              
-                // Data ports.
-                .address(sha256_address),
-                .write_data(sha256_write_data),
-                .read_data(sha256_read_data),
-                .error(sha256_error)
-               );
-
-  
-  sha512 sha512(
-                // Clock and reset.
-                .clk(clk),
-                .reset_n(reset_n),
-
-                // Control.
-                .cs(sha512_cs),
-                .we(sha512_we),
-
-                // Data ports.
-                .address(sha512_address),
-                .write_data(sha512_write_data),
-                .read_data(sha512_read_data),
-                .error(sha512_error)
-               );
-
-
-  //----------------------------------------------------------------
-  // address_mux
-  //
-  // Combinational data mux that handles addressing between
-  // cores using the 32-bit memory like interface.
-  //----------------------------------------------------------------
-  always @*
-    begin : address_mux
-      // Default assignments.
-      coretest_read_data = 32'h00000000;
-      coretest_error     = 0;
-
-      uart_cs            = 0;
-      uart_we            = 0;
-      uart_address       = 8'h00;
-      uart_write_data    = 32'h00000000;
-
-      sha1_cs            = 0;
-      sha1_we            = 0;
-      sha1_address       = 8'h00;
-      sha1_write_data    = 32'h00000000;
-
-      sha256_cs          = 0;
-      sha256_we          = 0;
-      sha256_address     = 8'h00;
-      sha256_write_data  = 32'h00000000;
-
-      sha512_cs          = 0;
-      sha512_we          = 0;
-      sha512_address     = 8'h00;
-      sha512_write_data  = 32'h00000000;
-
-
-      case (coretest_address[15 : 8])
-        UART_ADDR_PREFIX:
-          begin
-            uart_cs            = coretest_cs;
-            uart_we            = coretest_we;
-            uart_address       = coretest_address[7 : 0];
-            uart_write_data    = coretest_write_data;
-            coretest_read_data = uart_read_data;
-            coretest_error     = uart_error;
-          end
-
-        
-        SHA1_ADDR_PREFIX:
-          begin
-            sha1_cs            = coretest_cs;
-            sha1_we            = coretest_we;
-            sha1_address       = coretest_address[7 : 0];
-            sha1_write_data    = coretest_write_data;
-            coretest_read_data = sha1_read_data;
-            coretest_error     = sha1_error;
-          end
-
-        
-        SHA256_ADDR_PREFIX:
-          begin
-            sha256_cs          = coretest_cs;
-            sha256_we          = coretest_we;
-            sha256_address     = coretest_address[7 : 0];
-            sha256_write_data  = coretest_write_data;
-            coretest_read_data = sha256_read_data;
-            coretest_error     = sha256_error;
-          end
-
-
-        SHA512_ADDR_PREFIX:
-          begin
-            sha512_cs          = coretest_cs;
-            sha512_we          = coretest_we;
-            sha512_address     = coretest_address[7 : 0];
-            sha512_write_data  = coretest_write_data;
-            coretest_read_data = sha512_read_data;
-            coretest_error     = sha512_error;
-          end
-        
-        
-        default:
-          begin
-          end
-      endcase // case (coretest_address[15 : 8])
-    end // address_mux
-  
-endmodule // coretest_hashes
-
-//======================================================================
-// EOF coretest_hashes.v
-//======================================================================
diff --git a/src/sw/hash_tester.py b/sw/hash_tester.py
index d91d906..d91d906 100755
--- a/src/sw/hash_tester.py
+++ b/sw/hash_tester.py
diff --git a/terasic_regs.v b/terasic_regs.v
new file mode 100644
index 0000000..8d7d92c
--- /dev/null
+++ b/terasic_regs.v
@@ -0,0 +1,129 @@
+//======================================================================
+//
+// terasic_regs.v
+// -------------
+// Global registers for the Cryptech Terasic FPGA framework.
+//
+//
+// Author: Pavel Shatov
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+`timescale 1ns / 1ps
+
+module board_regs
+  (
+   input wire           clk,
+   input wire           rst,
+
+   input wire           cs,
+   input wire           we,
+
+   input wire [ 7 : 0]  address,
+   input wire [31 : 0]  write_data,
+   output wire [31 : 0] read_data
+   );
+
+
+   //----------------------------------------------------------------
+   // Internal constant and parameter definitions.
+   //----------------------------------------------------------------
+   // API addresses.
+   localparam ADDR_CORE_NAME0   = 8'h00;
+   localparam ADDR_CORE_NAME1   = 8'h01;
+   localparam ADDR_CORE_VERSION = 8'h02;
+   localparam ADDR_DUMMY_REG    = 8'hFF;    // general-purpose register
+
+   // Core ID constants.
+   localparam CORE_NAME0   = 32'h54433547;  // "TC5G"
+   localparam CORE_NAME1   = 32'h20202020;  // "    "
+   localparam CORE_VERSION = 32'h302e3130;  // "0.10"
+
+
+   //----------------------------------------------------------------
+   // Wires.
+   //----------------------------------------------------------------
+   reg [31: 0]          tmp_read_data;
+
+   // dummy register to check that you can actually write something
+   reg [31: 0] 		reg_dummy;
+
+   
+   //----------------------------------------------------------------
+   // Concurrent connectivity for ports etc.
+   //----------------------------------------------------------------
+   assign read_data = tmp_read_data;
+   
+
+   //----------------------------------------------------------------
+   // Access Handler
+   //----------------------------------------------------------------
+   always @(posedge clk)
+     //
+     if (rst)
+       reg_dummy <= {32{1'b0}};
+     else if (cs) begin
+        //
+        if (we) begin
+           //
+           // WRITE handler
+           //
+           case (address)
+             ADDR_DUMMY_REG:
+               reg_dummy        <= write_data;
+           endcase
+           //
+        end else begin
+           //
+           // READ handler
+           //
+           case (address)
+             ADDR_CORE_NAME0:
+               tmp_read_data <= CORE_NAME0;
+             ADDR_CORE_NAME1:
+               tmp_read_data <= CORE_NAME1;
+             ADDR_CORE_VERSION:
+               tmp_read_data <= CORE_VERSION;
+             ADDR_DUMMY_REG:
+               tmp_read_data <= reg_dummy;
+             //
+             default:
+               tmp_read_data <= {32{1'b0}};  // read non-existent locations as zeroes
+           endcase
+           //
+        end
+        //
+     end
+
+endmodule
+
+//======================================================================
+// EOF terasic_regs.v
+//======================================================================
diff --git a/terasic_top.qpf b/terasic_top.qpf
new file mode 100644
index 0000000..6f25a8f
--- /dev/null
+++ b/terasic_top.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
+# Date created = 16:43:44  February 25, 2015
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "14.1"
+DATE = "16:43:44  February 25, 2015"
+
+# Revisions
+
+PROJECT_REVISION = "terasic_top"
diff --git a/toolruns/quartus/terasic_c5g/coretest_hashes.qsf b/terasic_top.qsf
index 92ba7f8..5cbe5c9 100644
--- a/toolruns/quartus/terasic_c5g/coretest_hashes.qsf
+++ b/terasic_top.qsf
@@ -1,89 +1,101 @@
-# -------------------------------------------------------------------------- #

-#

-# Copyright (C) 1991-2014 Altera Corporation

-# Your use of Altera Corporation's design tools, logic functions 

-# and other software and tools, and its AMPP partner logic 

-# functions, and any output files from any of the foregoing 

-# (including device programming or simulation files), and any 

-# associated documentation or information are expressly subject 

-# to the terms and conditions of the Altera Program License 

-# Subscription Agreement, Altera MegaCore Function License 

-# Agreement, or other applicable license agreement, including, 

-# without limitation, that your use is for the sole purpose of 

-# programming logic devices manufactured by Altera and sold by 

-# Altera or its authorized distributors.  Please refer to the 

-# applicable agreement for further details.

-#

-# -------------------------------------------------------------------------- #

-#

-# Quartus II 64-Bit

-# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition

-# Date created = 08:59:21  March 17, 2014

-#

-# -------------------------------------------------------------------------- #

-#

-# Notes:

-#

-# 1) The default values for assignments are stored in the file:

-#		coretest_hashes_assignment_defaults.qdf

-#    If this file doesn't exist, see file:

-#		assignment_defaults.qdf

-#

-# 2) Altera recommends that you do not modify this file. This

-#    file is updated automatically by the Quartus II software

-#    and any changes you make may be lost or overwritten.

-#

-# -------------------------------------------------------------------------- #

-

-

-set_global_assignment -name FAMILY "Cyclone V"

-set_global_assignment -name DEVICE 5CGXFC5C6F27C7

-set_global_assignment -name TOP_LEVEL_ENTITY coretest_hashes

-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1

-set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:59:21  MARCH 17, 2014"

-set_global_assignment -name LAST_QUARTUS_VERSION 13.1

-set_global_assignment -name VERILOG_FILE ../../../../uart/src/rtl/uart_core.v

-set_global_assignment -name VERILOG_FILE ../../../../uart/src/rtl/uart.v

-set_global_assignment -name VERILOG_FILE ../../../../sha256/src/rtl/sha256_w_mem.v

-set_global_assignment -name VERILOG_FILE ../../../../sha256/src/rtl/sha256_k_constants.v

-set_global_assignment -name VERILOG_FILE ../../../../sha256/src/rtl/sha256_core.v

-set_global_assignment -name VERILOG_FILE ../../../../sha256/src/rtl/sha256.v

-set_global_assignment -name VERILOG_FILE ../../../../sha1/src/rtl/sha1_w_mem.v

-set_global_assignment -name VERILOG_FILE ../../../../sha1/src/rtl/sha1_core.v

-set_global_assignment -name VERILOG_FILE ../../../../sha1/src/rtl/sha1.v

-set_global_assignment -name VERILOG_FILE ../../../../coretest/src/rtl/coretest.v

-set_global_assignment -name VERILOG_FILE ../../../src/rtl/coretest_hashes.v

-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

-set_location_assignment PIN_R20 -to clk

-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk

-set_location_assignment PIN_P11 -to reset_n

-set_instance_assignment -name IO_STANDARD "1.2 V" -to reset_n

-set_location_assignment PIN_M9 -to rxd

-set_instance_assignment -name IO_STANDARD "2.5 V" -to rxd

-set_location_assignment PIN_L9 -to txd

-set_instance_assignment -name IO_STANDARD "2.5 V" -to txd

-set_location_assignment PIN_L7 -to debug[0]

-set_location_assignment PIN_K6 -to debug[1]

-set_location_assignment PIN_D8 -to debug[2]

-set_location_assignment PIN_E9 -to debug[3]

-set_location_assignment PIN_A5 -to debug[4]

-set_location_assignment PIN_B6 -to debug[5]

-set_location_assignment PIN_H8 -to debug[6]

-set_location_assignment PIN_H9 -to debug[7]

-set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[1]

-set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[2]

-set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[3]

-set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[4]

-set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[5]

-set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[6]

-set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[7]

-set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[0]

-

-set_global_assignment -name SDC_FILE coretest_hashes.sdc

+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
+# Date created = 16:43:44  February 25, 2015
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		terasic_top_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CGXFC5C6F27C7
+set_global_assignment -name TOP_LEVEL_ENTITY terasic_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:43:44  FEBRUARY 25, 2015"
+set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_location_assignment PIN_R20 -to clk
+set_location_assignment PIN_P11 -to reset_n
+set_location_assignment PIN_M9 -to rxd
+set_location_assignment PIN_L9 -to txd
+set_location_assignment PIN_L7 -to debug[0]
+set_location_assignment PIN_K6 -to debug[1]
+set_location_assignment PIN_D8 -to debug[2]
+set_location_assignment PIN_E9 -to debug[3]
+set_location_assignment PIN_A5 -to debug[4]
+set_location_assignment PIN_B6 -to debug[5]
+set_location_assignment PIN_H8 -to debug[6]
+set_location_assignment PIN_H9 -to debug[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk
+set_instance_assignment -name IO_STANDARD "1.2 V" -to reset_n
+set_instance_assignment -name IO_STANDARD "2.5 V" -to txd
+set_instance_assignment -name IO_STANDARD "2.5 V" -to rxd
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[7]
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VERILOG_FILE ../../hash/sha512/src/rtl/sha512_w_mem.v
+set_global_assignment -name VERILOG_FILE ../../hash/sha512/src/rtl/sha512_k_constants.v
+set_global_assignment -name VERILOG_FILE ../../hash/sha512/src/rtl/sha512_h_constants.v
+set_global_assignment -name VERILOG_FILE ../../hash/sha512/src/rtl/sha512_core.v
+set_global_assignment -name VERILOG_FILE ../../hash/sha512/src/rtl/sha512.v
+set_global_assignment -name VERILOG_FILE ../../hash/sha256/src/rtl/sha256_w_mem.v
+set_global_assignment -name VERILOG_FILE ../../hash/sha256/src/rtl/sha256_k_constants.v
+set_global_assignment -name VERILOG_FILE ../../hash/sha256/src/rtl/sha256_core.v
+set_global_assignment -name VERILOG_FILE ../../hash/sha256/src/rtl/sha256.v
+set_global_assignment -name VERILOG_FILE ../../hash/sha1/src/rtl/sha1_w_mem.v
+set_global_assignment -name VERILOG_FILE ../../hash/sha1/src/rtl/sha1_core.v
+set_global_assignment -name VERILOG_FILE ../../hash/sha1/src/rtl/sha1.v
+set_global_assignment -name VERILOG_FILE ../../comm/coretest/src/rtl/coretest.v
+set_global_assignment -name VERILOG_FILE ../../comm/uart/src/rtl/uart_core.v
+set_global_assignment -name VERILOG_FILE ../../comm/uart/src/rtl/uart_regs.v
+set_global_assignment -name VERILOG_FILE ../common/core_selector/src/rtl/rng_selector.v
+set_global_assignment -name VERILOG_FILE ../common/core_selector/src/rtl/hash_selector.v
+set_global_assignment -name VERILOG_FILE ../common/core_selector/src/rtl/cipher_selector.v
+set_global_assignment -name VERILOG_FILE ../common/core_selector/src/rtl/global_selector.v
+set_global_assignment -name VERILOG_FILE ../common/core_selector/src/rtl/core_selector.v
+set_global_assignment -name VERILOG_FILE terasic_regs.v
+set_global_assignment -name VERILOG_FILE terasic_top.v
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/toolruns/quartus/terasic_c5g/coretest_hashes.sdc b/terasic_top.sdc
index 93e1282..93e1282 100644
--- a/toolruns/quartus/terasic_c5g/coretest_hashes.sdc
+++ b/terasic_top.sdc
diff --git a/terasic_top.v b/terasic_top.v
new file mode 100644
index 0000000..5357e71
--- /dev/null
+++ b/terasic_top.v
@@ -0,0 +1,156 @@
+//======================================================================
+//
+// terasic_top.v
+// -------------
+// Top module for the Cryptech FPGA framework.
+//
+//
+// Author: Pavel Shatov
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module terasic_top
+  (
+   input wire 	       clk,
+   input wire 	       reset_n,
+  
+   // External interface.
+   input wire 	       rxd,
+   output wire 	       txd,
+  
+   output wire [7 : 0] debug
+   );
+
+   //----------------------------------------------------------------
+   // UART Interface
+   //
+   // UART subsystem handles all data transfer to/from host via serial.
+   //----------------------------------------------------------------
+
+   // UART configuration (set in uart_regs.v)
+   reg [15 : 0] 	bit_rate;
+   reg [3 : 0] 		data_bits;
+   reg [1 : 0] 		stop_bits;
+
+   // UART connections
+   wire 		uart_rxd_syn;
+   wire [7 : 0] 	uart_rxd_data;
+   wire 		uart_rxd_ack;
+   wire 		uart_txd_syn;
+   wire [7 : 0] 	uart_txd_data;
+   wire 		uart_txd_ack;
+
+   uart_core uart_core
+     (
+      .clk(clk),
+      .reset_n(reset_n),
+
+      // Configuration parameters
+      .bit_rate(bit_rate),
+      .data_bits(data_bits),
+      .stop_bits(stop_bits),
+
+      // External data interface
+      .rxd(rxd),
+      .txd(txd),
+
+      // Internal receive interface.
+      .rxd_syn(uart_rxd_syn),
+      .rxd_data(uart_rxd_data),
+      .rxd_ack(uart_rxd_ack),
+      
+      // Internal transmit interface.
+      .txd_syn(uart_txd_syn),
+      .txd_data(uart_txd_data),
+      .txd_ack(uart_txd_ack)
+      );
+
+
+   //----------------------------------------------------------------
+   // Coretest interface
+   //
+   // Coretest parses the input datastream into a read/write command,
+   // and marshalls the response into an output datastream.
+   // ----------------------------------------------------------------
+
+   // Coretest connections.
+   wire 		coretest_reset_n;
+   wire 		coretest_cs;
+   wire 		coretest_we;
+   wire [15 : 0] 	coretest_address;
+   wire [31 : 0] 	coretest_write_data;
+   wire [31 : 0] 	coretest_read_data;
+
+   coretest coretest
+     (
+      .clk(clk),
+      .reset_n(reset_n),
+      
+      // Interface to communication core
+      .rx_syn(uart_rxd_syn),
+      .rx_data(uart_rxd_data),
+      .rx_ack(uart_rxd_ack),
+      
+      .tx_syn(uart_txd_syn),
+      .tx_data(uart_txd_data),
+      .tx_ack(uart_txd_ack),
+      
+      // Interface to the core being tested.
+      .core_reset_n(coretest_reset_n),
+      .core_cs(coretest_cs),
+      .core_we(coretest_we),
+      .core_address(coretest_address),
+      .core_write_data(coretest_write_data),
+      .core_read_data(coretest_read_data)
+      );
+
+
+   //----------------------------------------------------------------
+   // Core Selector
+   //
+   // This multiplexer is used to map different types of cores, such as
+   // hashes, RNGs and ciphers to different regions (segments) of memory.
+   //----------------------------------------------------------------
+
+   core_selector cores
+     (
+      .sys_clk(clk),
+      .sys_rst(!reset_n),
+
+      .sys_eim_addr({coretest_address[15:13], 1'b0, coretest_address[12:0]}),
+      .sys_eim_wr(coretest_cs & coretest_we),
+      .sys_eim_rd(coretest_cs & ~coretest_we),
+
+      .sys_write_data(coretest_write_data),
+      .sys_read_data(coretest_read_data)
+      );  
+
+
+endmodule
diff --git a/toolruns/Makefile b/toolruns/Makefile
deleted file mode 100755
index fcccaa9..0000000
--- a/toolruns/Makefile
+++ /dev/null
@@ -1,72 +0,0 @@
-#===================================================================
-#
-# Makefile
-# --------
-# Makefile for building coretest_hashes simulations.
-#
-#
-# Author: Joachim Strombergson
-# Copyright (c) 2014, SUNET
-# All rights reserved.
-# 
-# Redistribution and use in source and binary forms, with or 
-# without modification, are permitted provided that the following 
-# conditions are met: 
-# 
-# 1. Redistributions of source code must retain the above copyright 
-#    notice, this list of conditions and the following disclaimer. 
-# 
-# 2. Redistributions in binary form must reproduce the above copyright 
-#    notice, this list of conditions and the following disclaimer in 
-#    the documentation and/or other materials provided with the 
-#    distribution. 
-# 
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
-# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
-# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
-# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-#===================================================================
-
-CORETEST_HASHES_SRC=../src/rtl/coretest_hashes.v
-
-CORETEST_SRC=../../coretest/src/rtl/coretest.v
-
-UART_SRC=../../uart/src/rtl/uart.v ../../uart/src/rtl/uart_core.v
-
-SHA1_SRC=../../sha1/src/rtl/sha1.v ../../sha1/src/rtl/sha1_core.v  ../../sha1/src/rtl/sha1_w_mem.v
-
-SHA256_SRC=../../sha256/src/rtl/sha256.v ../../sha256/src/rtl/sha256_core.v  ../../sha256/src/rtl/sha256_w_mem.v ../../sha256/src/rtl/sha256_k_constants.v
-
-CC=iverilog
-
-all: coretest_hashes
-
-
-coretest_hashes: $(CORETEST_HASHES_SRC) $(CORETEST_SRC) $(UART_SRC) $(SHA1_SRC) $(SHA256_SRC)
-	$(CC) -o coretest_hashes.sim  $(CORETEST_HASHES_SRC) $(CORETEST_SRC) $(UART_SRC) $(SHA1_SRC) $(SHA256_SRC)
-
-
-clean:
-	rm -f coretest_hashes.sim
-
-
-help:
-	@echo "Supported targets:"
-	@echo "------------------"
-	@echo "all:                 Build all targets."
-	@echo "coretest_hashes:     Build the coretest hashes target."
-	@echo "clean:               Delete all built files."
-
-#===================================================================
-# EOF Makefile
-#===================================================================
-
diff --git a/toolruns/quartus/terasic_c5g/coretest_hashes.qpf b/toolruns/quartus/terasic_c5g/coretest_hashes.qpf
deleted file mode 100644
index 6542ebb..0000000
--- a/toolruns/quartus/terasic_c5g/coretest_hashes.qpf
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #

-#

-# Copyright (C) 1991-2014 Altera Corporation

-# Your use of Altera Corporation's design tools, logic functions 

-# and other software and tools, and its AMPP partner logic 

-# functions, and any output files from any of the foregoing 

-# (including device programming or simulation files), and any 

-# associated documentation or information are expressly subject 

-# to the terms and conditions of the Altera Program License 

-# Subscription Agreement, Altera MegaCore Function License 

-# Agreement, or other applicable license agreement, including, 

-# without limitation, that your use is for the sole purpose of 

-# programming logic devices manufactured by Altera and sold by 

-# Altera or its authorized distributors.  Please refer to the 

-# applicable agreement for further details.

-#

-# -------------------------------------------------------------------------- #

-#

-# Quartus II 64-Bit

-# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition

-# Date created = 08:59:21  March 17, 2014

-#

-# -------------------------------------------------------------------------- #

-

-QUARTUS_VERSION = "13.1"

-DATE = "08:59:21  March 17, 2014"

-

-# Revisions

-

-PROJECT_REVISION = "coretest_hashes"

diff --git a/toolruns/quartus/terasic_c5g/cryptech_pre_build_image/coretest_hashes.sof b/toolruns/quartus/terasic_c5g/cryptech_pre_build_image/coretest_hashes.sof
deleted file mode 100644
index d223599..0000000
--- a/toolruns/quartus/terasic_c5g/cryptech_pre_build_image/coretest_hashes.sof
+++ /dev/null