Rearrange cores.

5 files changed, 0 insertions, 231 deletions

diff --git a/toolruns/Makefile b/toolruns/Makefile
deleted file mode 100755
index fcccaa9..0000000
--- a/toolruns/Makefile
+++ /dev/null
@@ -1,72 +0,0 @@
-#===================================================================
-#
-# Makefile
-# --------
-# Makefile for building coretest_hashes simulations.
-#
-#
-# Author: Joachim Strombergson
-# Copyright (c) 2014, SUNET
-# All rights reserved.
-# 
-# Redistribution and use in source and binary forms, with or 
-# without modification, are permitted provided that the following 
-# conditions are met: 
-# 
-# 1. Redistributions of source code must retain the above copyright 
-#    notice, this list of conditions and the following disclaimer. 
-# 
-# 2. Redistributions in binary form must reproduce the above copyright 
-#    notice, this list of conditions and the following disclaimer in 
-#    the documentation and/or other materials provided with the 
-#    distribution. 
-# 
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
-# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
-# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
-# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-#===================================================================
-
-CORETEST_HASHES_SRC=../src/rtl/coretest_hashes.v
-
-CORETEST_SRC=../../coretest/src/rtl/coretest.v
-
-UART_SRC=../../uart/src/rtl/uart.v ../../uart/src/rtl/uart_core.v
-
-SHA1_SRC=../../sha1/src/rtl/sha1.v ../../sha1/src/rtl/sha1_core.v  ../../sha1/src/rtl/sha1_w_mem.v
-
-SHA256_SRC=../../sha256/src/rtl/sha256.v ../../sha256/src/rtl/sha256_core.v  ../../sha256/src/rtl/sha256_w_mem.v ../../sha256/src/rtl/sha256_k_constants.v
-
-CC=iverilog
-
-all: coretest_hashes
-
-
-coretest_hashes: $(CORETEST_HASHES_SRC) $(CORETEST_SRC) $(UART_SRC) $(SHA1_SRC) $(SHA256_SRC)
-	$(CC) -o coretest_hashes.sim  $(CORETEST_HASHES_SRC) $(CORETEST_SRC) $(UART_SRC) $(SHA1_SRC) $(SHA256_SRC)
-
-
-clean:
-	rm -f coretest_hashes.sim
-
-
-help:
-	@echo "Supported targets:"
-	@echo "------------------"
-	@echo "all:                 Build all targets."
-	@echo "coretest_hashes:     Build the coretest hashes target."
-	@echo "clean:               Delete all built files."
-
-#===================================================================
-# EOF Makefile
-#===================================================================
-
diff --git a/toolruns/quartus/terasic_c5g/coretest_hashes.qpf b/toolruns/quartus/terasic_c5g/coretest_hashes.qpf
deleted file mode 100644
index 6542ebb..0000000
--- a/toolruns/quartus/terasic_c5g/coretest_hashes.qpf
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #

-#

-# Copyright (C) 1991-2014 Altera Corporation

-# Your use of Altera Corporation's design tools, logic functions 

-# and other software and tools, and its AMPP partner logic 

-# functions, and any output files from any of the foregoing 

-# (including device programming or simulation files), and any 

-# associated documentation or information are expressly subject 

-# to the terms and conditions of the Altera Program License 

-# Subscription Agreement, Altera MegaCore Function License 

-# Agreement, or other applicable license agreement, including, 

-# without limitation, that your use is for the sole purpose of 

-# programming logic devices manufactured by Altera and sold by 

-# Altera or its authorized distributors.  Please refer to the 

-# applicable agreement for further details.

-#

-# -------------------------------------------------------------------------- #

-#

-# Quartus II 64-Bit

-# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition

-# Date created = 08:59:21  March 17, 2014

-#

-# -------------------------------------------------------------------------- #

-

-QUARTUS_VERSION = "13.1"

-DATE = "08:59:21  March 17, 2014"

-

-# Revisions

-

-PROJECT_REVISION = "coretest_hashes"

diff --git a/toolruns/quartus/terasic_c5g/coretest_hashes.qsf b/toolruns/quartus/terasic_c5g/coretest_hashes.qsf
deleted file mode 100644
index 92ba7f8..0000000
--- a/toolruns/quartus/terasic_c5g/coretest_hashes.qsf
+++ /dev/null
@@ -1,89 +0,0 @@
-# -------------------------------------------------------------------------- #

-#

-# Copyright (C) 1991-2014 Altera Corporation

-# Your use of Altera Corporation's design tools, logic functions 

-# and other software and tools, and its AMPP partner logic 

-# functions, and any output files from any of the foregoing 

-# (including device programming or simulation files), and any 

-# associated documentation or information are expressly subject 

-# to the terms and conditions of the Altera Program License 

-# Subscription Agreement, Altera MegaCore Function License 

-# Agreement, or other applicable license agreement, including, 

-# without limitation, that your use is for the sole purpose of 

-# programming logic devices manufactured by Altera and sold by 

-# Altera or its authorized distributors.  Please refer to the 

-# applicable agreement for further details.

-#

-# -------------------------------------------------------------------------- #

-#

-# Quartus II 64-Bit

-# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition

-# Date created = 08:59:21  March 17, 2014

-#

-# -------------------------------------------------------------------------- #

-#

-# Notes:

-#

-# 1) The default values for assignments are stored in the file:

-#		coretest_hashes_assignment_defaults.qdf

-#    If this file doesn't exist, see file:

-#		assignment_defaults.qdf

-#

-# 2) Altera recommends that you do not modify this file. This

-#    file is updated automatically by the Quartus II software

-#    and any changes you make may be lost or overwritten.

-#

-# -------------------------------------------------------------------------- #

-

-

-set_global_assignment -name FAMILY "Cyclone V"

-set_global_assignment -name DEVICE 5CGXFC5C6F27C7

-set_global_assignment -name TOP_LEVEL_ENTITY coretest_hashes

-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1

-set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:59:21  MARCH 17, 2014"

-set_global_assignment -name LAST_QUARTUS_VERSION 13.1

-set_global_assignment -name VERILOG_FILE ../../../../uart/src/rtl/uart_core.v

-set_global_assignment -name VERILOG_FILE ../../../../uart/src/rtl/uart.v

-set_global_assignment -name VERILOG_FILE ../../../../sha256/src/rtl/sha256_w_mem.v

-set_global_assignment -name VERILOG_FILE ../../../../sha256/src/rtl/sha256_k_constants.v

-set_global_assignment -name VERILOG_FILE ../../../../sha256/src/rtl/sha256_core.v

-set_global_assignment -name VERILOG_FILE ../../../../sha256/src/rtl/sha256.v

-set_global_assignment -name VERILOG_FILE ../../../../sha1/src/rtl/sha1_w_mem.v

-set_global_assignment -name VERILOG_FILE ../../../../sha1/src/rtl/sha1_core.v

-set_global_assignment -name VERILOG_FILE ../../../../sha1/src/rtl/sha1.v

-set_global_assignment -name VERILOG_FILE ../../../../coretest/src/rtl/coretest.v

-set_global_assignment -name VERILOG_FILE ../../../src/rtl/coretest_hashes.v

-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

-set_location_assignment PIN_R20 -to clk

-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk

-set_location_assignment PIN_P11 -to reset_n

-set_instance_assignment -name IO_STANDARD "1.2 V" -to reset_n

-set_location_assignment PIN_M9 -to rxd

-set_instance_assignment -name IO_STANDARD "2.5 V" -to rxd

-set_location_assignment PIN_L9 -to txd

-set_instance_assignment -name IO_STANDARD "2.5 V" -to txd

-set_location_assignment PIN_L7 -to debug[0]

-set_location_assignment PIN_K6 -to debug[1]

-set_location_assignment PIN_D8 -to debug[2]

-set_location_assignment PIN_E9 -to debug[3]

-set_location_assignment PIN_A5 -to debug[4]

-set_location_assignment PIN_B6 -to debug[5]

-set_location_assignment PIN_H8 -to debug[6]

-set_location_assignment PIN_H9 -to debug[7]

-set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[1]

-set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[2]

-set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[3]

-set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[4]

-set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[5]

-set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[6]

-set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[7]

-set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[0]

-

-set_global_assignment -name SDC_FILE coretest_hashes.sdc

-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/toolruns/quartus/terasic_c5g/coretest_hashes.sdc b/toolruns/quartus/terasic_c5g/coretest_hashes.sdc
deleted file mode 100644
index 93e1282..0000000
--- a/toolruns/quartus/terasic_c5g/coretest_hashes.sdc
+++ /dev/null
@@ -1,40 +0,0 @@
-#************************************************************

-# THIS IS A WIZARD-GENERATED FILE.                           

-#

-# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition

-#

-#************************************************************

-

-# Copyright (C) 1991-2014 Altera Corporation

-# Your use of Altera Corporation's design tools, logic functions 

-# and other software and tools, and its AMPP partner logic 

-# functions, and any output files from any of the foregoing 

-# (including device programming or simulation files), and any 

-# associated documentation or information are expressly subject 

-# to the terms and conditions of the Altera Program License 

-# Subscription Agreement, Altera MegaCore Function License 

-# Agreement, or other applicable license agreement, including, 

-# without limitation, that your use is for the sole purpose of 

-# programming logic devices manufactured by Altera and sold by 

-# Altera or its authorized distributors.  Please refer to the 

-# applicable agreement for further details.

-

-

-

-# Clock constraints

-

-create_clock -name "clk" -period 20.000ns [get_ports {clk}]

-

-

-# Automatically constrain PLL and other generated clocks

-derive_pll_clocks -create_base_clocks

-

-# Automatically calculate clock uncertainty to jitter and other effects.

-derive_clock_uncertainty

-

-# tsu/th constraints

-

-# tco constraints

-

-# tpd constraints

-

diff --git a/toolruns/quartus/terasic_c5g/cryptech_pre_build_image/coretest_hashes.sof b/toolruns/quartus/terasic_c5g/cryptech_pre_build_image/coretest_hashes.sof
deleted file mode 100644
index d223599..0000000
--- a/toolruns/quartus/terasic_c5g/cryptech_pre_build_image/coretest_hashes.sof
+++ /dev/null