diff options
| author | Paul Selkirk <paul@psgd.org> | 2015-11-18 17:23:40 -0500 |
|---|---|---|
| committer | Paul Selkirk <paul@psgd.org> | 2015-11-18 17:23:40 -0500 |
| commit | 81286a692a3edade788c6d42beec1a7c8e5e07c9 (patch) | |
| tree | 680d461124463664c223e8013bf37df1fdef03e0 /common | |
| parent | b07ab1c2ff5e8f79d994455ccb68d7afccc53b26 (diff) | |
Move novena_clkmgr IBUFGDS to clkmgr_dcm, to put the Xilinx-specific primitives in one place.
Diffstat (limited to 'common')
| -rw-r--r-- | common/rtl/clkmgr_dcm.v | 19 | ||||
| -rw-r--r-- | common/rtl/novena_clkmgr.v | 21 |
2 files changed, 24 insertions, 16 deletions
diff --git a/common/rtl/clkmgr_dcm.v b/common/rtl/clkmgr_dcm.v index 7c851f1..141863e 100644 --- a/common/rtl/clkmgr_dcm.v +++ b/common/rtl/clkmgr_dcm.v @@ -38,9 +38,11 @@ module clkmgr_dcm ( - input wire clk_in, + input wire clk_in_p, + input wire clk_in_n, input wire reset_in, + output wire gclk_out, output wire gclk_missing_out, output wire clk_out, @@ -56,6 +58,20 @@ module clkmgr_dcm // + // IBUFGDS + // + /* Xilinx-specific primitive to handle LVDS input signal. */ + (* BUFFER_TYPE="NONE" *) + wire clk_in; + + IBUFGDS IBUFGDS_gclk + ( + .I(clk_in_p), + .IB(clk_in_n), + .O(clk_in) + ); + + // // DCM_SP // /* Xilinx-specific primitive. */ @@ -115,6 +131,7 @@ module clkmgr_dcm // // Mapping // + assign gclk_out = clk_in; assign gclk_missing_out= dcm_status_int[1]; assign clk_valid_out = dcm_locked_int & ((dcm_status_int[2:1] == 2'b00) ? 1'b1 : 1'b0); diff --git a/common/rtl/novena_clkmgr.v b/common/rtl/novena_clkmgr.v index e8ef1bd..83c6a68 100644 --- a/common/rtl/novena_clkmgr.v +++ b/common/rtl/novena_clkmgr.v @@ -56,22 +56,10 @@ module novena_clkmgr parameter CLK_OUT_DIV = 2; // - // IBUFGDS + // Wrapper for Xilinx-specific DCM (Digital Clock Manager) primitive. // - (* BUFFER_TYPE="NONE" *) - wire gclk; - IBUFGDS IBUFGDS_gclk - ( - .I(gclk_p), - .IB(gclk_n), - .O(gclk) - ); - - - // - // DCM - // + wire gclk; // buffered input clock wire dcm_reset; // dcm reset wire dcm_locked; // output clock valid wire gclk_missing; // no input clock @@ -83,8 +71,11 @@ module novena_clkmgr ) dcm ( - .clk_in (gclk), + .clk_in_p (gclk_p), + .clk_in_n (gclk_n), .reset_in (dcm_reset), + + .gclk_out (gclk), .gclk_missing_out (gclk_missing), .clk_out (sys_clk), |