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Diffstat (limited to 'common/rtl/novena_clkmgr.v')
-rw-r--r--common/rtl/novena_clkmgr.v21
1 files changed, 6 insertions, 15 deletions
diff --git a/common/rtl/novena_clkmgr.v b/common/rtl/novena_clkmgr.v
index e8ef1bd..83c6a68 100644
--- a/common/rtl/novena_clkmgr.v
+++ b/common/rtl/novena_clkmgr.v
@@ -56,22 +56,10 @@ module novena_clkmgr
parameter CLK_OUT_DIV = 2;
//
- // IBUFGDS
+ // Wrapper for Xilinx-specific DCM (Digital Clock Manager) primitive.
//
- (* BUFFER_TYPE="NONE" *)
- wire gclk;
- IBUFGDS IBUFGDS_gclk
- (
- .I(gclk_p),
- .IB(gclk_n),
- .O(gclk)
- );
-
-
- //
- // DCM
- //
+ wire gclk; // buffered input clock
wire dcm_reset; // dcm reset
wire dcm_locked; // output clock valid
wire gclk_missing; // no input clock
@@ -83,8 +71,11 @@ module novena_clkmgr
)
dcm
(
- .clk_in (gclk),
+ .clk_in_p (gclk_p),
+ .clk_in_n (gclk_n),
.reset_in (dcm_reset),
+
+ .gclk_out (gclk),
.gclk_missing_out (gclk_missing),
.clk_out (sys_clk),