diff options
Diffstat (limited to 'common/rtl/clkmgr_dcm.v')
| -rw-r--r-- | common/rtl/clkmgr_dcm.v | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/common/rtl/clkmgr_dcm.v b/common/rtl/clkmgr_dcm.v index 7c851f1..141863e 100644 --- a/common/rtl/clkmgr_dcm.v +++ b/common/rtl/clkmgr_dcm.v @@ -38,9 +38,11 @@ module clkmgr_dcm ( - input wire clk_in, + input wire clk_in_p, + input wire clk_in_n, input wire reset_in, + output wire gclk_out, output wire gclk_missing_out, output wire clk_out, @@ -56,6 +58,20 @@ module clkmgr_dcm // + // IBUFGDS + // + /* Xilinx-specific primitive to handle LVDS input signal. */ + (* BUFFER_TYPE="NONE" *) + wire clk_in; + + IBUFGDS IBUFGDS_gclk + ( + .I(clk_in_p), + .IB(clk_in_n), + .O(clk_in) + ); + + // // DCM_SP // /* Xilinx-specific primitive. */ @@ -115,6 +131,7 @@ module clkmgr_dcm // // Mapping // + assign gclk_out = clk_in; assign gclk_missing_out= dcm_status_int[1]; assign clk_valid_out = dcm_locked_int & ((dcm_status_int[2:1] == 2'b00) ? 1'b1 : 1'b0); |