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-rw-r--r--core_selector/src/rtl/core_selector.v219
-rw-r--r--core_selector/src/rtl/global_selector.v38
-rw-r--r--core_selector/src/rtl/hash_selector.v59
-rw-r--r--core_selector/src/rtl/rng_selector.v35
4 files changed, 206 insertions, 145 deletions
diff --git a/core_selector/src/rtl/core_selector.v b/core_selector/src/rtl/core_selector.v
index a18717a..275089f 100644
--- a/core_selector/src/rtl/core_selector.v
+++ b/core_selector/src/rtl/core_selector.v
@@ -44,14 +44,14 @@ module core_selector
input wire sys_clk,
input wire sys_rst,
- input wire noise,
-
input wire [16: 0] sys_eim_addr,
input wire sys_eim_wr,
input wire sys_eim_rd,
output wire [31: 0] sys_read_data,
input wire [31: 0] sys_write_data,
+ output wire sys_error,
+ input wire noise,
output wire [7 : 0] debug
);
@@ -68,153 +68,182 @@ module core_selector
*/
//----------------------------------------------------------------
- // Segment Decoder
+ // Address Decoder
+ //----------------------------------------------------------------
+ // 3 upper bits are decoded here
+ wire [ 2: 0] addr_segment = sys_eim_addr[16:14];
+ // 14 lower bits are decoded in corresponding segment selectors
+ wire [13: 0] addr_segment_int = sys_eim_addr[13: 0];
+
+
+ //----------------------------------------------------------------
+ // List of Available Segments
+ //----------------------------------------------------------------
+ // Comment following lines to exclude segments from implementation.
+ `define USE_SEGMENT_GLOBALS
+ `define USE_SEGMENT_HASHES
+ `define USE_SEGMENT_RNGS
+// `define USE_SEGMENT_CIPHERS
+
+
+ //----------------------------------------------------------------
+ // Segment Address Table
//----------------------------------------------------------------
localparam SEGMENT_ADDR_GLOBALS = 3'd0;
localparam SEGMENT_ADDR_HASHES = 3'd1;
localparam SEGMENT_ADDR_RNGS = 3'd2;
localparam SEGMENT_ADDR_CIPHERS = 3'd3;
- wire [ 2: 0] addr_segment = sys_eim_addr[16:14]; // 3 upper bits are decoded here
- wire [13: 0] addr_segment_int = sys_eim_addr[13: 0]; // 14 lower bits are decoded individually
- // in corresponding segment selectors
-
- wire [31: 0] segment_globals_read_data; // data read from GLOBALS segment
- wire [31: 0] segment_hashes_read_data; // data read from HASHES segment
- wire [31: 0] segment_rngs_read_data; // data read from RNGS segment
- wire [31: 0] segment_ciphers_read_data; // data read from CIPHERS segment
-
- wire segment_enable_globals = (addr_segment == SEGMENT_ADDR_GLOBALS) ? 1'b1 : 1'b0; // GLOBALS segment is being addressed
- wire segment_enable_hashes = (addr_segment == SEGMENT_ADDR_HASHES) ? 1'b1 : 1'b0; // HASHES segment is being addressed
- wire segment_enable_rngs = (addr_segment == SEGMENT_ADDR_RNGS) ? 1'b1 : 1'b0; // RNGS segment is being addressed
- wire segment_enable_ciphers = (addr_segment == SEGMENT_ADDR_CIPHERS) ? 1'b1 : 1'b0; // CIPHERS segment is being addressed
-
-
- //----------------------------------------------------------------
- // Output (Read Data) Bus
- //----------------------------------------------------------------
- reg [31: 0] sys_read_data_reg;
- assign sys_read_data = sys_read_data_reg;
-
- always @*
- //
- case (addr_segment)
- SEGMENT_ADDR_GLOBALS: sys_read_data_reg = segment_globals_read_data;
- SEGMENT_ADDR_HASHES: sys_read_data_reg = segment_hashes_read_data;
- SEGMENT_ADDR_RNGS: sys_read_data_reg = segment_rngs_read_data;
- SEGMENT_ADDR_CIPHERS: sys_read_data_reg = segment_ciphers_read_data;
- default: sys_read_data_reg = {32{1'b0}};
- endcase
-
-
-
+
//----------------------------------------------------------------
- // GLOBAL Core Selector
- //
- // This selector is used to map core registers into
- // EIM address space and select which core to send EIM read and
- // write operations to.
+ // GLOBALS Segment
//----------------------------------------------------------------
+ `ifdef USE_SEGMENT_GLOBALS
+ wire segment_enable_globals = (addr_segment == SEGMENT_ADDR_GLOBALS) ? 1'b1 : 1'b0;
+ wire [31: 0] segment_globals_read_data;
+ wire segment_globals_error;
+
global_selector globals
(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
+ .sys_ena(segment_enable_globals),
- .sys_ena(segment_enable_globals), // only enable active selector
-
- .sys_eim_addr(addr_segment_int), // we only connect 14 lower bits of address here,
- // because we have already decoded 3 upper bits earlier,
- // every segment can have its own address decoder.
+ .sys_eim_addr(addr_segment_int),
.sys_eim_wr(sys_eim_wr),
.sys_eim_rd(sys_eim_rd),
-
.sys_write_data(sys_write_data),
- .sys_read_data(segment_globals_read_data) // output from GLOBALS segment
+ .sys_read_data(segment_globals_read_data),
+ .sys_error(segment_globals_error)
);
-
-
+ `endif
+
+
//----------------------------------------------------------------
- // HASH Core Selector
- //
- // This selector is used to map core registers into
- // EIM address space and select which core to send EIM read and
- // write operations to.
+ // HASHES Segment
//----------------------------------------------------------------
+ `ifdef USE_SEGMENT_HASHES
+ wire segment_enable_hashes = (addr_segment == SEGMENT_ADDR_HASHES) ? 1'b1 : 1'b0;
+ wire [31: 0] segment_hashes_read_data;
+ wire segment_hashes_error;
+
hash_selector hashes
(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
+ .sys_ena(segment_enable_hashes),
- .sys_ena(segment_enable_hashes), // only enable active selector
-
- .sys_eim_addr(addr_segment_int), // we only connect 14 lower bits of address here,
- // because we have already decoded 3 upper bits earlier,
- // every segment can have its own address decoder.
+ .sys_eim_addr(addr_segment_int),
.sys_eim_wr(sys_eim_wr),
.sys_eim_rd(sys_eim_rd),
-
.sys_write_data(sys_write_data),
- .sys_read_data(segment_hashes_read_data) // output from HASHES segment
+ .sys_read_data(segment_hashes_read_data),
+ .sys_error(segment_hashes_error)
);
-
-
+ `endif
+
+
//----------------------------------------------------------------
- // RNG Selector
- //
- // This selector is used to map random number generator registers into
- // EIM address space and select which RNG to send EIM read and
- // write operations to. So far there are no RNG cores.
+ // RNGS Segment
//----------------------------------------------------------------
+ `ifdef USE_SEGMENT_RNGS
+ wire segment_enable_rngs = (addr_segment == SEGMENT_ADDR_RNGS) ? 1'b1 : 1'b0;
+ wire [31: 0] segment_rngs_read_data;
+ wire segment_rngs_error;
+
rng_selector rngs
(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
+ .sys_ena(segment_enable_rngs),
- .noise(noise),
-
- .sys_ena(segment_enable_rngs), // only enable active selector
-
- .sys_eim_addr(addr_segment_int), // we only connect 14 lower bits of address here,
- // because we have already decoded 3 upper bits earlier,
- // every segment can have its own address decoder.
+ .sys_eim_addr(addr_segment_int),
.sys_eim_wr(sys_eim_wr),
- .sys_eim_rd(sys_eim_rd),
-
+ .sys_eim_rd(sys_eim_rd),
.sys_write_data(sys_write_data),
- .sys_read_data(segment_rngs_read_data), // output from RNGS segment
+ .sys_read_data(segment_rngs_read_data),
+ .sys_error(segment_rngs_error),
+ .noise(noise), // only RNG segment uses these ports
.debug(debug)
);
-
-
+ `endif
+
+
//----------------------------------------------------------------
- // CIPHER Selector
- //
- // This selector is used to map cipher registers into
- // EIM address space and select which CIPHER to send EIM read and
- // write operations to. So far there are no CIPHER cores.
+ // CIPHERS Segment
//----------------------------------------------------------------
+ `ifdef USE_SEGMENT_CIPHERS
+ wire segment_enable_ciphers = (addr_segment == SEGMENT_ADDR_CIPHERS) ? 1'b1 : 1'b0;
+ wire [31: 0] segment_ciphers_read_data;
+ wire segment_ciphers_error;
+
cipher_selector ciphers
(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
+ .sys_ena(segment_enable_ciphers),
- .sys_ena(segment_enable_ciphers), // only enable active selector
-
- .sys_eim_addr(addr_segment_int), // we only connect 14 lower bits of address here,
- // because we have already decoded 3 upper bits earlier,
- // every segment can have its own address decoder.
+ .sys_eim_addr(addr_segment_int),
.sys_eim_wr(sys_eim_wr),
- .sys_eim_rd(sys_eim_rd),
-
+ .sys_eim_rd(sys_eim_rd),
.sys_write_data(sys_write_data),
- .sys_read_data(segment_ciphers_read_data) // output from CIPHERS segment
+ .sys_read_data(segment_ciphers_read_data),
+ .sys_error(segment_ciphers_error)
);
+ `endif
+
+
+ //----------------------------------------------------------------
+ // Output (Read Data) Bus
+ //----------------------------------------------------------------
+ reg [31: 0] sys_read_data_reg;
+ assign sys_read_data = sys_read_data_reg;
+ reg sys_error_reg;
+ assign sys_error = sys_error_reg;
+ always @*
+ //
+ case (addr_segment)
+ `ifdef USE_SEGMENT_GLOBALS
+ SEGMENT_ADDR_GLOBALS:
+ begin
+ sys_read_data_reg = segment_globals_read_data;
+ sys_error_reg = segment_globals_error;
+ end
+ `endif
+ `ifdef USE_SEGMENT_HASHES
+ SEGMENT_ADDR_HASHES:
+ begin
+ sys_read_data_reg = segment_hashes_read_data;
+ sys_error_reg = segment_hashes_error;
+ end
+ `endif
+ `ifdef USE_SEGMENT_RNGS
+ SEGMENT_ADDR_RNGS:
+ begin
+ sys_read_data_reg = segment_rngs_read_data;
+ sys_error_reg = segment_rngs_error;
+ end
+ `endif
+ `ifdef USE_SEGMENT_CIPHERS
+ SEGMENT_ADDR_CIPHERS:
+ begin
+ sys_read_data_reg = segment_ciphers_read_data;
+ sys_error_reg = segment_ciphers_error;
+ end
+ `endif
+ default:
+ begin
+ sys_read_data_reg = {32{1'b0}};
+ sys_error_reg = 1;
+ end
+ endcase
+
endmodule
//======================================================================
-// EOF eim_memory.v
+// EOF core_selector.v
//======================================================================
diff --git a/core_selector/src/rtl/global_selector.v b/core_selector/src/rtl/global_selector.v
index 25cad4e..523cc9b 100644
--- a/core_selector/src/rtl/global_selector.v
+++ b/core_selector/src/rtl/global_selector.v
@@ -49,15 +49,18 @@ module global_selector
input wire sys_eim_wr,
input wire sys_eim_rd,
output wire [31 : 0] sys_read_data,
- input wire [31 : 0] sys_write_data
+ input wire [31 : 0] sys_write_data,
+ output wire sys_error
);
//----------------------------------------------------------------
// Address Decoder
//----------------------------------------------------------------
- wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; // upper 6 bits specify core being addressed
- wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; // lower 8 bits specify register offset in core
+ // upper 6 bits specify core being addressed
+ wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8];
+ // lower 8 bits specify register offset in core
+ wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0];
//----------------------------------------------------------------
@@ -72,6 +75,8 @@ module global_selector
//----------------------------------------------------------------
wire [31: 0] read_data_board;
wire enable_board = sys_ena && (addr_core_num == CORE_ADDR_BOARD_REGS);
+ wire error_board;
+
board_regs board_regs
(
.clk(sys_clk),
@@ -82,7 +87,8 @@ module global_selector
.address(addr_core_reg),
.write_data(sys_write_data),
- .read_data(read_data_board)
+ .read_data(read_data_board),
+ .error(error_board)
);
@@ -91,6 +97,8 @@ module global_selector
//----------------------------------------------------------------
wire [31: 0] read_data_comm;
wire enable_comm = sys_ena && (addr_core_num == CORE_ADDR_COMM_REGS);
+ wire error_comm;
+
comm_regs comm_regs
(
.clk(sys_clk),
@@ -101,7 +109,8 @@ module global_selector
.address(addr_core_reg),
.write_data(sys_write_data),
- .read_data(read_data_comm)
+ .read_data(read_data_comm),
+ .error(error_comm)
);
@@ -109,19 +118,30 @@ module global_selector
// Output (Read Data) Multiplexor
//----------------------------------------------------------------
reg [31: 0] sys_read_data_mux;
- assign sys_read_data = sys_read_data_mux;
+ assign sys_read_data = sys_read_data_mux;
+ reg sys_error_mux;
+ assign sys_error = sys_error_mux;
always @*
//
case (addr_core_num)
//
CORE_ADDR_BOARD_REGS:
- sys_read_data_mux = read_data_board;
+ begin
+ sys_read_data_mux = read_data_board;
+ sys_error_mux = error_board;
+ end
CORE_ADDR_COMM_REGS:
- sys_read_data_mux = read_data_comm;
+ begin
+ sys_read_data_mux = read_data_comm;
+ sys_error_mux = error_comm;
+ end
//
default:
- sys_read_data_mux = {32{1'b0}};
+ begin
+ sys_read_data_mux = {32{1'b0}};
+ sys_error_mux = 1;
+ end
//
endcase
diff --git a/core_selector/src/rtl/hash_selector.v b/core_selector/src/rtl/hash_selector.v
index 66806b6..ad6793e 100644
--- a/core_selector/src/rtl/hash_selector.v
+++ b/core_selector/src/rtl/hash_selector.v
@@ -49,7 +49,8 @@ module hash_selector
input wire sys_eim_wr,
input wire sys_eim_rd,
output wire [31 : 0] sys_read_data,
- input wire [31 : 0] sys_write_data
+ input wire [31 : 0] sys_write_data,
+ output wire sys_error
);
/* In this memory segment (HASHES) we have 14 address bits. Every core has
@@ -114,17 +115,16 @@ XXX move to `define in wrapper core??
//----------------------------------------------------------------
// Address Decoder
//----------------------------------------------------------------
- wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; // upper 6 bits specify core being addressed
- wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; // lower 8 bits specify register offset in core
+ // upper 6 bits specify core being addressed
+ wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8];
+ // lower 8 bits specify register offset in core
+ wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0];
- /* We can comment following lines to exclude cores from implementation
- * in case we run out of slices.
- */
-
//----------------------------------------------------------------
// List of Available Cores
//----------------------------------------------------------------
+ // Comment following lines to exclude cores from implementation.
`define USE_CORE_SHA1
`define USE_CORE_SHA256
`define USE_CORE_SHA512
@@ -142,8 +142,10 @@ XXX move to `define in wrapper core??
// SHA-1
//----------------------------------------------------------------
`ifdef USE_CORE_SHA1
- wire [31: 0] read_data_sha1;
wire enable_sha1 = sys_ena && (addr_core_num == CORE_ADDR_SHA1);
+ wire [31: 0] read_data_sha1;
+ wire error_sha1;
+
sha1 sha1_inst
(
.clk(sys_clk),
@@ -154,7 +156,8 @@ XXX move to `define in wrapper core??
.address(addr_core_reg),
.write_data(sys_write_data),
- .read_data(read_data_sha1)
+ .read_data(read_data_sha1),
+ .error(error_sha1)
);
`endif
@@ -163,8 +166,10 @@ XXX move to `define in wrapper core??
// SHA-256
//----------------------------------------------------------------
`ifdef USE_CORE_SHA256
- wire [31: 0] read_data_sha256;
wire enable_sha256 = sys_ena && (addr_core_num == CORE_ADDR_SHA256);
+ wire [31: 0] read_data_sha256;
+ wire error_sha256;
+
sha256 sha256_inst
(
.clk(sys_clk),
@@ -175,7 +180,8 @@ XXX move to `define in wrapper core??
.address(addr_core_reg),
.write_data(sys_write_data),
- .read_data(read_data_sha256)
+ .read_data(read_data_sha256),
+ .error(error_sha256)
);
`endif
@@ -184,8 +190,10 @@ XXX move to `define in wrapper core??
// SHA-512
//----------------------------------------------------------------
`ifdef USE_CORE_SHA512
- wire [31: 0] read_data_sha512;
wire enable_sha512 = sys_ena && (addr_core_num == CORE_ADDR_SHA512);
+ wire [31: 0] read_data_sha512;
+ wire error_sha512;
+
sha512 sha512_inst
(
.clk(sys_clk),
@@ -196,7 +204,8 @@ XXX move to `define in wrapper core??
.address(addr_core_reg),
.write_data(sys_write_data),
- .read_data(read_data_sha512)
+ .read_data(read_data_sha512),
+ .error(error_sha512)
);
`endif
@@ -205,7 +214,9 @@ XXX move to `define in wrapper core??
// Output (Read Data) Multiplexor
//----------------------------------------------------------------
reg [31: 0] sys_read_data_mux;
- assign sys_read_data = sys_read_data_mux;
+ assign sys_read_data = sys_read_data_mux;
+ reg sys_error_mux;
+ assign sys_error = sys_error_mux;
always @*
//
@@ -213,19 +224,31 @@ XXX move to `define in wrapper core??
//
`ifdef USE_CORE_SHA1
CORE_ADDR_SHA1:
- sys_read_data_mux = read_data_sha1;
+ begin
+ sys_read_data_mux = read_data_sha1;
+ sys_error_mux = error_sha1;
+ end
`endif
`ifdef USE_CORE_SHA256
CORE_ADDR_SHA256:
- sys_read_data_mux = read_data_sha256;
+ begin
+ sys_read_data_mux = read_data_sha256;
+ sys_error_mux = error_sha256;
+ end
`endif
`ifdef USE_CORE_SHA512
CORE_ADDR_SHA512:
- sys_read_data_mux = read_data_sha512;
+ begin
+ sys_read_data_mux = read_data_sha512;
+ sys_error_mux = error_sha512;
+ end
`endif
//
default:
- sys_read_data_mux = {32{1'b0}};
+ begin
+ sys_read_data_mux = {32{1'b0}};
+ sys_error_mux = 1;
+ end
//
endcase
diff --git a/core_selector/src/rtl/rng_selector.v b/core_selector/src/rtl/rng_selector.v
index 0b56684..9dd0330 100644
--- a/core_selector/src/rtl/rng_selector.v
+++ b/core_selector/src/rtl/rng_selector.v
@@ -41,26 +41,22 @@
module rng_selector
(
- input wire sys_clk,
- input wire sys_rst,
+ input wire sys_clk,
+ input wire sys_rst,
+ input wire sys_ena,
- input wire noise,
-
- input wire sys_ena,
- input wire [13: 0] sys_eim_addr,
- input wire sys_eim_wr,
- input wire sys_eim_rd,
+ input wire [13: 0] sys_eim_addr,
+ input wire sys_eim_wr,
+ input wire sys_eim_rd,
output wire [31 : 0] sys_read_data,
- input wire [31 : 0] sys_write_data,
+ input wire [31 : 0] sys_write_data,
+ output wire sys_error,
- output wire [7 : 0] debug
+ input wire noise,
+ output wire [7 : 0] debug
);
-`define USE_TRNG
-
-`ifdef USE_TRNG
-
// This is a pass-through to trng.v, which instantiates and muxes the
// entropy sources, mixer, and csprng.
@@ -69,25 +65,18 @@ module rng_selector
.clk(sys_clk),
.reset_n(~sys_rst),
- .avalanche_noise(noise),
-
.cs(sys_ena & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
.address(sys_eim_addr[11:0]),
.write_data(sys_write_data),
.read_data(sys_read_data),
+ .error(sys_error),
+ .avalanche_noise(noise),
.debug(debug)
);
-`else
-
- assign sys_read_data = {32{1'b0}};
- assign debug = {32{1'b0}};
-
-`endif
-
endmodule
//======================================================================
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 20:36:16 +0000