diff options
Diffstat (limited to 'src')
47 files changed, 5964 insertions, 0 deletions
diff --git a/src/rtl/ipcore/_xmsgs/cg.xmsgs b/src/rtl/ipcore/_xmsgs/cg.xmsgs new file mode 100644 index 0000000..f165d5f --- /dev/null +++ b/src/rtl/ipcore/_xmsgs/cg.xmsgs @@ -0,0 +1,39 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages> +<msg type="info" file="sim" num="172" delta="old" >Generating IP...
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'multiplier_s6' already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'multiplier_s6' already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+ +<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for 'multiplier_s6'...</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
+</msg>
+ +<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
+</msg>
+ +<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
+</msg>
+ +</messages> +
diff --git a/src/rtl/ipcore/_xmsgs/pn_parser.xmsgs b/src/rtl/ipcore/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..cd873b7 --- /dev/null +++ b/src/rtl/ipcore/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated --> +<!-- by the Xilinx ISE software. Any direct editing or --> +<!-- changes made to this file may result in unpredictable --> +<!-- behavior or data corruption. It is strongly advised that --> +<!-- users do not edit the contents of this file. --> +<!-- --> +<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> + +<messages> +<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/pselkirk/cryptech/core/math/modexps6/src/rtl/ipcore/subtractor_s6.v" into library work</arg> +</msg> + +</messages> + diff --git a/src/rtl/ipcore/coregen.cgp b/src/rtl/ipcore/coregen.cgp new file mode 100644 index 0000000..8bc2e70 --- /dev/null +++ b/src/rtl/ipcore/coregen.cgp @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = Verilog +SET device = xc6slx45 +SET devicefamily = spartan6 +SET flowvendor = Other +SET package = csg324 +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false diff --git a/src/rtl/ipcore/edit_multiplier_s6.tcl b/src/rtl/ipcore/edit_multiplier_s6.tcl new file mode 100644 index 0000000..b2357d5 --- /dev/null +++ b/src/rtl/ipcore/edit_multiplier_s6.tcl @@ -0,0 +1,37 @@ +##
+## Core Generator Run Script, generator for Project Navigator edit command
+##
+
+proc findRtfPath { relativePath } {
+ set xilenv ""
+ if { [info exists ::env(XILINX) ] } {
+ if { [info exists ::env(MYXILINX)] } {
+ set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+ } else {
+ set xilenv $::env(XILINX)
+ }
+ }
+ foreach path [ split $xilenv $::xilinx::path_sep ] {
+ set fullPath [ file join $path $relativePath ]
+ if { [ file exists $fullPath ] } {
+ return $fullPath
+ }
+ }
+ return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_edit "multiplier_s6" xc6slx45-3csg324 Verilog ]
+
+if { $result == 0 } {
+ puts "Core Generator edit command completed successfully."
+} elseif { $result == 1 } {
+ puts "Core Generator edit command failed."
+} elseif { $result == 3 || $result == 4 } {
+ # convert 'version check' result to real return range, bypassing any messages.
+ set result [ expr $result - 3 ]
+} else {
+ puts "Core Generator edit cancelled."
+}
+exit $result
diff --git a/src/rtl/ipcore/edit_subtractor_s6.tcl b/src/rtl/ipcore/edit_subtractor_s6.tcl new file mode 100644 index 0000000..49f4d27 --- /dev/null +++ b/src/rtl/ipcore/edit_subtractor_s6.tcl @@ -0,0 +1,37 @@ +##
+## Core Generator Run Script, generator for Project Navigator edit command
+##
+
+proc findRtfPath { relativePath } {
+ set xilenv ""
+ if { [info exists ::env(XILINX) ] } {
+ if { [info exists ::env(MYXILINX)] } {
+ set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+ } else {
+ set xilenv $::env(XILINX)
+ }
+ }
+ foreach path [ split $xilenv $::xilinx::path_sep ] {
+ set fullPath [ file join $path $relativePath ]
+ if { [ file exists $fullPath ] } {
+ return $fullPath
+ }
+ }
+ return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_edit "subtractor_s6" xc6slx45-3csg324 Verilog ]
+
+if { $result == 0 } {
+ puts "Core Generator edit command completed successfully."
+} elseif { $result == 1 } {
+ puts "Core Generator edit command failed."
+} elseif { $result == 3 || $result == 4 } {
+ # convert 'version check' result to real return range, bypassing any messages.
+ set result [ expr $result - 3 ]
+} else {
+ puts "Core Generator edit cancelled."
+}
+exit $result
diff --git a/src/rtl/ipcore/multiplier_s6.asy b/src/rtl/ipcore/multiplier_s6.asy new file mode 100644 index 0000000..4bcf909 --- /dev/null +++ b/src/rtl/ipcore/multiplier_s6.asy @@ -0,0 +1,21 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 multiplier_s6 +RECTANGLE Normal 32 32 544 416 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName a[31:0] +PINATTR Polarity IN +LINE Wide 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName b[31:0] +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName p[63:0] +PINATTR Polarity OUT +
diff --git a/src/rtl/ipcore/multiplier_s6.gise b/src/rtl/ipcore/multiplier_s6.gise new file mode 100644 index 0000000..bfafdc6 --- /dev/null +++ b/src/rtl/ipcore/multiplier_s6.gise @@ -0,0 +1,53 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="multiplier_s6.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="multiplier_s6.asy" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="multiplier_s6.sym" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="multiplier_s6.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">
+ <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1436912095">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-480660529792370684" xil_pn:start_ts="1436912095">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1432244621186928363" xil_pn:start_ts="1436912095">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1436912095">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6211771399160386746" xil_pn:start_ts="1436912095">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ </transforms>
+
+</generated_project>
diff --git a/src/rtl/ipcore/multiplier_s6.ncf b/src/rtl/ipcore/multiplier_s6.ncf new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/rtl/ipcore/multiplier_s6.ncf diff --git a/src/rtl/ipcore/multiplier_s6.ngc b/src/rtl/ipcore/multiplier_s6.ngc new file mode 100644 index 0000000..10fa0cc --- /dev/null +++ b/src/rtl/ipcore/multiplier_s6.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$5`544<,[o}e~g`n;"2*73>(-80!<?400285=<NFY__6L2>7;2=55=603CE\XZ5B=34>586;2;36D@_UU8AGLH;9>0;2<>4198JJUSS2M6:;7>11492<?IR\Y__6OM@UU>23?6990196B[[PTV9^@THWMO_INZ31;2=55=4:3CE\XZ5A=12>58682996D@_UU8A867=87;;7><5IORVP?g;;80;2<>4338JJUSS2k68=7>110902?IR\Y__6@2<5;2=55=303CE\XZ5C=64>586;2>36D@_UU8SGLH;<>0;2<?4498LQQVR\3Z78:4?>0780=<H]]Z^X7^LARA?02<768?0854@UURVP?VDG\^78:4?>03821<H]]Z^X7^36283:47<>=0DYY^ZT;r?26<76l1=av;5bqd772*;89047GAPTV9KUKHLL6<6=0:;@2QAB3<I8XNK95N<1<6?D:687?0M1?>>49B8449=2K7=>0:;@>20;3<I5;>285N<04=3>G;9>0;285N<05=1>G;914>7L2>9?68E979=2K7>=0:;@>15;3<I589285N<31=1>G;:=4>7L2=5?78E9416<1J0?915:C?6=823H6953:4A=0=1>G;;94<7L2<1;2=1>G;;84?7L2<>59B81833H6>295N<7<7?D:06=1J050;;@>::0=E8[OL96L>RDE7?G:76<1I0<>15:@?54823K6:>3;4B=30:0=E48>596L314<6?G:6>7=0N1?8:1<6?G:6?7?0N1?7>49A84?9<2H7=3;4B=03:0=E4;;596L323<6?G:5;7?0N1<;>49A8739=2H7>;0:;C>13;3<J583285M<3;=0>D;:7?0N1=?>69A867=87?0N1=>>59A86833K6?295M<4<7?G:16=1I0:0;;C>;:1=E404<7OMFN=2=<>DDAG6:<364BBKM847902HHEC2>2?:8FFOI489546LLIO>20;><JJCE0<;18:@@MK:6>7k0NNGA<0594;><JJCE0<917:@@MK:66>1IOD@32?58FFOI4:4<7OMFN=6=3>DDAG6>2:5MCHL?2;1<JJCE0:08;CAJJ9>9?2HHEC26>99AGJSS49427OM@UU>24;?<JJE^X1?>>89AGJSS488556LLOTV?568>3KIDYY2>4?;8FFIR\5;>245MCNWW8409j2HHCXZ31683:<=EKF__0<918:@@KPR;9720NNAZT=0=<>DDG\^7?364BBMVP92902HHCXZ35?:8FFIR\5<546LLOTV?3;><JJE^X1618:@@KPR;1720NX]PIODL5>E33J6;285L<02=1>E;984>7N2>2?78G9746<1H0<:15:A?50823J6::3;4C=34:0=D482596M318<7?F:66<1H0?>15:A?64823J69>3;4C=00:0=D4;>596M324<6?F:5>7?0O1<8>49@87>9=2I7>40;;B>1:0=D4::596M330<6?F:4:7?0O1=<>49@8629=2I7?80:;B>02;3<K59<285L<2:=1>E;;04?7N2<>49@8169=2I78<0:;B>76;3<K5>8285L<56=1>E;<<4>7N2;6?58G920294>7N2;7?68G929<2I793:4C=4=0>E;?7>0O1614:A?=;1<KHXYUD@n;BCQV\OIZLMj7NO]RXKMW@J?3JKY^TAZT89@EWT^G\^Mn6MNRS[LQQTBO;1HI>5LE@18G@D43JOH56MJC@PQ]LH43JOO?6MJM99@AJVJGMO87NK_139@L@ELWECHIC]J_U[SA6=DDB>0OAE?6:AOO4>7>2IGG?9?5:AOO7^?3JF@>U?7049@HN?7=2IGGL?8;BNHE4B5?2IGGL?K469@HNG6L1?0OAEM149@HNE6=2IGGI?:;BNH@Se<KEAOZRJFVHFF1>EKCOR37NBDFY3;4<=DGDGBXYKK159@KWCXOLDN^LZFOO]JJCI03JXNMYKK4:AQAB7<L=1O0=0:;E>24;3<L5;:285K<00=1>B;9:4>7I2>4?78@9726<1O0<817:F?52<76<1O0<914:F?5;2<L58586J33?68@929<2N793:4D=4=0>B;?7>0H1614:F?=;2<L[OL;6J\P5:B57=AL81L?6IAD89JJLRT\H^N:6B@AEGG2>JHKBOO;6B@GHABH1=J494>7@2>0?78I9766<1F0<<15:O?56823D6:83;4M=36:0=J48<596C316<6?H:607?0A1?6>59N84823D69<3;4M=02:0=J4;8596C322<6?H:5<7?0A1<:>49N8709=2G7>:0:;L>1<;3<E582295B<3<6?H:487?0A1=>>49N8649=2G7?>0:;L>00;1<E59>6=0:;L>01;2<E59586C34?68I939<2G7:3:4M=5=0>K;07>0A1714:OQABe<Eh`d~[k}shmmg>Knffx]i}foo58J@RPG[A<7B^BOEG6=>IWEFNN0=06;NRNKAC;9730C]C@DD>1:<=HXDEOI1=19:MSIJBB4=427B^BOEG?1;?<GYGDHH29>c9LTHICM5=1<374OQOL@@:0601D\@AKESGD52=HX]CFEWKPPSKNMQOQMZUEKNo4Ocdvwfgsg{;0\n5_.3227466;VF?7]2?>49S8469=2Z7=<0:;Q>26;3<X5;8285_<06=1>V;9<4>7]2>6?78T9706<1[0<615:R?5<833Y6:285_<32=1>V;:84>7]2=2?78T9446<1[0?:15:R?60823Y69:3;4P=04:0=W4;2596^328<7?U:56<1[0>>15:R?74823Y68>3;4P=10:0=W4:>596^334<6?U:4>7?0\1=8>49S86>9=2Z7?40;;Q>0:0=W4=:596^340<6?U:3:7?0\1:<>49S8129=2Z7880:;Q>72;1<X5><6=0:;Q>73;3<X5>3285_<5;=0>V;<7?0\1;?>49S8079=2Z79?0:;Q>67;3<X5??285_<47=1>V;=?4>7]2:7?78T93?6<1[08714:R?1;3<X5<;285_<73=1>V;>;4<7]293;2=1>V;>:4?7]29>59S82833Y63295_<8<7?UGU\11[OL]L<1<:?UEF[J6:<374PBCPG976601[OL]L<00==>VDIZI7=>06;QABWF:6<730\NO\C=36:<=WKHYH0<819:R@EVE;9>427]MNSB>2<;?<XJKXO1?6>99SGDUD48427]MNSB>14;?<XJKXO1<>>89SGDUD4;8556^LARA?668>3YIJ_N2=4?;8TFGTK58>245_C@Q@870912ZHM^M326<:?UEF[J694374PBCPG94>611[OL]L<3<:?UEF[J68<374PBCPG956601[OL]L<20==>VDIZI7?>06;QABWF:4<730\NO\C=16:<=WKHYH0>819:R@EVE;;>427]MNSB>0<;?<XJKXO1=6>99SGDUD4:427]MNSB>74;?<XJKXO1:>>89SGDUD4=8556^LARA?068>3YIJ_N2;4?;8TFGTK5>>245_C@Q@8109j2ZHM^M34683:<=WKHYH09918:R@EVE;<720\NO\C=7=<>VDIZI7:364PBCPG91902ZHM^M38?:8TFGTK535;6^LIO>3:==WK@D7==07;QAJJ976611[OD@313<;?UENF5;8255_CHL?518?3YIBB1?:>99SGLH;9?437]MFN=34:==WK@D7=507;QAJJ97>6>1[OD@31?:8TFOI4;:546^LIO>15;><XJCE0?<18:R@MK:5;720\NGA<36=<>VDAG699364PBKM870902ZHEC2=7?:8TFOI4;2546^LIO>1=;1<XJCE0?07;QAJJ957611[OD@330<;?UENF599255_CHL?768?3YIBB1=;>99SGLH;;<437]MFN=15:==WK@D7?:07;QAJJ95?611[OD@338<4?UENF59546^LIO>74;><XJCE09?18:R@MK:3:720\NGA<51=<>VDAG6?8364PBKM813902ZHEC2;6?c8TFOI4==1<364PBKM8119?2ZHEC2;>69SGLH;=7=0\NGA<7<4?UENF5=5;6^LIO>;:2=WK@D75364PBMVP96912ZHCXZ311<:?UEH]]6:=374PBMVP975601[OB[[<01==>VDG\^7=906;QALQQ:6=730\NAZT=35:<=WKF__0<919:R@KPR;91427]M@UU>2=;><XJE^X1?19:R@KPR;:9427]M@UU>15;?<XJE^X1<=>89SGJSS4;9556^LOTV?618>3YIDYY2=5?;8TFIR\58=245_CNWW871912ZHCXZ329<:?UEH]]695364PBMVP94912ZHCXZ331<:?UEH]]68=374PBMVP955601[OB[[<21==>VDG\^7?906;QALQQ:4=730\NAZT=15:<=WKF__0>919:R@KPR;;1427]M@UU>0=;><XJE^X1=19:R@KPR;<9427]M@UU>75;?<XJE^X1:=>89SGJSS4=9556^LOTV?018>3YIDYY2;5?;8TFIR\5>=2o5_CNWW811=8730\NAZT=64:==WKF__0907;QALQQ:2611[OB[[<7<;?UEH]]6<255_CNWW8=8?3YIDYY26>`9SMKYE]ZCOTo5_IO]AQVHFEL>0\_KH6:RP@JHB92[?7_][A59QWQD33[Y_Ol5]SUABVW_NF=1Y_YJ;;SQWI<=U[]E[ABJJ4:PPPU1<ZZ^_U]K;;RAOV47<[AXNKRKWTSC@PZH@Kl1XD_KH_LKM[VO]M11XGD^PPHL5?VIRZJO=7^ZNTTQ7?V_IK=1_U]Kl;TQFVZPN[@HGI>5YCB;8RLCPW]S[I<j4XHNJJ]+_LK*;"<.\TT@#4+7'IZIBE;5WSUNJFg=_WJEYIRGAFN48\adXAml0TifPPsknR`ttafd:<6Vkm^ObnjtQm{ybcc??;Yfn[Hoig{\n~~g`n29[wq5<Qlyn7WK]O^FFP@ES494:<6TJRN]GAQCD\5;1<3k4ZDPL[ACSMJ^7=3:4a=2=1>g;994>7l2>1?78e9756<1j0<=15:c?51823h6:93;4a=35:0=f48=596o319<6?d:617>0m1?15:c?65823h69=3;4a=01:0=f4;9596o325<6?d:5=7?0m1<9>49b8719=2k7>50:;`>1=;2<i58596o331<4?d:493:596o330<7?d:46=1j090;;`>6:1=f4?4?7l28>59b8=833h62295m<1<6?g:687?0n1?>>49a8449=2h7=>0:;c>20;3<j5;>285m<04=1>d;9>4>7o2>8?78f97>6=1i0<0:;c>14;3<j58:285m<30=1>d;::4>7o2=4?78f9426<1i0?815:`?62823k6943;4b=0::1=e4;4>7o2<0?58f956294>7o2<1?68f959<2h783:4b=7=0>d;>7>0n1914:`?<;2<j535n6lck12345679k1i`f>?012347d<jea;<=>?011a?gjl89:;<=>;b:`oo56789:;9o5mlj2345678?h0nae?0123451e3kf`<=>?012;f>dkc9:;<=>?9c9ahn6789:;<ll4bmi3456789hi7obd0123456dj2hgg=>?0123`g=edb:;<=>?0d`8fim789:;<=hm;cnh456789;;n6lck12345669k1i`f>?012357d<jea;<=>?001a?gjl89:;<=?;b:`oo56789::9o5mlj2345679?h0nae?0123441e3kf`<=>?013;f>dkc9:;<=>>9c9ahn6789:;=ll4bmi3456788hi7obd0123457dj2hgg=>?0122`g=edb:;<=>?1d`8fim789:;<<hm;cnh4567898;n6lck12345659k1i`f>?012367d<jea;<=>?031a?gjl89:;<=<;b:`oo56789:99o5mlj234567:?h0nae?0123471e3kf`<=>?010;f>dkc9:;<=>=929`hne<llfjuRbfnd]2g>bbdhsT`d`j_3a8``jfqVfbbhQ<c:ffhdXd`dnS9m4ddnb}ZjnflU>?6j|pd9nqirXoldTz<?P23c8ipjsWnoeS{?>_3.#\ljnfq*HC_K/Gdlfvdrhz);?":?=;lwopZabfV|:=R<Pxrvg?hsk|`zgeh|Ps737=>krd}c{`dk}_r4/ipjsWnoeS{?>_3.xgZgX|pzn1<"l_`]tmaro5:8'oRlPtxrf94*dWkU}ma{j=02345679%iTnRyfduj>77*dWjifSdc=1.`[fcXgoy~djjs^q`hw;7$jUcm~Qle<2/gZnf{Vyh`3?,b]kevY}m{eThhzjcu?3(fYki}oeot3=,b]nkackW}s{i0>#c^ovhqYsqyo6=!mPoqvjil|bWnej`0?#c^mvpZnnoa7=?!mPotv\hjq:8%iT~b{ad^mvpuss59&hSazne]sp86+kV|n~oa|iu{>4)eXpmo}enkialko}8uwi{~jb;s>f:ovhqowd`oyS~8#mtnw[bciW;:S?"t}99mcfdraen97ca6;nr\v`unrl>0|1>15:r?55823y6:=3;4p=31:0=w489596~315<6?u:6=7?0|1?9>49s8419=2z7=50:;q>2=;2<x5;596~321<6?u:597?0|1<=>49s8759=2z7>90:;q>11;3<x58=285<35=1>v;:14>7}2=9?68t949=2z7?=0:;q>05;3<x599285<21=1>v;;=4>7}2<5?78t9516<1{0>915:r?7=823y6853:4p=1=1>v;<94>7}2;1?78t9256<1{09=15:r?01823y6?93;4p=65:0=w4==596~349<6?u:317>0|1:15:r?15823y6>=3;4p=71:0=w4<9596~355<6?u:2=7?0|1;9>49s8019=2z7950:;q>6=;2<x5?596~361<6?u:197?0|18=>69s835=87?0|18<>59s83833y6<295<9<7?u:>6k1xej>?012344d<{`m;<=>?010a?vo`89:;<=><b:qjc56789:;8o5|if2345678<h0di?0123450e3zcl<=>?0124f>uno9:;<=>?8c9pmb6789:;<4l4she3456789ki7~gh0123456ej2ybk=>?0123gg=tan:;<=>?0e`8wla789:;<=km;rkd456789:mn6}fg12345668k1xej>?012354d<{`m;<=>?000a?vo`89:;<=?<b:qjc56789::8o5|if2345679<h0di?0123440e3zcl<=>?0134f>uno9:;<=>>8c9pmb6789:;=4l4she3456788ki7~gh0123457ej2ybk=>?0122gg=tan:;<=>?1e`8wla789:;<<km;rkd456789;mn6}fg12345658k1xej>?012364d<{`m;<=>?030a?vo`89:;<=<<b:qjc56789:98o5|if234567:<h0di?0123470e3zcl<=>?0104f>uno9:;<=>=8c9pmb6789:;>4l4she345678;ki7~gh0123454ej2ybk=>?0121gg=tan:;<=>?2e`8wla789:;<?km;rkd4567898mn6}fg12345648k1xej>?012374d<{`m;<=>?020a?vo`89:;<==<b:qjc56789:88o5|if234567;<h0di?0123460e3zcl<=>?0114f>uno9:;<=><8c9pmb6789:;?4l4she345678:ki7~gh0123455ej2ybk=>?0120gg=tan:;<=>?3e`8wla789:;<>km;rkd4567899mn6}fg12345638k1xej>?012304d<{`m;<=>?050a?vo`89:;<=:<b:qjc56789:?8o5|if234567<<h0di?0123410e3zcl<=>?0164f>uno9:;<=>;8c9pmb6789:;84l4she345678=ki7~gh0123452ej2ybk=>?0127gg=tan:;<=>?4e`8wla789:;<9km;rkd456789>mn6}fg12345628k1xej>?012314d<{`m;<=>?040a?vo`89:;<=;<b:qjc56789:>8o5|if234567=<h0di?0123400e3zcl<=>?0174f>uno9:;<=>:8c9pmb6789:;94l4she345678<ki7~gh0123453ej2ybk=>?0126gg=tan:;<=>?5e`8wla789:;<8km;rkd456789?mn6}fg12345618k1xej>?012324d<{`m;<=>?070a?vo`89:;<=8<b:qjc56789:=8o5|if234567><h0di?0123430e3zcl<=>?0144f>uno9:;<=>98c9pmb6789:;:4l4she345678?ki7~gh0123450ej2ybk=>?0125gg=tan:;<=>?6e`8wla789:;<;km;rkd456789<mn6}fg12345608k1xej>?012334d<{`m;<=>?060a?vo`89:;<=9<b:qjc56789:<8o5|if234567?<h0di?0123420e3zcl<=>?0154f>uno9:;<=>88c9pmb6789:;;4l4she345678>ki7~gh0123451ej2ybk=>?0124gg=tan:;<=>?7e`8wla789:;<:km;rkd456789=mn6}fg123456?8k1xej>?0123<4d<{`m;<=>?090a?vo`89:;<=6<b:qjc56789:38o5|if2345670<h0di?01234=0e3zcl<=>?01:4f>uno9:;<=>78c9pmb6789:;44l4she3456781ki7~gh012345>ej2ybk=>?012;gg=tan:;<=>?8e`8wla789:;<5km;rkd4567892mn6}fg123456>8k1xej>?0123=4d<{`m;<=>?080a?vo`89:;<=7<b:qjc56789:28o5|if2345671<h0di?01234<0e3zcl<=>?01;4f>uno9:;<=>68c9pmb6789:;54l4she3456780ki7~gh012345?ej2ybk=>?012:gg=tan:;<=>?9e`8wla789:;<4km;rkd4567893mn6}fg123456f8k1xej>?0123e4d<{`m;<=>?0`0a?vo`89:;<=o<b:qjc56789:j8o5|if234567i<h0di?01234d0e3zcl<=>?01c4f>uno9:;<=>n8c9pmb6789:;m4l4she345678hki7~gh012345gej2ybk=>?012bgg=tan:;<=>?ae`8wla789:;<lkm;rkd456789kmn6}fg123456e8k1xej>?0123f4d<{`m;<=>?0c0a?vo`89:;<=l<b:qjc56789:i8o5|if234567j<h0di?01234g0e3zcl<=>?01`4f>uno9:;<=>m8c9pmb6789:;n4l4she345678kki7~gh012345dej2ybk=>?012agg=tan:;<=>?be`8wla789:;<okm;rkd456789hmn6}fg123456d8k1xej>?0123g4d<{`m;<=>?0b0a?vo`89:;<=m<b:qjc56789:h8o5|if234567k<h0di?01234f0e3zcl<=>?01a4f>uno9:;<=>l8c9pmb6789:;o4l4she345678jki7~gh012345eej2ybk=>?012`gg=tan:;<=>?ce`8wla789:;<nkm;rkd456789imn6}fg123456c8k1xej>?0123`4d<{`m;<=>?0e0a?vo`89:;<=j<b:qjc56789:o8o5|if234567l<h0di?01234a0e3zcl<=>?01f4f>uno9:;<=>k8c9pmb6789:;h4l4she345678mki7~gh012345bej2ybk=>?012ggg=tan:;<=>?de`8wla789:;<ikm;rkd456789nmn6}fg123456b8k1xej>?0123a4d<{`m;<=>?0d0a?vo`89:;<=k<b:qjc56789:n8o5|if234567m<h0di?01234`0e3zcl<=>?01g4f>uno9:;<=>j8c9pmb6789:;i4l4she345678lki7~gh012345cej2ybk=>?012fgg=tan:;<=>?ee`8wla789:;<hkm;rkd456789omn6}fg123456a8k1xej>?0123b4d<{`m;<=>?0g0a?vo`89:;<=h<b:qjc56789:m8o5|if234567n<h0di?01234c0e3zcl<=>?01d4f>uno9:;<=>i8c9pmb6789:;j4l4she345678oki7~gh012345`ej2ybk=>?012egg=tan:;<=>?fe`8wla789:;<kkm;rkd456789lmn6}fg12345778k1xej>?012244d<{`m;<=>?110a?vo`89:;<<><b:qjc56789;;8o5|if2345668<h0di?0123550e3zcl<=>?0024f>uno9:;<=??8c9pmb6789::<4l4she3456799ki7~gh0123446ej2ybk=>?0133gg=tan:;<=>>0e`8wla789:;==km;rkd456788:mn6}fg12345768k1xej>?012254d<{`m;<=>?100a?vo`89:;<<?<b:qjc56789;:8o5|if2345669<h0di?0123540e3zcl<=>?0034f>uno9:;<=?>8c9pmb6789::=4l4she3456798ki7~gh0123447ej2ybk=>?0132gg=tan:;<=>>1e`8wla789:;=<km;rkd456788;mn6}fg12345758k1xej>?012264d<{`m;<=>?130a?vo`89:;<<<<b:qjc56789;98o5|if234566:<h0di?0123570e3zcl<=>?0004f>uno9:;<=?=8c9pmb6789::>4l4she345679;ki7~gh0123444ej2ybk=>?0131gg=tan:;<=>>2e`8wla789:;=?km;rkd4567888mn6}fg12345748k1xej>?012274d<{`m;<=>?120a?vo`89:;<<=<b:qjc56789;88o5|if234566;<h0di?0123560e3zcl<=>?0014f>uno9:;<=?<8c9pmb6789::?4l4she345679:ki7~gh0123445ej2ybk=>?0130gg=tan:;<=>>3e`8wla789:;=>km;rkd4567889mn6}fg12345738k1xej>?012204d<{`m;<=>?150a?vo`89:;<<:<b:qjc56789;?8o5|if234566<<h0di?0123510e3zcl<=>?0064f>uno9:;<=?;8c9pmb6789::84l4she345679=ki7~gh0123442ej2ybk=>?0137gg=tan:;<=>>4e`8wla789:;=9km;rkd456788>mn6}fg12345728k1xej>?012214d<{`m;<=>?140a?vo`89:;<<;<b:qjc56789;>8o5|if234566=<h0di?0123500e3zcl<=>?0074f>uno9:;<=?:8c9pmb6789::94l4she345679<ki7~gh0123443ej2ybk=>?0136gg=tan:;<=>>5e`8wla789:;=8km;rkd456788?mn6}fg12345718k1xej>?012224d<{`m;<=>?170a?vo`89:;<<8<b:qjc56789;=8o5|if234566><h0di?0123530e3zcl<=>?0044f>uno9:;<=?98c9pmb6789:::4l4she345679?ki7~gh0123440ej2ybk=>?0135gg=tan:;<=>>6e`8wla789:;=;km;rkd456788<mn6}fg12345708k1xej>?012234d<{`m;<=>?160a?vo`89:;<<9<b:qjc56789;<8o5|if234566?<h0di?0123520e3zcl<=>?0054f>uno9:;<=?88c9pmb6789::;4l4she345679>ki7~gh0123441ej2ybk=>?0134gg=tan:;<=>>7e`8wla789:;=:km;rkd456788=mn6}fg123457?8k1xej>?0122<4d<{`m;<=>?190a?vo`89:;<<6<b:qjc56789;38o5|if2345660<h0di?01235=0e3zcl<=>?00:4f>uno9:;<=?78c9pmb6789::44l4she3456791ki7~gh012344>ej2ybk=>?013;gg=tan:;<=>>8e`8wla789:;=5km;rkd4567882mn6}fg123457>8k1xej>?0122=4d<{`m;<=>?180a?vo`89:;<<7<b:qjc56789;28o5|if2345661<h0di?01235<0e3zcl<=>?00;4f>uno9:;<=?68c9pmb6789::54l4she3456790ki7~gh012344?ej2ybk=>?013:gg=tan:;<=>>9e`8wla789:;=4km;rkd4567883mn6}fg123457f8k1xej>?0122e4d<{`m;<=>?1`0a?vo`89:;<<o<b:qjc56789;j8o5|if234566i<h0di?01235d0e3zcl<=>?00c4f>uno9:;<=?n8c9pmb6789::m4l4she345679hki7~gh012344gej2ybk=>?013bgg=tan:;<=>>ae`8wla789:;=lkm;rkd456788kmn6}fg123457e8k1xej>?0122f4d<{`m;<=>?1c0a?vo`89:;<<l<b:qjc56789;i8o5|if234566j<h0di?01235g0e3zcl<=>?00`4f>uno9:;<=?m8c9pmb6789::n4l4she345679kki7~gh012344dej2ybk=>?013agg=tan:;<=>>be`8wla789:;=okm;rkd456788hmn6}fg123457d8k1xej>?0122g4d<{`m;<=>?1b0a?vo`89:;<<m<b:qjc56789;h8o5|if234566k<h0di?01235f0e3zcl<=>?00a40>p6&9;:7ÎŲ½Ç¼ÔÈÁ¸À´¶Ú³¿·94ÎÎÉÌ»¹Êc3ØÈ´ÜÁ°ØºÄÁ¹¸¼c<Ù˵ÛÀ³ÙʻȿÁÀ{GHyh?n6NOx3c0>C<128qXhn4=288277<6;:=2n;4=3617k45?3;0b?<7:79'673=:;80q^jn:30:>4552898;4l9:31470=Tn109m;4?:0103<d12;9<?;5\d`81e3<72898;4l9:31472=Tn10:?=4;b082761>j?09?:=7;Rfb>4572=h:6<=<78`5>750;11o>l=50;395~Uck38957?<2;3072?e>388;>:4vU02f?6=93;1=n9tSea967?=9:81=>=89c496614<2.9><4ia:T163<5s|;9=7?4u001>5=z,8=>6<;4b3c0>5<?93;14<uG20d8 77b2;k87W6::2ya>f<6<3w/>?:52`38 f1=:h?0(il52`68 77>281/><6523c8m720290/>=o52548j76>2910e?:::18'65g=:=<0b?>6:098m724290/>=o52548j76>2;10e?:=:18'65g=:=<0b?>6:298m726290/>=o52548j76>2=10e?:?:18'65g=:=<0b?>6:498m75a290/>=o52548j76>2?10e?=j:18'65g=:=<0b?>6:698m75c290/>=o52548j76>2110e?=l:18'65g=:=<0b?>6:898m75e290/>=o52548j76>2h10e?=n:18'65g=:=<0b?>6:c98m75?290/>=o52548j76>2j10e?=8:18'65g=:=<0b?>6:e98m751290/>=o52548j76>2l10e?=::18'65g=:=<0b?>6:g98m753290/>=o52548j76>28:07d<<3;29 76f2;>=7c<?9;32?>o5;;0;6)<?a;072>h5800:>65f22394?"58h098;5a21;956=<a;9;6=4+21c9610<f;:26<:4;h01b?6=,;:j6?:9;o03=?7232c98h4?:%03e?43>2d9<44>6:9j61b=83.9<l4=479m65?=9>10e?:l:18'65g=:=<0b?>6:0:8?l43j3:1(?>n:365?k4713;276g=4`83>!47i38?:6`=0882e>=n:=31<7*=0`8103=i:931=o54i36;>5<#:9k1>984n32:>4e<3`8?87>5$32b>7213g8;57?k;:k17<<72-8;m7<;6:l14<<6m21b>?k50;&14d<5<?1e>=751g98m70?290/>=o52758j76>2910e?89:18'65g=:?=0b?>6:098m703290/>=o52758j76>2;10e?8<:18'65g=:?=0b?>6:298m705290/>=o52758j76>2=10e?8>:18'65g=:?=0b?>6:498m707290/>=o52758j76>2?10e?;i:18'65g=:?=0b?>6:698m73b290/>=o52758j76>2110e?;k:18'65g=:?=0b?>6:898m73d290/>=o52758j76>2h10e?;m:18'65g=:?=0b?>6:c98m73>290/>=o52758j76>2j10e?;7:18'65g=:?=0b?>6:e98m730290/>=o52758j76>2l10e?;9:18'65g=:?=0b?>6:g98m732290/>=o52758j76>28:07d<:4;29 76f2;<<7c<?9;32?>o5=:0;6)<?a;053>h5800:>65f24094?"58h09::5a21;956=<a;?:6=4+21c9631<f;:26<:4;h064?6=,;:j6?88;o03=?7232c9:k4?:%03e?41?2d9<44>6:9j63c=83.9<l4=669m65?=9>10e?8k:18'65g=:?=0b?>6:0:8?l41k3:1(?>n:344?k4713;276g=6c83>!47i38=;6`=0882e>=n:?k1<7*=0`8122=i:931=o54i34:>5<#:9k1>;94n32:>4e<3`8=97>5$32b>7003g8;57?k;:k11d<72-8;m7<97:l14<<6m21b>9h50;&14d<5>>1e>=751g98m7?>2900c?k::18'65g=:l>0b?>6:198k7c4290/>=o52d68j76>2810c?k=:18'65g=:l>0b?>6:398k7c6290/>=o52d68j76>2:10c?ji:18'65g=:l>0b?>6:598k7bb290/>=o52d68j76>2<10c?jk:18'65g=:l>0b?>6:798k7bd290/>=o52d68j76>2>10c?jm:18'65g=:l>0b?>6:998k7bf290/>=o52d68j76>2010c?j6:18'65g=:l>0b?>6:`98k7b?290/>=o52d68j76>2k10c?j8:18'65g=:l>0b?>6:b98k7b1290/>=o52d68j76>2m10c?j;:18'65g=:l>0b?>6:d98k7b4290/>=o52d68j76>2o10c?j=:18'65g=:l>0b?>6:028?j4c93:1(?>n:3g7?k4713;:76a=d183>!47i38n86`=08826>=h:jl1<7*=0`81a1=i:931=>54o3af>5<#:9k1>h:4n32:>42<3f8hh7>5$32b>7c33g8;57?:;:m1gf<72-8;m7<j4:l14<<6>21d>nl50;&14d<5m=1e>=751698k7e>290/>=o52d68j76>28207b<l8;29 76f2;o?7c<?9;3:?>i5k>0;6)<?a;0f0>h5800:m65`2b494?"58h09i95a21;95g=<g;i>6=4+21c96`2<f;:26<m4;n0`0?6=,;:j6?k;;o03=?7c32e9o>4?:%03e?4b<2d9<44>e:9l6f4=83.9<l4=e59m65?=9o10c?m>:18'65g=:l>0b?>6:328?j4d83:1(?>n:3g7?k47138:76a=bd83>!47i38n86`=08816>=h:kn1<7*=0`81a1=i:931>>54o3``>5<#:9k1>h:4n32:>72<3f8in7>5$32b>7c33g8;57<:;:m1fd<72-8;m7<j4:l14<<5>21d>o750;&14d<5m=1e>=752698k7d?290/>=o52d68j76>2;207b<m7;29 76f2;o?7c<?9;0:?>i5j?0;6)<?a;0f0>h58009m65`2c794?"58h09i95a21;96g=<g;h86=4+21c96`2<f;:26?m4;n0a6?6=,;:j6?k;;o03=?4c32e9n<4?:%03e?4b<2d9<44=e:9l6g6=83.9<l4=e59m65?=:o10c?oi:18'65g=:l>0b?>6:228?j4fm3:1(?>n:3g7?k47139:76a=ae83>!47i38n86`=08806>=h:hi1<7*=0`81a1=i:931?>54o3ca>5<#:9k1>h:4n32:>62<3f8jm7>5$32b>7c33g8;57=:;:m1a<<72-8;m7<j4:l14<<4>21d>h650;&14d<5m=1e>=753698k7c0290/>=o52d68j76>2:207b<j6;29 76f2;o?7c<?9;1:?>i5m90;6)<?a;0f0>h58008m65`2e794?"58h09i95a21;97g=<g;ij6=4+21c96`2<f;:26>m4;n0ab?6=,;:j6?k;;o03=?5c32e9n94?:%03e?4b<2d9<44<e:9l6d?=83.9<l4=e59m65?=;o10n?9?:18a1?4?28i<wE<>f:&15`<5i;1Q484:{88b>=<6;3;:6p*;b587f6=#<k?18o<4i2194?"58h08>6`=0883?>o493:1(?>n:208j76>2810e?h50;&14d<4:2d9<44=;:k1a?6=,;:j6><4n32:>6=<a;n1<7*=0`806>h5800?76g=c;29 76f2:80b?>6:498m7d=83.9<l4<2:l14<<132c9m7>5$32b>64<f;:26:54i3;94?"58h08>6`=088;?>o503:1(?>n:208j76>2010e?950;&14d<4:2d9<44n;:k12?6=,;:j6><4n32:>g=<a;>1<7*=0`806>h5800h76g=3;29 76f2:80b?>6:e98m74=83.9<l4<2:l14<<b32c9<7>5$32b>64<f;:26k54i0d94?"58h08>6`=08824>=n9l0;6)<?a;11?k4713;:76g>d;29 76f2:80b?>6:008?l7d290/>=o5339m65?=9:10e<l50;&14d<4:2d9<44>4:9j5d<72-8;m7==;o03=?7232c8m7>5$32b>64<f;:26<84;h1:>5<#:9k1??5a21;952=<a:21<7*=0`806>h5800:465f3683>!47i3997c<?9;3:?>o4>3:1(?>n:208j76>28k07d=::18'65g=;;1e>=751c98m62=83.9<l4<2:l14<<6k21b?=4?:%03e?553g8;57?k;:k11?6=,;:j6><4n32:>4c<3`;26=4+21c977=i:931=k54i4594?"58h0>:6`=0883?>o2=3:1(?>n:448j76>2810e8=50;&14d<2>2d9<44=;:k66?6=,;:j6884n32:>6=<a<;1<7*=0`862>h5800?76g:0;29 76f2<<0b?>6:498m1`=83.9<l4:6:l14<<132c?i7>5$32b>00<f;:26:54i5f94?"58h0>:6`=088;?>o3k3:1(?>n:448j76>2010e9l50;&14d<2>2d9<44n;:k7e?6=,;:j6884n32:>g=<a=21<7*=0`862>h5800h76g;7;29 76f2<<0b?>6:e98m10=83.9<l4:6:l14<<b32c?87>5$32b>00<f;:26k54i5194?"58h0>:6`=08824>=n<;0;6)<?a;75?k4713;:76g;1;29 76f2<<0b?>6:008?l27290/>=o5579m65?=9:10e>h50;&14d<2>2d9<44>4:9j7`<72-8;m7;9;o03=?7232c>i7>5$32b>00<f;:26<84;h7g>5<#:9k19;5a21;952=<a<i1<7*=0`862>h5800:465f5c83>!47i3?=7c<?9;3:?>o2i3:1(?>n:448j76>28k07d;6:18'65g==?1e>=751c98m0>=83.9<l4:6:l14<<6k21b994?:%03e?313g8;57?k;:k7=?6=,;:j6884n32:>4c<3`9o6=4+21c913=i:931=k54ib:94?=njl0;66g=1683>>i5:m0;6)<?a;01g>h5800;76a=2c83>!47i389o6`=0882?>i6?90;6)<?a;35b>h5800;76a>6d83>!47i3;=j6`=0882?>i6>m0;6)<?a;35b>h5800976a>6b83>!47i3;=j6`=0880?>i6>h0;6)<?a;35b>h5800?76a>6883>!47i3;=j6`=0886?>i6>10;6)<?a;35b>h5800=76a>6683>!47i3;=j6`=0884?>i6>?0;6)<?a;35b>h5800376a>6483>!47i3;=j6`=088:?>i6>=0;6)<?a;35b>h5800j76a>6283>!47i3;=j6`=088a?>i6>;0;6)<?a;35b>h5800h76a>6083>!47i3;=j6`=088g?>i6=o0;6)<?a;35b>h5800n76a>5d83>!47i3;=j6`=088e?>i6=m0;6)<?a;35b>h5800:<65`14`94?"58h0::k5a21;954=<g8?j6=4+21c953`<f;:26<<4;n36=?6=,;:j6<8i;o03=?7432e:954?:%03e?71n2d9<44>4:9l501=83.9<l4>6g9m65?=9<10c<;9:18'65g=9?l0b?>6:048?j72=3:1(?>n:04e?k4713;<76a>5283>!47i3;=j6`=0882<>=h9<81<7*=0`822c=i:931=454o072>5<#:9k1=;h4n32:>4g<3f;><7>5$32b>40a3g8;57?m;:m20c<72-8;m7?9f:l14<<6k21d=9k50;&14d<6>o1e>=751e98k42c290/>=o517d8j76>28o07b?;c;29 76f28<m7c<?9;3e?>i6<k0;6)<?a;35b>h58009<65`15c94?"58h0::k5a21;964=<g8>36=4+21c953`<f;:26?<4;n373?6=,;:j6<8i;o03=?4432e:8;4?:%03e?71n2d9<44=4:9l513=83.9<l4>6g9m65?=:<10c<:;:18'65g=9?l0b?>6:348?j73;3:1(?>n:04e?k47138<76a>4383>!47i3;=j6`=0881<>=h9=;1<7*=0`822c=i:931>454o063>5<#:9k1=;h4n32:>7g<3f;8j7>5$32b>40a3g8;57<m;:m27a<72-8;m7?9f:l14<<5k21d=>m50;&14d<6>o1e>=752e98k45e290/>=o517d8j76>2;o07b?<a;29 76f28<m7c<?9;0e?>i6;00;6)<?a;35b>h58008<65`12:94?"58h0::k5a21;974=<g89<6=4+21c953`<f;:26><4;n302?6=,;:j6<8i;o03=?5432e:?84?:%03e?71n2d9<44<4:9l562=83.9<l4>6g9m65?=;<10c<9;:18'65g=9?l0b?>6:248?j70;3:1(?>n:04e?k47139<76a>7383>!47i3;=j6`=0880<>=h9>;1<7*=0`822c=i:931?454o04a>5<#:9k1=;h4n32:>6g<3f;=<7>5$32b>40a3g8;57=m;:m211<72-8;m7?9f:l14<<4k21d=9750;&14d<6>o1e>=753e98k45b290/>=o517d8j76>2:o07b?<3;29 76f28<m7c<?9;1e?>i6i90;6)<?a;3:b>h5800;76a>9d83>!47i3;2j6`=0882?>i61m0;6)<?a;3:b>h5800976a>9b83>!47i3;2j6`=0880?>i61k0;6)<?a;3:b>h5800?76a>9`83>!47i3;2j6`=0886?>i6100;6)<?a;3:b>h5800=76a>9983>!47i3;2j6`=0884?>i61?0;6)<?a;3:b>h5800376a>9483>!47i3;2j6`=088:?>i61=0;6)<?a;3:b>h5800j76a>9283>!47i3;2j6`=088a?>i61;0;6)<?a;3:b>h5800h76a>9083>!47i3;2j6`=088g?>i6190;6)<?a;3:b>h5800n76a>8g83>!47i3;2j6`=088e?>i60l0;6)<?a;3:b>h5800:<65`19f94?"58h0:5k5a21;954=<g82i6=4+21c95<`<f;:26<<4;n3;e?6=,;:j6<7i;o03=?7432e:444?:%03e?7>n2d9<44>4:9l5=>=83.9<l4>9g9m65?=9<10c<68:18'65g=90l0b?>6:048?j7?>3:1(?>n:0;e?k4713;<76a>8483>!47i3;2j6`=0882<>=h91>1<7*=0`82=c=i:931=454o0:0>5<#:9k1=4h4n32:>4g<3f;3>7>5$32b>4?a3g8;57?m;:m2<5<72-8;m7?6f:l14<<6k21d=:h50;&14d<61o1e>=751e98k41b290/>=o518d8j76>28o07b?8d;29 76f283m7c<?9;3e?>i6?j0;6)<?a;3:b>h58009<65`16`94?"58h0:5k5a21;964=<g8=j6=4+21c95<`<f;:26?<4;n34=?6=,;:j6<7i;o03=?4432e:;54?:%03e?7>n2d9<44=4:9l521=83.9<l4>9g9m65?=:<10c<o9:18'65g=90l0b?>6:348?j7f=3:1(?>n:0;e?k47138<76a>a583>!47i3;2j6`=0881<>=h9h91<7*=0`82=c=i:931>454o0c1>5<#:9k1=4h4n32:>7g<3f;j=7>5$32b>4?a3g8;57<m;:m2=2<72-8;m7?6f:l14<<5k21d=5m50;&14d<61o1e>=752e98k4>6290/>=o518d8j76>2;o07b?86;29 76f283m7c<?9;0e?>d5?80;6<4?:1y'64c=:;:0D?<<;I02b>i6;80;66sm26094?7=83:p(??j:g48L7443A8:j6ai5;29?xd5?:0;6<;n:183!46m3l87E<=3:J15c=]0<0iw<857;31>c<22=0n6<>56;19`?{#9;l1>l94n0594>h603;0b>l50:l0g?6<fk31<6*ma;310>hcl3:0bk<50:l265<73g;9i7>4n32a>4=#:8<1><j4ncf94>od:3:17d<>0;29?l4693:17dm<:188m7752900en;50;9jg4<722eio7>5;h020?6=3`8:?7>5;ha;>5<<a;:m6=44ib694?=nk90;66gm8;29?le12900eoh50;9lfg<722c9<h4?::k150<722c?:7>5$32b>13<f;:26=54i5694?"58h0?96`=0882?>o3;3:1(?>n:578j76>2;10e9<50;&14d<3=2d9<44<;:k75?6=,;:j69;4n32:>1=<a=:1<7*=0`871>h5800>76g<f;29 76f2=?0b?>6:798m6c=83.9<l4;5:l14<<032c>i7>5$32b>13<f;:26554i4f94?"58h0?96`=088:?>o2k3:1(?>n:578j76>2h10e8l50;&14d<3=2d9<44m;:k6e?6=,;:j69;4n32:>f=<a<31<7*=0`871>h5800o76g:8;29 76f2=?0b?>6:d98m02=83.9<l4;5:l14<<a32c?57>5$32b>13<f;:26<>4;h1g>5<#:9k1885a21;954=<g>h1<7*=0`84e>h5800;76a89;29 76f2>k0b?>6:098k2>=83.9<l48a:l14<<532e<;7>5$32b>2g<f;:26>54o6494?"58h0<m6`=0887?>i0=3:1(?>n:6c8j76>2<10c::50;&14d<0i2d9<449;:m47?6=,;:j6:o4n32:>2=<g1>1<7*=0`84e>h5800376a73;29 76f2>k0b?>6:898k=4=83.9<l48a:l14<<f32e3=7>5$32b>2g<f;:26o54o9294?"58h0<m6`=088`?>i0n3:1(?>n:6c8j76>2m10c:k50;&14d<0i2d9<44j;:m4`?6=,;:j6:o4n32:>c=<g>i1<7*=0`84e>h5800:<65`7383>!47i3=j7c<?9;32?>o6l80;6)<?a;3g4>h5800;76g>cg83>!47i3;o<6`=0882?>o6kl0;6)<?a;3g4>h5800976g>ce83>!47i3;o<6`=0880?>o6kj0;6)<?a;3g4>h5800?76g>cc83>!47i3;o<6`=0886?>o6kh0;6)<?a;3g4>h5800=76g>c883>!47i3;o<6`=0884?>o6k>0;6)<?a;3g4>h5800376g>c783>!47i3;o<6`=088:?>o6k<0;6)<?a;3g4>h5800j76g>c583>!47i3;o<6`=088a?>o6k:0;6)<?a;3g4>h5800h76g>c383>!47i3;o<6`=088g?>o6k80;6)<?a;3g4>h5800n76g>c183>!47i3;o<6`=088e?>o6jo0;6)<?a;3g4>h5800:<65f1cg94?"58h0:h=5a21;954=<a8hh6=4+21c95a6<f;:26<<4;h3af?6=,;:j6<j?;o03=?7432c:nl4?:%03e?7c82d9<44>4:9j5g?=83.9<l4>d19m65?=9<10e<l7:18'65g=9m:0b?>6:048?l7e?3:1(?>n:0f3?k4713;<76g>b783>!47i3;o<6`=0882<>=n9k?1<7*=0`82`5=i:931=454i0`7>5<#:9k1=i>4n32:>4g<3`;i?7>5$32b>4b73g8;57?m;:k2f4<72-8;m7?k0:l14<<6k21b=o>50;&14d<6l91e>=751e98m4ga290/>=o51e28j76>28o07d?ne;29 76f28n;7c<?9;3e?>o6im0;6)<?a;3g4>h58009<65f1`a94?"58h0:h=5a21;964=<a8ki6=4+21c95a6<f;:26?<4;h3be?6=,;:j6<j?;o03=?4432c:m44?:%03e?7c82d9<44=4:9j5d>=83.9<l4>d19m65?=:<10e<j8:18'65g=9m:0b?>6:348?l7c>3:1(?>n:0f3?k47138<76g>d483>!47i3;o<6`=0881<>=n9m>1<7*=0`82`5=i:931>454i0f0>5<#:9k1=i>4n32:>7g<3`;o>7>5$32b>4b73g8;57<m;:k2g=<72-8;m7?k0:l14<<5k21b=oj50;&14d<6l91e>=752e98m4d5290/>=o51e28j76>2;o07d?n7;29 76f28n;7c<?9;0e?>oe93:1(?>n:c28j76>2910elh50;&14d<e82d9<44>;:kba?6=,;:j6o>4n32:>7=<ahn1<7*=0`8a4>h5800876gnc;29 76f2k:0b?>6:598mdd=83.9<l4m0:l14<<232cjm7>5$32b>g6<f;:26;54i`;94?"58h0i<6`=0884?>of?3:1(?>n:c28j76>2110el850;&14d<e82d9<446;:kb1?6=,;:j6o>4n32:>d=<ah>1<7*=0`8a4>h5800i76gn3;29 76f2k:0b?>6:b98md4=83.9<l4m0:l14<<c32cj=7>5$32b>g6<f;:26h54i`294?"58h0i<6`=088e?>o>n3:1(?>n:c28j76>28:07d7j:18'65g=j91e>=751098m<e=83.9<l4m0:l14<<6:21b5o4?:%03e?d73g8;57?<;:k:e?6=,;:j6o>4n32:>42<3`326=4+21c9f5=i:931=854i8:94?"58h0i<6`=08822>=n1>0;6)<?a;`3?k4713;<76g66;29 76f2k:0b?>6:0:8?l?2290/>=o5b19m65?=9010e4:50;&14d<e82d9<44>a:9j=6<72-8;m7l?;o03=?7e32c2=7>5$32b>g6<f;:26<m4;h;3>5<#:9k1n=5a21;95a=<a1l1<7*=0`8a4>h5800:i65f8d83>!47i3h;7c<?9;3e?>o?l3:1(?>n:c28j76>2;:07d6l:18'65g=j91e>=752098m=d=83.9<l4m0:l14<<5:21b4l4?:%03e?d73g8;57<<;:k;=?6=,;:j6o>4n32:>72<3`236=4+21c9f5=i:931>854ic594?"58h0i<6`=08812>=nj?0;6)<?a;`3?k47138<76gm5;29 76f2k:0b?>6:3:8?ld3290/>=o5b19m65?=:010eo=50;&14d<e82d9<44=a:9jf7<72-8;m7l?;o03=?4e32cj47>5$32b>g6<f;:26?m4;h;g>5<#:9k1n=5a21;96a=<a081<7*=0`8a4>h58009i65f8683>!47i3h;7c<?9;0e?>i6=m0;6)<?a;36g>h5800;76a>5c83>!47i3;>o6`=0882?>i6=h0;6)<?a;36g>h5800976a>5883>!47i3;>o6`=0880?>i6=10;6)<?a;36g>h5800?76a>5683>!47i3;>o6`=0886?>i6=?0;6)<?a;36g>h5800=76a>5483>!47i3;>o6`=0884?>i6=:0;6)<?a;36g>h5800376a>5383>!47i3;>o6`=088:?>i6=80;6)<?a;36g>h5800j76a>5183>!47i3;>o6`=088a?>i6<o0;6)<?a;36g>h5800h76a>4d83>!47i3;>o6`=088g?>i6<m0;6)<?a;36g>h5800n76a>4b83>!47i3;>o6`=088e?>i6<k0;6)<?a;36g>h5800:<65`15c94?"58h0:9n5a21;954=<g8>36=4+21c950e<f;:26<<4;n373?6=,;:j6<;l;o03=?7432e:8;4?:%03e?72k2d9<44>4:9l513=83.9<l4>5b9m65?=9<10c<:;:18'65g=9<i0b?>6:048?j73;3:1(?>n:07`?k4713;<76a>4383>!47i3;>o6`=0882<>=h9=;1<7*=0`821f=i:931=454o063>5<#:9k1=8m4n32:>4g<3f;8j7>5$32b>43d3g8;57?m;:m27a<72-8;m7?:c:l14<<6k21d=>m50;&14d<6=j1e>=751e98k45e290/>=o514a8j76>28o07b?<a;29 76f28?h7c<?9;3e?>i6;00;6)<?a;36g>h58009<65`12:94?"58h0:9n5a21;964=<g89<6=4+21c950e<f;:26?<4;n302?6=,;:j6<;l;o03=?4432e:?84?:%03e?72k2d9<44=4:9l562=83.9<l4>5b9m65?=:<10c<9;:18'65g=9<i0b?>6:348?j70;3:1(?>n:07`?k47138<76a>7383>!47i3;>o6`=0881<>=h9>;1<7*=0`821f=i:931>454o04a>5<#:9k1=8m4n32:>7g<3f;=<7>5$32b>43d3g8;57<m;:m211<72-8;m7?:c:l14<<5k21d=9750;&14d<6=j1e>=752e98k45b290/>=o514a8j76>2;o07b?<3;29 76f28?h7c<?9;0e?>o6:m0;6)<?a;31g>h5800;76g>2c83>!47i3;9o6`=0882?>o6:h0;6)<?a;31g>h5800976g>2883>!47i3;9o6`=0880?>o6:10;6)<?a;31g>h5800?76g>2683>!47i3;9o6`=0886?>o6:?0;6)<?a;31g>h5800=76g>2483>!47i3;9o6`=0884?>ob03:1(?>n:d58j76>2910eh850;&14d<b?2d9<44>;:kf1?6=,;:j6h94n32:>7=<al>1<7*=0`8f3>h5800876gj3;29 76f2l=0b?>6:598m`4=83.9<l4j7:l14<<232cn=7>5$32b>`1<f;:26;54id294?"58h0n;6`=0884?>oa93:1(?>n:d58j76>2110ek>50;&14d<b?2d9<446;:kfb?6=,;:j6h94n32:>d=<alo1<7*=0`8f3>h5800i76gjd;29 76f2l=0b?>6:b98m`e=83.9<l4j7:l14<<c32cnn7>5$32b>`1<f;:26h54idc94?"58h0n;6`=088e?>ob13:1(?>n:d58j76>28:07dji:18'65g=m>1e>=751098k765290/>=o52138j76>2910c?>?:18'65g=:9;0b?>6:098k4`a290/>=o52138j76>2;10c<hj:18'65g=:9;0b?>6:298k4`c290/>=o52138j76>2=10c<hl:18'65g=:9;0b?>6:498k4`e290/>=o52138j76>2?10c<hn:18'65g=:9;0b?>6:698k4`?290/>=o52138j76>2110c<h8:18'65g=:9;0b?>6:898k4`1290/>=o52138j76>2h10c<h::18'65g=:9;0b?>6:c98k4`3290/>=o52138j76>2j10c<h<:18'65g=:9;0b?>6:e98k4`5290/>=o52138j76>2l10c<h>:18'65g=:9;0b?>6:g98k4`7290/>=o52138j76>28:07b?jf;29 76f2;::7c<?9;32?>i6mm0;6)<?a;035>h5800:>65`1da94?"58h09<<5a21;956=<g8oi6=4+21c9657<f;:26<:4;n3fe?6=,;:j6?>>;o03=?7232e:i44?:%03e?4792d9<44>6:9l5`>=83.9<l4=009m65?=9>10c<k8:18'65g=:9;0b?>6:0:8?j7b>3:1(?>n:322?k4713;276a>e483>!47i38;=6`=0882e>=h9l>1<7*=0`8144=i:931=o54o0g1>5<#:9k1>=?4n32:>4e<3f;n=7>5$32b>7663g8;57?k;:m2a5<72-8;m7<?1:l14<<6m21d=ih50;&14d<5881e>=751g98k4bb290/>=o52138j76>2;:07b?kd;29 76f2;::7c<?9;02?>i6lj0;6)<?a;035>h58009>65`1e`94?"58h09<<5a21;966=<g8nj6=4+21c9657<f;:26?:4;n3g=?6=,;:j6?>>;o03=?4232e9<54?:%03e?4792d9<44=6:9l651=83.9<l4=009m65?=:>10c?>9:18'65g=:9;0b?>6:3:8?j47=3:1(?>n:322?k47138276a=0583>!47i38;=6`=0881e>=h:991<7*=0`8144=i:931>o54o0d:>5<#:9k1>=?4n32:>7e<3f;ni7>5$32b>7663g8;57<k;:m2a6<72-8;m7<?1:l14<<5m21d=i650;&14d<5881e>=752g98m74=83.9<l4=1:l14<<732c9<7>5$32b>77<f;:26<54i0d94?"58h09=6`=0881?>o6m3:1(?>n:338j76>2:10e<j50;&14d<592d9<44;;:k2g?6=,;:j6??4n32:>0=<a8h1<7*=0`815>h5800=76g>a;29 76f2;;0b?>6:698m6g=83.9<l4=1:l14<<?32c857>5$32b>77<f;:26454i2:94?"58h09=6`=088b?>o4?3:1(?>n:338j76>2k10e>850;&14d<592d9<44l;:k01?6=,;:j6??4n32:>a=<a:>1<7*=0`815>h5800n76g<0;29 76f2;;0b?>6:g98m73=83.9<l4=1:l14<<6821b=44?:%03e?463g8;57?>;:m25=<72-8;m7?>7:l14<<732e:=;4?:%03e?76?2d9<44>;:m250<72-8;m7?>7:l14<<532e:=94?:%03e?76?2d9<44<;:m256<72-8;m7?>7:l14<<332e:=?4?:%03e?76?2d9<44:;:m255<72-8;m7?>7:l14<<132e:<k4?:%03e?76?2d9<448;:m24`<72-8;m7?>7:l14<<?32e:<i4?:%03e?76?2d9<446;:m24f<72-8;m7?>7:l14<<f32e:<o4?:%03e?76?2d9<44m;:m24d<72-8;m7?>7:l14<<d32e:<44?:%03e?76?2d9<44k;:m24=<72-8;m7?>7:l14<<b32e:<:4?:%03e?76?2d9<44i;:m240<72-8;m7?>7:l14<<6821d==:50;&14d<69>1e>=751098k464290/>=o51058j76>28807b??2;29 76f28;<7c<?9;30?>i6880;6)<?a;323>h5800:865`11294?"58h0:=:5a21;950=<gol1<7*=0`8252=i:931=;54ogg94?"58h0:=:5a21;952=<gon1<7*=0`8252=i:931=554oga94?"58h0:=:5a21;95<=<g8;m6=4+21c9541<f;:26<o4;n32a?6=,;:j6<?8;o03=?7e32e:=i4?:%03e?76?2d9<44>c:9l54e=83.9<l4>169m65?=9m10c<?m:18'65g=98=0b?>6:0g8?j76i3:1(?>n:034?k4713;m76a>1883>!47i3;:;6`=08814>=h98;1<7*=0`8252=i:931><54o025>5<#:9k1=<94n32:>74<3fli6=4+21c9541<f;:26?=4;h4;>5<#:9k1::5a21;94>N59h10e;850;&14d<1?2d9<44>;I02e>=n><0;6)<?a;44?k471380D??n;:k50?6=,;:j6;94n32:>6=O:8k07d8<:18'65g=>>1e>=754:J15d=<a?81<7*=0`853>h5800>7E<>a:9j24<72-8;m788;o03=?0<@;;j76g90;29 76f2?=0b?>6:69K64g<3`=:6=4+21c922=i:93146F=1`98m26=83.9<l497:l14<<>3A8:m65f6g83>!47i3<<7c<?9;c8L77f32c=i7>5$32b>31<f;:26o5G20c8?l0c290/>=o5669m65?=k2B9=l54i7a94?"58h0=;6`=088g?M46i21b:o4?:%03e?003g8;57k4H33b?>o1i3:1(?>n:758j76>2o1C><o4;h4:>5<#:9k1::5a21;955=O:8k07d;i:18'65g=>>1e>=75109K64g<3th9;94?:07b>5<7s-8:i7h<;I017>N59o1Q484m{0493?752o0>694j:0292?5=l3w/=?h52`58j41=82d:47?4n2`94>h4k3:0bo750:&ae?75<2doh7>4ng094>h6:90;7c?=e;28j76e291/><8520f8jgb=82ch>7>5;h024?6=3`8:=7>5;ha0>5<<a;;96=44ib794?=nk80;66amc;29?l46<3:17d<>3;29?le?2900e?>i:188mf2=831bo=4?::ka<?6=3`i=6=44icd94?=hjk0;66g=0d83>>o59<0;66g;6;29 76f2=?0b?>6:198m12=83.9<l4;5:l14<<632c??7>5$32b>13<f;:26?54i5094?"58h0?96`=0880?>o393:1(?>n:578j76>2=10e9>50;&14d<3=2d9<44:;:k0b?6=,;:j69;4n32:>3=<a:o1<7*=0`871>h5800<76g:e;29 76f2=?0b?>6:998m0b=83.9<l4;5:l14<<>32c>o7>5$32b>13<f;:26l54i4`94?"58h0?96`=088a?>o2i3:1(?>n:578j76>2j10e8750;&14d<3=2d9<44k;:k6<?6=,;:j69;4n32:>`=<a<>1<7*=0`871>h5800m76g;9;29 76f2=?0b?>6:028?l5c290/>=o5449m65?=9810c:l50;&14d<0i2d9<44?;:m4=?6=,;:j6:o4n32:>4=<g>21<7*=0`84e>h5800976a87;29 76f2>k0b?>6:298k20=83.9<l48a:l14<<332e<97>5$32b>2g<f;:26854o6694?"58h0<m6`=0885?>i0;3:1(?>n:6c8j76>2>10c5:50;&14d<0i2d9<447;:m;7?6=,;:j6:o4n32:><=<g181<7*=0`84e>h5800j76a71;29 76f2>k0b?>6:c98k=6=83.9<l48a:l14<<d32e<j7>5$32b>2g<f;:26i54o6g94?"58h0<m6`=088f?>i0l3:1(?>n:6c8j76>2o10c:m50;&14d<0i2d9<44>0:9l37<72-8;m79n;o03=?7632c:h<4?:%03e?7c82d9<44?;:k2gc<72-8;m7?k0:l14<<632c:oh4?:%03e?7c82d9<44=;:k2ga<72-8;m7?k0:l14<<432c:on4?:%03e?7c82d9<44;;:k2gg<72-8;m7?k0:l14<<232c:ol4?:%03e?7c82d9<449;:k2g<<72-8;m7?k0:l14<<032c:o:4?:%03e?7c82d9<447;:k2g3<72-8;m7?k0:l14<<>32c:o84?:%03e?7c82d9<44n;:k2g1<72-8;m7?k0:l14<<e32c:o>4?:%03e?7c82d9<44l;:k2g7<72-8;m7?k0:l14<<c32c:o<4?:%03e?7c82d9<44j;:k2g5<72-8;m7?k0:l14<<a32c:nk4?:%03e?7c82d9<44>0:9j5gc=83.9<l4>d19m65?=9810e<ll:18'65g=9m:0b?>6:008?l7ej3:1(?>n:0f3?k4713;876g>b`83>!47i3;o<6`=08820>=n9k31<7*=0`82`5=i:931=854i0`;>5<#:9k1=i>4n32:>40<3`;i;7>5$32b>4b73g8;57?8;:k2f3<72-8;m7?k0:l14<<6021b=o;50;&14d<6l91e>=751898m4d3290/>=o51e28j76>28k07d?m3;29 76f28n;7c<?9;3a?>o6j80;6)<?a;3g4>h5800:o65f1c294?"58h0:h=5a21;95a=<a8km6=4+21c95a6<f;:26<k4;h3ba?6=,;:j6<j?;o03=?7a32c:mi4?:%03e?7c82d9<44=0:9j5de=83.9<l4>d19m65?=:810e<om:18'65g=9m:0b?>6:308?l7fi3:1(?>n:0f3?k47138876g>a883>!47i3;o<6`=08810>=n9h21<7*=0`82`5=i:931>854i0f4>5<#:9k1=i>4n32:>70<3`;o:7>5$32b>4b73g8;57<8;:k2`0<72-8;m7?k0:l14<<5021b=i:50;&14d<6l91e>=752898m4b4290/>=o51e28j76>2;k07d?k2;29 76f28n;7c<?9;0a?>o6k10;6)<?a;3g4>h58009o65f1cf94?"58h0:h=5a21;96a=<a8h96=4+21c95a6<f;:26?k4;h3b3?6=,;:j6<j?;o03=?4a32ci=7>5$32b>g6<f;:26=54i`d94?"58h0i<6`=0882?>ofm3:1(?>n:c28j76>2;10elj50;&14d<e82d9<44<;:kbg?6=,;:j6o>4n32:>1=<ahh1<7*=0`8a4>h5800>76gna;29 76f2k:0b?>6:798md?=83.9<l4m0:l14<<032cj;7>5$32b>g6<f;:26554i`494?"58h0i<6`=088:?>of=3:1(?>n:c28j76>2h10el:50;&14d<e82d9<44m;:kb7?6=,;:j6o>4n32:>f=<ah81<7*=0`8a4>h5800o76gn1;29 76f2k:0b?>6:d98md6=83.9<l4m0:l14<<a32c2j7>5$32b>g6<f;:26<>4;h;f>5<#:9k1n=5a21;954=<a0i1<7*=0`8a4>h5800:>65f9c83>!47i3h;7c<?9;30?>o>i3:1(?>n:c28j76>28>07d76:18'65g=j91e>=751498m<>=83.9<l4m0:l14<<6>21b5:4?:%03e?d73g8;57?8;:k:2?6=,;:j6o>4n32:>4><3`3>6=4+21c9f5=i:931=454i8694?"58h0i<6`=0882e>=n1:0;6)<?a;`3?k4713;i76g61;29 76f2k:0b?>6:0a8?l?7290/>=o5b19m65?=9m10e5h50;&14d<e82d9<44>e:9j<`<72-8;m7l?;o03=?7a32c3h7>5$32b>g6<f;:26?>4;h:`>5<#:9k1n=5a21;964=<a1h1<7*=0`8a4>h58009>65f8`83>!47i3h;7c<?9;00?>o?13:1(?>n:c28j76>2;>07d67:18'65g=j91e>=752498mg1=83.9<l4m0:l14<<5>21bn;4?:%03e?d73g8;57<8;:ka1?6=,;:j6o>4n32:>7><3`h?6=4+21c9f5=i:931>454ic194?"58h0i<6`=0881e>=nj;0;6)<?a;`3?k47138i76gn8;29 76f2k:0b?>6:3a8?l?c290/>=o5b19m65?=:m10e4<50;&14d<e82d9<44=e:9j<2<72-8;m7l?;o03=?4a32e:9i4?:%03e?72k2d9<44?;:m21g<72-8;m7?:c:l14<<632e:9l4?:%03e?72k2d9<44=;:m21<<72-8;m7?:c:l14<<432e:954?:%03e?72k2d9<44;;:m212<72-8;m7?:c:l14<<232e:9;4?:%03e?72k2d9<449;:m210<72-8;m7?:c:l14<<032e:9>4?:%03e?72k2d9<447;:m217<72-8;m7?:c:l14<<>32e:9<4?:%03e?72k2d9<44n;:m215<72-8;m7?:c:l14<<e32e:8k4?:%03e?72k2d9<44l;:m20`<72-8;m7?:c:l14<<c32e:8i4?:%03e?72k2d9<44j;:m20f<72-8;m7?:c:l14<<a32e:8o4?:%03e?72k2d9<44>0:9l51g=83.9<l4>5b9m65?=9810c<:7:18'65g=9<i0b?>6:008?j73?3:1(?>n:07`?k4713;876a>4783>!47i3;>o6`=08820>=h9=?1<7*=0`821f=i:931=854o067>5<#:9k1=8m4n32:>40<3f;??7>5$32b>43d3g8;57?8;:m207<72-8;m7?:c:l14<<6021d=9?50;&14d<6=j1e>=751898k427290/>=o514a8j76>28k07b?<f;29 76f28?h7c<?9;3a?>i6;m0;6)<?a;36g>h5800:o65`12a94?"58h0:9n5a21;95a=<g89i6=4+21c950e<f;:26<k4;n30e?6=,;:j6<;l;o03=?7a32e:?44?:%03e?72k2d9<44=0:9l56>=83.9<l4>5b9m65?=:810c<=8:18'65g=9<i0b?>6:308?j74>3:1(?>n:07`?k47138876a>3483>!47i3;>o6`=08810>=h9:>1<7*=0`821f=i:931>854o057>5<#:9k1=8m4n32:>70<3f;<?7>5$32b>43d3g8;57<8;:m237<72-8;m7?:c:l14<<5021d=:?50;&14d<6=j1e>=752898k40e290/>=o514a8j76>2;k07b?90;29 76f28?h7c<?9;0a?>i6==0;6)<?a;36g>h58009o65`15;94?"58h0:9n5a21;96a=<g89n6=4+21c950e<f;:26?k4;n307?6=,;:j6<;l;o03=?4a32c:>i4?:%03e?75k2d9<44?;:k26g<72-8;m7?=c:l14<<632c:>l4?:%03e?75k2d9<44=;:k26<<72-8;m7?=c:l14<<432c:>54?:%03e?75k2d9<44;;:k262<72-8;m7?=c:l14<<232c:>;4?:%03e?75k2d9<449;:k260<72-8;m7?=c:l14<<032cn47>5$32b>`1<f;:26=54id494?"58h0n;6`=0882?>ob=3:1(?>n:d58j76>2;10eh:50;&14d<b?2d9<44<;:kf7?6=,;:j6h94n32:>1=<al81<7*=0`8f3>h5800>76gj1;29 76f2l=0b?>6:798m`6=83.9<l4j7:l14<<032cm=7>5$32b>`1<f;:26554ig294?"58h0n;6`=088:?>obn3:1(?>n:d58j76>2h10ehk50;&14d<b?2d9<44m;:kf`?6=,;:j6h94n32:>f=<ali1<7*=0`8f3>h5800o76gjb;29 76f2l=0b?>6:d98m`g=83.9<l4j7:l14<<a32cn57>5$32b>`1<f;:26<>4;hfe>5<#:9k1i:5a21;954=<g;:96=4+21c9657<f;:26=54o323>5<#:9k1>=?4n32:>4=<g8lm6=4+21c9657<f;:26?54o0df>5<#:9k1>=?4n32:>6=<g8lo6=4+21c9657<f;:26954o0d`>5<#:9k1>=?4n32:>0=<g8li6=4+21c9657<f;:26;54o0db>5<#:9k1>=?4n32:>2=<g8l36=4+21c9657<f;:26554o0d4>5<#:9k1>=?4n32:><=<g8l=6=4+21c9657<f;:26l54o0d6>5<#:9k1>=?4n32:>g=<g8l?6=4+21c9657<f;:26n54o0d0>5<#:9k1>=?4n32:>a=<g8l96=4+21c9657<f;:26h54o0d2>5<#:9k1>=?4n32:>c=<g8l;6=4+21c9657<f;:26<>4;n3fb?6=,;:j6?>>;o03=?7632e:ii4?:%03e?4792d9<44>2:9l5`e=83.9<l4=009m65?=9:10c<km:18'65g=:9;0b?>6:068?j7bi3:1(?>n:322?k4713;>76a>e883>!47i38;=6`=08822>=h9l21<7*=0`8144=i:931=:54o0g4>5<#:9k1>=?4n32:>4><3f;n:7>5$32b>7663g8;57?6;:m2a0<72-8;m7<?1:l14<<6i21d=h:50;&14d<5881e>=751c98k4c5290/>=o52138j76>28i07b?j1;29 76f2;::7c<?9;3g?>i6m90;6)<?a;035>h5800:i65`1ed94?"58h09<<5a21;95c=<g8nn6=4+21c9657<f;:26?>4;n3g`?6=,;:j6?>>;o03=?4632e:hn4?:%03e?4792d9<44=2:9l5ad=83.9<l4=009m65?=::10c<jn:18'65g=:9;0b?>6:368?j7c13:1(?>n:322?k47138>76a=0983>!47i38;=6`=08812>=h:9=1<7*=0`8144=i:931>:54o325>5<#:9k1>=?4n32:>7><3f8;97>5$32b>7663g8;57<6;:m141<72-8;m7<?1:l14<<5i21d>==50;&14d<5881e>=752c98k4`>290/>=o52138j76>2;i07b?je;29 76f2;::7c<?9;0g?>i6m:0;6)<?a;035>h58009i65`1e:94?"58h09<<5a21;96c=<a;81<7*=0`815>h5800;76g=0;29 76f2;;0b?>6:098m4`=83.9<l4=1:l14<<532c:i7>5$32b>77<f;:26>54i0f94?"58h09=6`=0887?>o6k3:1(?>n:338j76>2<10e<l50;&14d<592d9<449;:k2e?6=,;:j6??4n32:>2=<a:k1<7*=0`815>h5800376g<9;29 76f2;;0b?>6:898m6>=83.9<l4=1:l14<<f32c8;7>5$32b>77<f;:26o54i2494?"58h09=6`=088`?>o4=3:1(?>n:338j76>2m10e>:50;&14d<592d9<44j;:k04?6=,;:j6??4n32:>c=<a;?1<7*=0`815>h5800:<65f1883>!47i38:7c<?9;32?>i6910;6)<?a;323>h5800;76a>1783>!47i3;:;6`=0882?>i69<0;6)<?a;323>h5800976a>1583>!47i3;:;6`=0880?>i69:0;6)<?a;323>h5800?76a>1383>!47i3;:;6`=0886?>i6990;6)<?a;323>h5800=76a>0g83>!47i3;:;6`=0884?>i68l0;6)<?a;323>h5800376a>0e83>!47i3;:;6`=088:?>i68j0;6)<?a;323>h5800j76a>0c83>!47i3;:;6`=088a?>i68h0;6)<?a;323>h5800h76a>0883>!47i3;:;6`=088g?>i6810;6)<?a;323>h5800n76a>0683>!47i3;:;6`=088e?>i68<0;6)<?a;323>h5800:<65`11694?"58h0:=:5a21;954=<g8:86=4+21c9541<f;:26<<4;n336?6=,;:j6<?8;o03=?7432e:<<4?:%03e?76?2d9<44>4:9l556=83.9<l4>169m65?=9<10ckh50;&14d<69>1e>=751798kcc=83.9<l4>169m65?=9>10ckj50;&14d<69>1e>=751998kce=83.9<l4>169m65?=9010c<?i:18'65g=98=0b?>6:0c8?j76m3:1(?>n:034?k4713;i76a>1e83>!47i3;:;6`=0882g>=h98i1<7*=0`8252=i:931=i54o03a>5<#:9k1=<94n32:>4c<3f;:m7>5$32b>4703g8;57?i;:m25<<72-8;m7?>7:l14<<5821d=<?50;&14d<69>1e>=752098k461290/>=o51058j76>2;807bhm:18'65g=98=0b?>6:318?l0?290/>=o5669m65?=82B9=l54i7494?"58h0=;6`=0882?M46i21b:84?:%03e?003g8;57<4H33b?>o1<3:1(?>n:758j76>2:1C><o4;h40>5<#:9k1::5a21;90>N59h10e;<50;&14d<1?2d9<44:;I02e>=n>80;6)<?a;44?k4713<0D??n;:k54?6=,;:j6;94n32:>2=O:8k07d9>:18'65g=>>1e>=758:J15d=<a>:1<7*=0`853>h580027E<>a:9j2c<72-8;m788;o03=?g<@;;j76g9e;29 76f2?=0b?>6:c9K64g<3`<o6=4+21c922=i:931o6F=1`98m3e=83.9<l497:l14<<c3A8:m65f6c83>!47i3<<7c<?9;g8L77f32c=m7>5$32b>31<f;:26k5G20c8?l0>290/>=o5669m65?=991C><o4;h7e>5<#:9k1::5a21;954=O:8k07pl=7483>43f290;w)<>e;d0?M45;2B9=k5U848a40=?3;96k4::58f>46=>391h7s+13d96d1<f8=1<6`>8;38j6d=82d8o7?4nc;94>"ei3;986`kd;28jc4=82d:>=4?;o31a?6<f;:i6=5+204964b<fkn1<6gl2;29?l4683:17d<>1;29?le42900e??=:188mf3=831bo<4?::mag?6=3`8:87>5;h027?6=3`i36=44i32e>5<<aj>1<75fc183>>oe03:17dm9:188mg`=831dno4?::k14`<722c9=84?::k72?6=,;:j69;4n32:>5=<a=>1<7*=0`871>h5800:76g;3;29 76f2=?0b?>6:398m14=83.9<l4;5:l14<<432c?=7>5$32b>13<f;:26954i5294?"58h0?96`=0886?>o4n3:1(?>n:578j76>2?10e>k50;&14d<3=2d9<448;:k6a?6=,;:j69;4n32:>==<a<n1<7*=0`871>h5800276g:c;29 76f2=?0b?>6:`98m0d=83.9<l4;5:l14<<e32c>m7>5$32b>13<f;:26n54i4;94?"58h0?96`=088g?>o203:1(?>n:578j76>2l10e8:50;&14d<3=2d9<44i;:k7=?6=,;:j69;4n32:>46<3`9o6=4+21c900=i:931=<54o6`94?"58h0<m6`=0883?>i013:1(?>n:6c8j76>2810c:650;&14d<0i2d9<44=;:m43?6=,;:j6:o4n32:>6=<g><1<7*=0`84e>h5800?76a85;29 76f2>k0b?>6:498k22=83.9<l48a:l14<<132e<?7>5$32b>2g<f;:26:54o9694?"58h0<m6`=088;?>i?;3:1(?>n:6c8j76>2010c5<50;&14d<0i2d9<44n;:m;5?6=,;:j6:o4n32:>g=<g1:1<7*=0`84e>h5800h76a8f;29 76f2>k0b?>6:e98k2c=83.9<l48a:l14<<b32e<h7>5$32b>2g<f;:26k54o6a94?"58h0<m6`=08824>=h?;0;6)<?a;5b?k4713;:76g>d083>!47i3;o<6`=0883?>o6ko0;6)<?a;3g4>h5800:76g>cd83>!47i3;o<6`=0881?>o6km0;6)<?a;3g4>h5800876g>cb83>!47i3;o<6`=0887?>o6kk0;6)<?a;3g4>h5800>76g>c`83>!47i3;o<6`=0885?>o6k00;6)<?a;3g4>h5800<76g>c683>!47i3;o<6`=088;?>o6k?0;6)<?a;3g4>h5800276g>c483>!47i3;o<6`=088b?>o6k=0;6)<?a;3g4>h5800i76g>c283>!47i3;o<6`=088`?>o6k;0;6)<?a;3g4>h5800o76g>c083>!47i3;o<6`=088f?>o6k90;6)<?a;3g4>h5800m76g>bg83>!47i3;o<6`=08824>=n9ko1<7*=0`82`5=i:931=<54i0``>5<#:9k1=i>4n32:>44<3`;in7>5$32b>4b73g8;57?<;:k2fd<72-8;m7?k0:l14<<6<21b=o750;&14d<6l91e>=751498m4d?290/>=o51e28j76>28<07d?m7;29 76f28n;7c<?9;34?>o6j?0;6)<?a;3g4>h5800:465f1c794?"58h0:h=5a21;95<=<a8h?6=4+21c95a6<f;:26<o4;h3a7?6=,;:j6<j?;o03=?7e32c:n<4?:%03e?7c82d9<44>c:9j5g6=83.9<l4>d19m65?=9m10e<oi:18'65g=9m:0b?>6:0g8?l7fm3:1(?>n:0f3?k4713;m76g>ae83>!47i3;o<6`=08814>=n9hi1<7*=0`82`5=i:931><54i0ca>5<#:9k1=i>4n32:>74<3`;jm7>5$32b>4b73g8;57<<;:k2e<<72-8;m7?k0:l14<<5<21b=l650;&14d<6l91e>=752498m4b0290/>=o51e28j76>2;<07d?k6;29 76f28n;7c<?9;04?>o6l<0;6)<?a;3g4>h58009465f1e694?"58h0:h=5a21;96<=<a8n86=4+21c95a6<f;:26?o4;h3g6?6=,;:j6<j?;o03=?4e32c:o54?:%03e?7c82d9<44=c:9j5gb=83.9<l4>d19m65?=:m10e<l=:18'65g=9m:0b?>6:3g8?l7f?3:1(?>n:0f3?k47138m76gm1;29 76f2k:0b?>6:198md`=83.9<l4m0:l14<<632cji7>5$32b>g6<f;:26?54i`f94?"58h0i<6`=0880?>ofk3:1(?>n:c28j76>2=10ell50;&14d<e82d9<44:;:kbe?6=,;:j6o>4n32:>3=<ah31<7*=0`8a4>h5800<76gn7;29 76f2k:0b?>6:998md0=83.9<l4m0:l14<<>32cj97>5$32b>g6<f;:26l54i`694?"58h0i<6`=088a?>of;3:1(?>n:c28j76>2j10el<50;&14d<e82d9<44k;:kb5?6=,;:j6o>4n32:>`=<ah:1<7*=0`8a4>h5800m76g6f;29 76f2k:0b?>6:028?l?b290/>=o5b19m65?=9810e4m50;&14d<e82d9<44>2:9j=g<72-8;m7l?;o03=?7432c2m7>5$32b>g6<f;:26<:4;h;:>5<#:9k1n=5a21;950=<a021<7*=0`8a4>h5800::65f9683>!47i3h;7c<?9;34?>o>>3:1(?>n:c28j76>28207d7::18'65g=j91e>=751898m<2=83.9<l4m0:l14<<6i21b5>4?:%03e?d73g8;57?m;:k:5?6=,;:j6o>4n32:>4e<3`3;6=4+21c9f5=i:931=i54i9d94?"58h0i<6`=0882a>=n0l0;6)<?a;`3?k4713;m76g7d;29 76f2k:0b?>6:328?l>d290/>=o5b19m65?=:810e5l50;&14d<e82d9<44=2:9j<d<72-8;m7l?;o03=?4432c357>5$32b>g6<f;:26?:4;h:;>5<#:9k1n=5a21;960=<ak=1<7*=0`8a4>h58009:65fb783>!47i3h;7c<?9;04?>oe=3:1(?>n:c28j76>2;207dl;:18'65g=j91e>=752898mg5=83.9<l4m0:l14<<5i21bn?4?:%03e?d73g8;57<m;:kb<?6=,;:j6o>4n32:>7e<3`3o6=4+21c9f5=i:931>i54i8094?"58h0i<6`=0881a>=n0>0;6)<?a;`3?k47138m76a>5e83>!47i3;>o6`=0883?>i6=k0;6)<?a;36g>h5800:76a>5`83>!47i3;>o6`=0881?>i6=00;6)<?a;36g>h5800876a>5983>!47i3;>o6`=0887?>i6=>0;6)<?a;36g>h5800>76a>5783>!47i3;>o6`=0885?>i6=<0;6)<?a;36g>h5800<76a>5283>!47i3;>o6`=088;?>i6=;0;6)<?a;36g>h5800276a>5083>!47i3;>o6`=088b?>i6=90;6)<?a;36g>h5800i76a>4g83>!47i3;>o6`=088`?>i6<l0;6)<?a;36g>h5800o76a>4e83>!47i3;>o6`=088f?>i6<j0;6)<?a;36g>h5800m76a>4c83>!47i3;>o6`=08824>=h9=k1<7*=0`821f=i:931=<54o06;>5<#:9k1=8m4n32:>44<3f;?;7>5$32b>43d3g8;57?<;:m203<72-8;m7?:c:l14<<6<21d=9;50;&14d<6=j1e>=751498k423290/>=o514a8j76>28<07b?;3;29 76f28?h7c<?9;34?>i6<;0;6)<?a;36g>h5800:465`15394?"58h0:9n5a21;95<=<g8>;6=4+21c950e<f;:26<o4;n30b?6=,;:j6<;l;o03=?7e32e:?i4?:%03e?72k2d9<44>c:9l56e=83.9<l4>5b9m65?=9m10c<=m:18'65g=9<i0b?>6:0g8?j74i3:1(?>n:07`?k4713;m76a>3883>!47i3;>o6`=08814>=h9:21<7*=0`821f=i:931><54o014>5<#:9k1=8m4n32:>74<3f;8:7>5$32b>43d3g8;57<<;:m270<72-8;m7?:c:l14<<5<21d=>:50;&14d<6=j1e>=752498k413290/>=o514a8j76>2;<07b?83;29 76f28?h7c<?9;04?>i6?;0;6)<?a;36g>h58009465`16394?"58h0:9n5a21;96<=<g8<i6=4+21c950e<f;:26?o4;n354?6=,;:j6<;l;o03=?4e32e:994?:%03e?72k2d9<44=c:9l51?=83.9<l4>5b9m65?=:m10c<=j:18'65g=9<i0b?>6:3g8?j74;3:1(?>n:07`?k47138m76g>2e83>!47i3;9o6`=0883?>o6:k0;6)<?a;31g>h5800:76g>2`83>!47i3;9o6`=0881?>o6:00;6)<?a;31g>h5800876g>2983>!47i3;9o6`=0887?>o6:>0;6)<?a;31g>h5800>76g>2783>!47i3;9o6`=0885?>o6:<0;6)<?a;31g>h5800<76gj8;29 76f2l=0b?>6:198m`0=83.9<l4j7:l14<<632cn97>5$32b>`1<f;:26?54id694?"58h0n;6`=0880?>ob;3:1(?>n:d58j76>2=10eh<50;&14d<b?2d9<44:;:kf5?6=,;:j6h94n32:>3=<al:1<7*=0`8f3>h5800<76gi1;29 76f2l=0b?>6:998mc6=83.9<l4j7:l14<<>32cnj7>5$32b>`1<f;:26l54idg94?"58h0n;6`=088a?>obl3:1(?>n:d58j76>2j10ehm50;&14d<b?2d9<44k;:kff?6=,;:j6h94n32:>`=<alk1<7*=0`8f3>h5800m76gj9;29 76f2l=0b?>6:028?lba290/>=o5e69m65?=9810c?>=:18'65g=:9;0b?>6:198k767290/>=o52138j76>2810c<hi:18'65g=:9;0b?>6:398k4`b290/>=o52138j76>2:10c<hk:18'65g=:9;0b?>6:598k4`d290/>=o52138j76>2<10c<hm:18'65g=:9;0b?>6:798k4`f290/>=o52138j76>2>10c<h7:18'65g=:9;0b?>6:998k4`0290/>=o52138j76>2010c<h9:18'65g=:9;0b?>6:`98k4`2290/>=o52138j76>2k10c<h;:18'65g=:9;0b?>6:b98k4`4290/>=o52138j76>2m10c<h=:18'65g=:9;0b?>6:d98k4`6290/>=o52138j76>2o10c<h?:18'65g=:9;0b?>6:028?j7bn3:1(?>n:322?k4713;:76a>ee83>!47i38;=6`=08826>=h9li1<7*=0`8144=i:931=>54o0ga>5<#:9k1>=?4n32:>42<3f;nm7>5$32b>7663g8;57?:;:m2a<<72-8;m7<?1:l14<<6>21d=h650;&14d<5881e>=751698k4c0290/>=o52138j76>28207b?j6;29 76f2;::7c<?9;3:?>i6m<0;6)<?a;035>h5800:m65`1d694?"58h09<<5a21;95g=<g8o96=4+21c9657<f;:26<m4;n3f5?6=,;:j6?>>;o03=?7c32e:i=4?:%03e?4792d9<44>e:9l5a`=83.9<l4=009m65?=9o10c<jj:18'65g=:9;0b?>6:328?j7cl3:1(?>n:322?k47138:76a>db83>!47i38;=6`=08816>=h9mh1<7*=0`8144=i:931>>54o0fb>5<#:9k1>=?4n32:>72<3f;o57>5$32b>7663g8;57<:;:m14=<72-8;m7<?1:l14<<5>21d>=950;&14d<5881e>=752698k761290/>=o52138j76>2;207b<?5;29 76f2;::7c<?9;0:?>i58=0;6)<?a;035>h58009m65`21194?"58h09<<5a21;96g=<g8l26=4+21c9657<f;:26?m4;n3fa?6=,;:j6?>>;o03=?4c32e:i>4?:%03e?4792d9<44=e:9l5a>=83.9<l4=009m65?=:o10e?<50;&14d<592d9<44?;:k14?6=,;:j6??4n32:>4=<a8l1<7*=0`815>h5800976g>e;29 76f2;;0b?>6:298m4b=83.9<l4=1:l14<<332c:o7>5$32b>77<f;:26854i0`94?"58h09=6`=0885?>o6i3:1(?>n:338j76>2>10e>o50;&14d<592d9<447;:k0=?6=,;:j6??4n32:><=<a:21<7*=0`815>h5800j76g<7;29 76f2;;0b?>6:c98m60=83.9<l4=1:l14<<d32c897>5$32b>77<f;:26i54i2694?"58h09=6`=088f?>o483:1(?>n:338j76>2o10e?;50;&14d<592d9<44>0:9j5<<72-8;m7<>;o03=?7632e:=54?:%03e?76?2d9<44?;:m253<72-8;m7?>7:l14<<632e:=84?:%03e?76?2d9<44=;:m251<72-8;m7?>7:l14<<432e:=>4?:%03e?76?2d9<44;;:m257<72-8;m7?>7:l14<<232e:==4?:%03e?76?2d9<449;:m24c<72-8;m7?>7:l14<<032e:<h4?:%03e?76?2d9<447;:m24a<72-8;m7?>7:l14<<>32e:<n4?:%03e?76?2d9<44n;:m24g<72-8;m7?>7:l14<<e32e:<l4?:%03e?76?2d9<44l;:m24<<72-8;m7?>7:l14<<c32e:<54?:%03e?76?2d9<44j;:m242<72-8;m7?>7:l14<<a32e:<84?:%03e?76?2d9<44>0:9l552=83.9<l4>169m65?=9810c<><:18'65g=98=0b?>6:008?j77:3:1(?>n:034?k4713;876a>0083>!47i3;:;6`=08820>=h99:1<7*=0`8252=i:931=854ogd94?"58h0:=:5a21;953=<goo1<7*=0`8252=i:931=:54ogf94?"58h0:=:5a21;95==<goi1<7*=0`8252=i:931=454o03e>5<#:9k1=<94n32:>4g<3f;:i7>5$32b>4703g8;57?m;:m25a<72-8;m7?>7:l14<<6k21d=<m50;&14d<69>1e>=751e98k47e290/>=o51058j76>28o07b?>a;29 76f28;<7c<?9;3e?>i6900;6)<?a;323>h58009<65`10394?"58h0:=:5a21;964=<g8:=6=4+21c9541<f;:26?<4;nda>5<#:9k1=<94n32:>75<3`<36=4+21c922=i:931<6F=1`98m30=83.9<l497:l14<<63A8:m65f6483>!47i3<<7c<?9;08L77f32c=87>5$32b>31<f;:26>5G20c8?l04290/>=o5669m65?=<2B9=l54i7094?"58h0=;6`=0886?M46i21b:<4?:%03e?003g8;5784H33b?>o183:1(?>n:758j76>2>1C><o4;h52>5<#:9k1::5a21;9<>N59h10e:>50;&14d<1?2d9<446;I02e>=n>o0;6)<?a;44?k4713k0D??n;:k5a?6=,;:j6;94n32:>g=O:8k07d8k:18'65g=>>1e>=75c:J15d=<a?i1<7*=0`853>h5800o7E<>a:9j2g<72-8;m788;o03=?c<@;;j76g9a;29 76f2?=0b?>6:g9K64g<3`<26=4+21c922=i:931==5G20c8?l3a290/>=o5669m65?=981C><o4;|`133<728?j6=4?{%02a?`43A89?6F=1g9Y<0<es8<1;7?=:g86>1<b28:1:7=5d;'57`=:h=0b<950:l2<?7<f:h1<6`<c;38jg?=82.im7?=4:lg`?6<fo81<6`>2183?k75m3:0b?>m:19'640=:8n0boj50:k`6?6=3`8:<7>5;h025?6=3`i86=44i331>5<<aj?1<75fc083>>iek3:17d<>4;29?l46;3:17dm7:188m76a2900en:50;9jg5<722ci47>5;ha5>5<<akl1<75`bc83>>o58l0;66g=1483>>o3>3:1(?>n:578j76>2910e9:50;&14d<3=2d9<44>;:k77?6=,;:j69;4n32:>7=<a=81<7*=0`871>h5800876g;1;29 76f2=?0b?>6:598m16=83.9<l4;5:l14<<232c8j7>5$32b>13<f;:26;54i2g94?"58h0?96`=0884?>o2m3:1(?>n:578j76>2110e8j50;&14d<3=2d9<446;:k6g?6=,;:j69;4n32:>d=<a<h1<7*=0`871>h5800i76g:a;29 76f2=?0b?>6:b98m0?=83.9<l4;5:l14<<c32c>47>5$32b>13<f;:26h54i4694?"58h0?96`=088e?>o313:1(?>n:578j76>28:07d=k:18'65g=<<1e>=751098k2d=83.9<l48a:l14<<732e<57>5$32b>2g<f;:26<54o6:94?"58h0<m6`=0881?>i0?3:1(?>n:6c8j76>2:10c:850;&14d<0i2d9<44;;:m41?6=,;:j6:o4n32:>0=<g>>1<7*=0`84e>h5800=76a83;29 76f2>k0b?>6:698k=2=83.9<l48a:l14<<?32e3?7>5$32b>2g<f;:26454o9094?"58h0<m6`=088b?>i?93:1(?>n:6c8j76>2k10c5>50;&14d<0i2d9<44l;:m4b?6=,;:j6:o4n32:>a=<g>o1<7*=0`84e>h5800n76a8d;29 76f2>k0b?>6:g98k2e=83.9<l48a:l14<<6821d;?4?:%03e?1f3g8;57?>;:k2`4<72-8;m7?k0:l14<<732c:ok4?:%03e?7c82d9<44>;:k2g`<72-8;m7?k0:l14<<532c:oi4?:%03e?7c82d9<44<;:k2gf<72-8;m7?k0:l14<<332c:oo4?:%03e?7c82d9<44:;:k2gd<72-8;m7?k0:l14<<132c:o44?:%03e?7c82d9<448;:k2g2<72-8;m7?k0:l14<<?32c:o;4?:%03e?7c82d9<446;:k2g0<72-8;m7?k0:l14<<f32c:o94?:%03e?7c82d9<44m;:k2g6<72-8;m7?k0:l14<<d32c:o?4?:%03e?7c82d9<44k;:k2g4<72-8;m7?k0:l14<<b32c:o=4?:%03e?7c82d9<44i;:k2fc<72-8;m7?k0:l14<<6821b=ok50;&14d<6l91e>=751098m4dd290/>=o51e28j76>28807d?mb;29 76f28n;7c<?9;30?>o6jh0;6)<?a;3g4>h5800:865f1c;94?"58h0:h=5a21;950=<a8h36=4+21c95a6<f;:26<84;h3a3?6=,;:j6<j?;o03=?7032c:n;4?:%03e?7c82d9<44>8:9j5g3=83.9<l4>d19m65?=9010e<l;:18'65g=9m:0b?>6:0c8?l7e;3:1(?>n:0f3?k4713;i76g>b083>!47i3;o<6`=0882g>=n9k:1<7*=0`82`5=i:931=i54i0ce>5<#:9k1=i>4n32:>4c<3`;ji7>5$32b>4b73g8;57?i;:k2ea<72-8;m7?k0:l14<<5821b=lm50;&14d<6l91e>=752098m4ge290/>=o51e28j76>2;807d?na;29 76f28n;7c<?9;00?>o6i00;6)<?a;3g4>h58009865f1`:94?"58h0:h=5a21;960=<a8n<6=4+21c95a6<f;:26?84;h3g2?6=,;:j6<j?;o03=?4032c:h84?:%03e?7c82d9<44=8:9j5a2=83.9<l4>d19m65?=:010e<j<:18'65g=9m:0b?>6:3c8?l7c:3:1(?>n:0f3?k47138i76g>c983>!47i3;o<6`=0881g>=n9kn1<7*=0`82`5=i:931>i54i0`1>5<#:9k1=i>4n32:>7c<3`;j;7>5$32b>4b73g8;57<i;:ka5?6=,;:j6o>4n32:>5=<ahl1<7*=0`8a4>h5800:76gne;29 76f2k:0b?>6:398mdb=83.9<l4m0:l14<<432cjo7>5$32b>g6<f;:26954i``94?"58h0i<6`=0886?>ofi3:1(?>n:c28j76>2?10el750;&14d<e82d9<448;:kb3?6=,;:j6o>4n32:>==<ah<1<7*=0`8a4>h5800276gn5;29 76f2k:0b?>6:`98md2=83.9<l4m0:l14<<e32cj?7>5$32b>g6<f;:26n54i`094?"58h0i<6`=088g?>of93:1(?>n:c28j76>2l10el>50;&14d<e82d9<44i;:k:b?6=,;:j6o>4n32:>46<3`3n6=4+21c9f5=i:931=<54i8a94?"58h0i<6`=08826>=n1k0;6)<?a;`3?k4713;876g6a;29 76f2k:0b?>6:068?l?>290/>=o5b19m65?=9<10e4650;&14d<e82d9<44>6:9j=2<72-8;m7l?;o03=?7032c2:7>5$32b>g6<f;:26<64;h;6>5<#:9k1n=5a21;95<=<a0>1<7*=0`8a4>h5800:m65f9283>!47i3h;7c<?9;3a?>o>93:1(?>n:c28j76>28i07d7?:18'65g=j91e>=751e98m=`=83.9<l4m0:l14<<6m21b4h4?:%03e?d73g8;57?i;:k;`?6=,;:j6o>4n32:>76<3`2h6=4+21c9f5=i:931><54i9`94?"58h0i<6`=08816>=n0h0;6)<?a;`3?k47138876g79;29 76f2k:0b?>6:368?l>?290/>=o5b19m65?=:<10eo950;&14d<e82d9<44=6:9jf3<72-8;m7l?;o03=?4032ci97>5$32b>g6<f;:26?64;h`7>5<#:9k1n=5a21;96<=<ak91<7*=0`8a4>h58009m65fb383>!47i3h;7c<?9;0a?>of03:1(?>n:c28j76>2;i07d7k:18'65g=j91e>=752e98m<4=83.9<l4m0:l14<<5m21b4:4?:%03e?d73g8;57<i;:m21a<72-8;m7?:c:l14<<732e:9o4?:%03e?72k2d9<44>;:m21d<72-8;m7?:c:l14<<532e:944?:%03e?72k2d9<44<;:m21=<72-8;m7?:c:l14<<332e:9:4?:%03e?72k2d9<44:;:m213<72-8;m7?:c:l14<<132e:984?:%03e?72k2d9<448;:m216<72-8;m7?:c:l14<<?32e:9?4?:%03e?72k2d9<446;:m214<72-8;m7?:c:l14<<f32e:9=4?:%03e?72k2d9<44m;:m20c<72-8;m7?:c:l14<<d32e:8h4?:%03e?72k2d9<44k;:m20a<72-8;m7?:c:l14<<b32e:8n4?:%03e?72k2d9<44i;:m20g<72-8;m7?:c:l14<<6821d=9o50;&14d<6=j1e>=751098k42?290/>=o514a8j76>28807b?;7;29 76f28?h7c<?9;30?>i6<?0;6)<?a;36g>h5800:865`15794?"58h0:9n5a21;950=<g8>?6=4+21c950e<f;:26<84;n377?6=,;:j6<;l;o03=?7032e:8?4?:%03e?72k2d9<44>8:9l517=83.9<l4>5b9m65?=9010c<:?:18'65g=9<i0b?>6:0c8?j74n3:1(?>n:07`?k4713;i76a>3e83>!47i3;>o6`=0882g>=h9:i1<7*=0`821f=i:931=i54o01a>5<#:9k1=8m4n32:>4c<3f;8m7>5$32b>43d3g8;57?i;:m27<<72-8;m7?:c:l14<<5821d=>650;&14d<6=j1e>=752098k450290/>=o514a8j76>2;807b?<6;29 76f28?h7c<?9;00?>i6;<0;6)<?a;36g>h58009865`12694?"58h0:9n5a21;960=<g8=?6=4+21c950e<f;:26?84;n347?6=,;:j6<;l;o03=?4032e:;?4?:%03e?72k2d9<44=8:9l527=83.9<l4>5b9m65?=:010c<8m:18'65g=9<i0b?>6:3c8?j7183:1(?>n:07`?k47138i76a>5583>!47i3;>o6`=0881g>=h9=31<7*=0`821f=i:931>i54o01f>5<#:9k1=8m4n32:>7c<3f;8?7>5$32b>43d3g8;57<i;:k26a<72-8;m7?=c:l14<<732c:>o4?:%03e?75k2d9<44>;:k26d<72-8;m7?=c:l14<<532c:>44?:%03e?75k2d9<44<;:k26=<72-8;m7?=c:l14<<332c:>:4?:%03e?75k2d9<44:;:k263<72-8;m7?=c:l14<<132c:>84?:%03e?75k2d9<448;:kf<?6=,;:j6h94n32:>5=<al<1<7*=0`8f3>h5800:76gj5;29 76f2l=0b?>6:398m`2=83.9<l4j7:l14<<432cn?7>5$32b>`1<f;:26954id094?"58h0n;6`=0886?>ob93:1(?>n:d58j76>2?10eh>50;&14d<b?2d9<448;:ke5?6=,;:j6h94n32:>==<ao:1<7*=0`8f3>h5800276gjf;29 76f2l=0b?>6:`98m`c=83.9<l4j7:l14<<e32cnh7>5$32b>`1<f;:26n54ida94?"58h0n;6`=088g?>obj3:1(?>n:d58j76>2l10eho50;&14d<b?2d9<44i;:kf=?6=,;:j6h94n32:>46<3`nm6=4+21c9a2=i:931=<54o321>5<#:9k1>=?4n32:>5=<g;:;6=4+21c9657<f;:26<54o0de>5<#:9k1>=?4n32:>7=<g8ln6=4+21c9657<f;:26>54o0dg>5<#:9k1>=?4n32:>1=<g8lh6=4+21c9657<f;:26854o0da>5<#:9k1>=?4n32:>3=<g8lj6=4+21c9657<f;:26:54o0d;>5<#:9k1>=?4n32:>==<g8l<6=4+21c9657<f;:26454o0d5>5<#:9k1>=?4n32:>d=<g8l>6=4+21c9657<f;:26o54o0d7>5<#:9k1>=?4n32:>f=<g8l86=4+21c9657<f;:26i54o0d1>5<#:9k1>=?4n32:>`=<g8l:6=4+21c9657<f;:26k54o0d3>5<#:9k1>=?4n32:>46<3f;nj7>5$32b>7663g8;57?>;:m2aa<72-8;m7<?1:l14<<6:21d=hm50;&14d<5881e>=751298k4ce290/>=o52138j76>28>07b?ja;29 76f2;::7c<?9;36?>i6m00;6)<?a;035>h5800::65`1d:94?"58h09<<5a21;952=<g8o<6=4+21c9657<f;:26<64;n3f2?6=,;:j6?>>;o03=?7>32e:i84?:%03e?4792d9<44>a:9l5`2=83.9<l4=009m65?=9k10c<k=:18'65g=:9;0b?>6:0a8?j7b93:1(?>n:322?k4713;o76a>e183>!47i38;=6`=0882a>=h9ml1<7*=0`8144=i:931=k54o0ff>5<#:9k1>=?4n32:>76<3f;oh7>5$32b>7663g8;57<>;:m2`f<72-8;m7<?1:l14<<5:21d=il50;&14d<5881e>=752298k4bf290/>=o52138j76>2;>07b?k9;29 76f2;::7c<?9;06?>i5810;6)<?a;035>h58009:65`21594?"58h09<<5a21;962=<g;:=6=4+21c9657<f;:26?64;n031?6=,;:j6?>>;o03=?4>32e9<94?:%03e?4792d9<44=a:9l655=83.9<l4=009m65?=:k10c<h6:18'65g=:9;0b?>6:3a8?j7bm3:1(?>n:322?k47138o76a>e283>!47i38;=6`=0881a>=h9m21<7*=0`8144=i:931>k54i3094?"58h09=6`=0883?>o583:1(?>n:338j76>2810e<h50;&14d<592d9<44=;:k2a?6=,;:j6??4n32:>6=<a8n1<7*=0`815>h5800?76g>c;29 76f2;;0b?>6:498m4d=83.9<l4=1:l14<<132c:m7>5$32b>77<f;:26:54i2c94?"58h09=6`=088;?>o413:1(?>n:338j76>2010e>650;&14d<592d9<44n;:k03?6=,;:j6??4n32:>g=<a:<1<7*=0`815>h5800h76g<5;29 76f2;;0b?>6:e98m62=83.9<l4=1:l14<<b32c8<7>5$32b>77<f;:26k54i3794?"58h09=6`=08824>=n900;6)<?a;02?k4713;:76a>1983>!47i3;:;6`=0883?>i69?0;6)<?a;323>h5800:76a>1483>!47i3;:;6`=0881?>i69=0;6)<?a;323>h5800876a>1283>!47i3;:;6`=0887?>i69;0;6)<?a;323>h5800>76a>1183>!47i3;:;6`=0885?>i68o0;6)<?a;323>h5800<76a>0d83>!47i3;:;6`=088;?>i68m0;6)<?a;323>h5800276a>0b83>!47i3;:;6`=088b?>i68k0;6)<?a;323>h5800i76a>0`83>!47i3;:;6`=088`?>i6800;6)<?a;323>h5800o76a>0983>!47i3;:;6`=088f?>i68>0;6)<?a;323>h5800m76a>0483>!47i3;:;6`=08824>=h99>1<7*=0`8252=i:931=<54o020>5<#:9k1=<94n32:>44<3f;;>7>5$32b>4703g8;57?<;:m244<72-8;m7?>7:l14<<6<21d==>50;&14d<69>1e>=751498kc`=83.9<l4>169m65?=9?10ckk50;&14d<69>1e>=751698kcb=83.9<l4>169m65?=9110ckm50;&14d<69>1e>=751898k47a290/>=o51058j76>28k07b?>e;29 76f28;<7c<?9;3a?>i69m0;6)<?a;323>h5800:o65`10a94?"58h0:=:5a21;95a=<g8;i6=4+21c9541<f;:26<k4;n32e?6=,;:j6<?8;o03=?7a32e:=44?:%03e?76?2d9<44=0:9l547=83.9<l4>169m65?=:810c<>9:18'65g=98=0b?>6:308?j`e290/>=o51058j76>2;907d87:18'65g=>>1e>=750:J15d=<a?<1<7*=0`853>h5800:7E<>a:9j20<72-8;m788;o03=?4<@;;j76g94;29 76f2?=0b?>6:29K64g<3`<86=4+21c922=i:93186F=1`98m34=83.9<l497:l14<<23A8:m65f6083>!47i3<<7c<?9;48L77f32c=<7>5$32b>31<f;:26:5G20c8?l16290/>=o5669m65?=02B9=l54i6294?"58h0=;6`=088:?M46i21b:k4?:%03e?003g8;57o4H33b?>o1m3:1(?>n:758j76>2k1C><o4;h4g>5<#:9k1::5a21;9g>N59h10e;m50;&14d<1?2d9<44k;I02e>=n>k0;6)<?a;44?k4713o0D??n;:k5e?6=,;:j6;94n32:>c=O:8k07d86:18'65g=>>1e>=75119K64g<3`?m6=4+21c922=i:931=<5G20c8?xd5?>0;6>4?:1y'64c=n=1C>?=4H33e?!`02;1b4;4?::kga?6=3f8;h7>5;|`13=<72:0;6=u+20g9b1=O:;90D??i;%d4>7=n0?0;66gke;29?j47l3:17pl=7883>6<729q/><k5f59K675<@;;m7)h8:39j<3<722coi7>5;n03`?6=3th9;l4?:283>5}#:8o1j95G2318L77a3-l<6?5f8783>>ocm3:17b<?d;29?xd5?k0;6>4?:1y'64c=n=1C>?=4H33e?!`02;1b4;4?::kga?6=3f8;h7>5;|`13f<72:0;6=u+20g9b1=O:;90D??i;%d4>7=n0?0;66gke;29?j47l3:17pl=7e83>6<729q/><k5f59K675<@;;m7)h8:39j<3<722coi7>5;n03`?6=3th9;h4?:283>5}#:8o1j95G2318L77a3-l<6?5f8783>>ocm3:17b<?d;29?xd5?o0;6>4?:1y'64c=n=1C>?=4H33e?!`02;1b4;4?::kga?6=3f8;h7>5;|`1<5<72:0;6=u+20g9b1=O:;90D??i;%d4>7=n0?0;66gke;29?j47l3:17pl=8083>6<729q/><k5f59K675<@;;m7)h8:39j<3<722coi7>5;n03`?6=3th94?4?:283>5}#:8o1j95G2318L77a3-l<6?5f8783>>ocm3:17b<?d;29?xd50:0;6>4?:1y'64c=n=1C>?=4H33e?!`02;1b4;4?::kga?6=3f8;h7>5;|`1<1<72:0;6=u+20g9b1=O:;90D??i;%d4>7=n0?0;66gke;29?j47l3:17pl=8483>6<729q/><k5f59K675<@;;m7)h8:39j<3<722coi7>5;n03`?6=3th94;4?:283>5}#:8o1j95G2318L77a3-l<6?5f8783>>ocm3:17b<?d;29?xd50>0;6>4?:1y'64c=n=1C>?=4H33e?!`02;1b4;4?::kga?6=3f8;h7>5;|`1<=<72:0;6=u+20g9b1=O:;90D??i;%d4>7=n0?0;66gke;29?j47l3:17pl=8883>6<729q/><k5f59K675<@;;m7)h8:39j<3<722coi7>5;n03`?6=3th94l4?:283>5}#:8o1j95G2318L77a3-l<6?5f8783>>ocm3:17b<?d;29?xd50k0;6>4?:1y'64c=n=1C>?=4H33e?!`02;1b4;4?::kga?6=3f8;h7>5;|`1<f<72:0;6=u+20g9b1=O:;90D??i;%d4>7=n0?0;66gke;29?j47l3:17pl=8e83>6<729q/><k5f59K675<@;;m7)h8:39j<3<722coi7>5;n03`?6=3th94h4?:283>5}#:8o1j95G2318L77a3-l<6?5f8783>>ocm3:17b<?d;29?xd50o0;6>4?:1y'64c=n=1C>?=4H33e?!`02;1b4;4?::kga?6=3f8;h7>5;|`1=5<72:0;6=u+20g9b1=O:;90D??i;%d4>7=n0?0;66gke;29?j47l3:17pl=9083>6<729q/><k5f59K675<@;;m7)h8:39j<3<722coi7>5;n03`?6=3th95?4?:283>5}#:8o1j95G2318L77a3-l<6?5f8783>>ocm3:17b<?d;29?xd51:0;6>4?:1y'64c=n=1C>?=4H33e?!`02;1b4;4?::kga?6=3f8;h7>5;|`1=1<72:0;6=u+20g9b1=O:;90D??i;%d4>7=n0?0;66gke;29?j47l3:17pl=9483>6<729q/><k5f59K675<@;;m7)h8:39j<3<722coi7>5;n03`?6=3th95;4?:283>5}#:8o1j95G2318L77a3-l<6?5f8783>>ocm3:17b<?d;29?xd51>0;6>4?:1y'64c=n=1C>?=4H33e?!`02;1b4;4?::kga?6=3f8;h7>5;|`1==<72:0;6=u+20g9b1=O:;90D??i;%d4>7=n0?0;66gke;29?j47l3:17p}=e`83>6}Y;:16>:=51d9>622=9l1v?km:180[56348<?7?k;<040?7c3ty9in4?:2y]6c=::>91=n5226695f=z{;oo6=4<{_0f?840;3;i70<84;3a?xu5ml0;6>uQ2e9>625=9h16>::51`9~w7ca2908wS<l;<047?5f348<87=n;|q1b5<72:qU>o5226197<=::>>1?45rs3d2>5<4sW8j70<83;1;?840<3937p}=f383>6}Y:016>:=5369>622=;>1v?h<:180[4?348<?7=9;<040?513ty9j94?:2y]62=::>91?852266970=z{;l>6=4<{_05?840;39?70<84;17?xu5n?0;6>uQ259>625=;916>::5319~w7`02908wS<<;<047?42348<87<:;|q1b=<72:qU>?5226195<=::>>1=45rs3d:>5<4sW8;70<85;03?840>38;7p}=f`83>6}Y9o16>:;51g9>620=9o1v?hm:180[7b348<97?j;<042?7b3ty9jn4?:2y]5a=::>?1=i5226495a=z{;lo6=4<{_3`?840=3;h70<86;3`?xu5nl0;6>uQ1c9>623=9k16>:851c9~w7`a2908wS?n;<041?7f348<:7?n;|q045<72:qU?l5226797d=::><1?l5rs222>5<4sW9270<85;1:?840>3927p}<0383>6}Y;116>:;5399>620=;11v>><:180[50348<97=8;<042?503ty8<94?:2y]73=::>?1?;52264973=z{::>6=4<{_16?840=39>70<86;16?xu48?0;6>uQ359>623=;=16>:85359~w6602908wS=?;<041?57348<:7=?;|q04=<72:qU>852267960=::><1>85rs22:>5<4sW;270<85;3:?840>3;27p}<0`83>7}Y=>16>:;5439~w66e2909wS;:;<041?263ty8<n4?:3y]16=::>?18=5rs22g>5<5sW?970<85;1e?xu48l0;6?uQ509>623=;l1v>>i:181[37348<97;j;|q055<72;qU8k5226791a=z{:;:6=4={_6f?840=3?h7p}<1383>7}Y<m16>:;55c9~w6742909wS:l;<041?3f3ty8=94?:3y]0g=::>?1945rs236>5<5sW>j70<85;7;?xu49?0;6?uQ499>623===1v>?8:181[20348<97:6;|q05=<72;qU8;5226797a=z{:;26=4={_67?840>3>?7p}<1`83>7}Y<:16>:85429~w67e2909wS:=;<042?253ty8=n4?:3y]04=::><18<5rs23g>5<5sW>;70<86;63?xu49l0;6?uQ3g9>620=;o1v>?i:181[5b348<:7=j;|q065<72;qU9h5226491`=z{:8:6=4={_7g?840>3?o7p}<2383>7}Y=j16>:855b9~w6442909wS;m;<042?3e3ty8>94?:3y]1d=::><19l5rs206>5<5sW?270<86;7:?xu4:?0;6?uQ599>620==11v><8:181[33348<:7;;;|q06=<72;qU845226490<=z{:826=4={_1g?840>39o7p}<2`83>71|Vj201?99:b:897122j201?9;:b:897142j201?68:94897>121<01?6::94897>321<01?6<:94897>521<01?6>:94897>721<01?9i:948971b21<01?9k:948971d21<01?9m:948971f21<01?96:948971?21<01?98:94897??21<01?78:94897?121<01?7::94897?321<01?7<:94897?521<01?7>:94897?721<01?6i:94897>b21<01?6k:94897>d21<01?6m:94897>f21<01?66:94897>?21<0q~==b;296~X6?916>:=515:8yv55k3:1>vP>6d9>625=9==0q~==d;296~X6>m16>:=51548yv55m3:1>vP>6b9>625=9=?0q~==f;296~X6>h16>:=51568yv5483:1>vP>689>625=9=90q~=<1;296~X6>116>:=51508yv54:3:1>vP>669>625=9=;0q~=<3;296~X6>?16>:=51528yv54<3:1>vP>649>625=9:l0q~=<5;296~X6>=16>:=512f8yv54>3:1>vP>629>625=9:i0q~=<7;296~X6>;16>:=512`8yv5403:1>vP>609>625=9:k0q~=<9;296~X6=o16>:=512;8yv54i3:1>vP>5d9>625=9:20q~=<b;296~X6=m16>:=51258yv54k3:1>vP>5c9>625=9:<0q~=<d;296~X6=h16>:=51278yv54m3:1>vP>589>625=9:>0q~=<f;296~X6=116>:=51668yv5383:1>vP>569>625=9>90q~=;1;296~X6=?16>:=51608yv53:3:1>vP>549>625=9>;0q~=;3;296~X6=:16>:=517`8yv53<3:1>vP>539>625=9?:0q~=;5;296~X6=816>:=51468yv53>3:1>vP>519>625=9=30q~=;7;296~X6<o16>:=512g8yv5303:1>vP>4d9>625=9:90q~=;9;296~X6<m16>:9521f8yv53i3:1>vP>4b9>62>=:9n0q~=;b;296~X6<k16>:7521f8yv53k3:1>vP>4`9>62g=:9n0q~=;d;296~X6<116>:l521f8yv53m3:1>vP>469>62e=:9n0q~=;f;296~X6<?16>:j521f8yv5283:1>vP>449>62c=:9n0q~=:1;296~X6<=16>:h521f8yv52:3:1>vP>429>6=6=:9n0q~=:3;296~X6<;16>5?521f8yv52<3:1>vP>409>6=4=:9n0q~=:5;296~X6<916>5=521f8yv52>3:1>vP>3g9>6=2=:9n0q~=:7;296~X6;m16>5;521f8yv5203:1>vP>3b9>6=0=:9n0q~=:9;296~X6;k16>59521f8yv52i3:1>vP>3`9>6=>=:9n0q~=:b;296~X6;016>57521f8yv52k3:1>vP>399>6=g=:9n0q~=:d;296~X6;>16>5l521f8yv52m3:1>vP>379>6=e=:9n0q~=:f;296~X6;<16>5j521f8yv5183:1>vP>359>6=c=:9n0q~=91;296~X6?=16>5h521f8yv51:3:1>vP>729>6<6=:9n0q~=93;296~X6?;16>4?521f8yv51<3:1>vP>709>6<4=:9n0q~=95;296~X6>k16>4=521f8yv51>3:1>vP>619>6<2=:9n0q~=97;296~X6==16>4;521f8yv5103:1>vP>489>6<0=:9n0q~=99;296~X6;l16>49521f8yv51i3:1>vP>329>6<>=:9n0q~=9b;296~X6i916>:=52108yv51k3:1>vP>9d9>625=:9:0q~=9d;296~X61m16>:=51gd8yv51m3:1>vP>9b9>625=9oo0q~=9f;296~X61k16>:=51gf8yv5083:1>vP>9`9>625=9oi0q~=81;296~X61016>:=51g`8yv50:3:1>vP>999>625=9ok0q~=83;296~X61?16>:=51g:8yv50<3:1>vP>949>625=9o=0q~=85;296~X61=16>:=51g48yv50>3:1>vP>929>625=9o?0q~=87;296~X61;16>:=51g68yv5003:1>vP>909>625=9o90q~=89;296~X61916>:=51g08yv50i3:1>vP>8g9>625=9o;0q~=8b;296~X60l16>:=51g28yv50k3:1>vP>8e9>625=9ll0q~=8d;296~X60k16>:=51df8yv50m3:1>vP>8`9>625=9li0q~=8f;296~X60016>:=51d`8yv5?83:1>vP>899>625=9lk0q~=71;296~X60>16>:=51d;8yv5?:3:1>vP>879>625=9l20q~=73;296~X60<16>:=51d58yv5?<3:1>vP>859>625=9l<0q~=75;296~X60:16>:=51d78yv5?>3:1>vP>839>625=9l>0q~=77;296~X60916>:=51d08yv5?03:1>vP>7g9>625=9l;0q~=79;296~X6?l16>:=51d28yv5?i3:1>vP>7e9>625=9ml0q~=7b;296~X6?j16>:=51eg8yv5?k3:1>vP>7c9>625=9mn0q~=7d;296~X6?h16>:=51ea8yv5?m3:1>vP>789>625=9mh0q~=7f;296~X6?116>:=51ec8yv5>83:1>vP>769>625=9m30q~=61;296~X6i?16>:=521:8yv5>:3:1>vP>a49>625=:9=0q~=63;296~X6i=16>:=52148yv5><3:1>vP>a29>625=:9?0q~=65;296~X6i;16>:=52168yv5>>3:1>vP>a09>625=:990q~=67;296~X61>16>:=51g;8yv5>03:1>vP>8b9>625=9lo0q~=69;296~X60816>:=51d18yv5>i3:1>vP>779>625=9m20q~=6b;2954}::>;1=>?4=355>g`<5;==6n>4=355>442348<97li;<041?e7348<97?=5:?130<6:>16>::5bg9>622=9;?01?9;:004?840<3;9463=728ab>;5?:0h:63=728260=::>91=?94=350>44?3ty85n4?:e`x97152o?0R?<m;<042?d?348<:7m>;<042?e5348<:7m<;<042?e3348<:7m:;<042?e1348<:7ji;<042?c>348<:7kn;<042?ce348<:7kl;<042?cc348<:7kj;<042?ca348<:7h?;<042?`6348<:7k?;<042?c6348<:7k=;<042?c4348<:7k;;<042?c2348<:7k9;<042?c?348<:7?=6:?133<6:016>:8513c89711288i70<86;31`>;5??0:m:5226495g4<5;==6<lk;<042?7d0279;;4>d39>620=9m901?99:0f7?840>3;o963=7782`3=::><1=i94=355>4g?348<:7?n9:?133<6ih16>:851``8971128kh70<86;3b`>;5??0:mh5226495d`<5;==6<l?;<042?7e9279;;4>b29>620=9k>01?99:0`6?840>3;i:63=7782f2=::><1=o64=355>4d>348<:7?ma:?133<6jk16>:851ca8971128hn70<86;3ab>;5??0:o=5226495f7<5;==6<m=;<042?7d;279;;4>c59>620=9j?01?99:0a5?840>3;h;63=7782g<=::><1=no4=355>4ee348<:7?lc:?133<6km16>:851bg8971128im70<86;3g5>;5??09<h52264965`<5;==6???;<042?469279;;4=139>620=:8901?99:337?840>38:963=748a<>;5?<0h=63=748`6>;5?<0h?63=748`0>;5?<0h963=748`2>;5?<0oj63=748f=>;5?<0nm63=748ff>;5?<0no63=748f`>;5?<0ni63=748fb>;5?<0m<63=748e5>;5?<0n<63=748f5>;5?<0n>63=748f7>;5?<0n863=748f1>;5?<0n:63=748f<>;5?<0:>;52267957><5;=>6<<6;<041?75i279;84>2c9>623=:9o01?9::32e?840=38:<63=748154=::>?1><<4=356>774348<97<>4:?130<59<16>::5b99>622=k916>::5c09>622=k;16>::5c29>622=k=16>::5c49>622=k?16>::5dg9>622=m016>::5e`9>622=mk16>::5eb9>622=mm16>::5ed9>622=mo16>::5f19>622=n816>::5e19>622=m816>::5e39>622=m:16>::5e59>622=m<16>::5e79>622=m116>::513489713288270<84;31e>;5?=0:>o52266965c<5;=?6?>i;<040?468279;94=109>622=:8801?9;:330?840<38:863=758150=::>91n5522619g5=::>91o<522619g7=::>91o>522619g1=::>91o8522619`c=::>91i4522619ad=::>91io522619af=::>91ii522619a`=::>91ik522619b5=::>91j<522619a5=::>91i<522619a7=::>91i>522619a1=::>91i8522619a3=::>91i5522619570<5;=86<<6;<047?75i279;>4>2c9>625=:9o01?9<:32e?840;38:<63=728154=::>91><<4=350>774348<?7<>4:?136<59<16>:851358971128837S<=d:?130<3;279;84;4:?130<3>279;;4;6:?130<5:279;;4=2:?136<6n279;>4=0:?136<5:279;94>f:?131<58279;94=2:?130<6:m16>::513f89714288o7p}<9e83>7}::>?1=l94=357>4b?3ty85h4?:3y>623=9k801?9;:0g0?xu41o0;6?u226795gb<5;=?6<kj;|q0e5<72;q6>:;51b:8971328l27p}<a083>7}::>?1=i<4=357>7643ty8m?4?:3y>623=9m901?9;:327?xu4i:0;6?u226795a2<5;=?6?>:;|q0e1<72;q6>:;51e7897132;:=7p}<a483>7}::>?1=i84=357>7603ty8m;4?:3y>623=9m=01?9;:32;?xu4i>0;6?u226795d><5;=?6<j6;|q0e=<72;q6>:;51`;8971328nj7p}<a883>7}::>?1=lo4=357>4be3ty8ml4?:3y>623=9hh01?9;:0f`?xu4ik0;6?u226795de<5;=?6<jk;|q0ef<72;q6>:;51`f8971328nn7p}<ae83>7}::>?1=lk4=357>4ba3ty8mh4?:3y>623=9hl01?9;:0g3?xu4io0;6?u226795g6<5;=?6<k>;|q0f5<72;q6>:;51c38971328o97p}<b083>7}::>?1=o=4=357>4c33ty8n?4?:3y>623=9k>01?9;:0g6?xu4j:0;6?u226795g3<5;=?6<k9;|q0f1<72;q6>:;51c48971328o<7p}<b483>7}::>?1=o94=357>4c?3ty8n;4?:3y>623=9k201?9;:0g:?xu4j>0;6?u226795g?<5;=?6<kn;|q0f=<72;q6>:;51cc8971328oi7p}<b883>7}::>?1=ol4=357>4cd3ty8nl4?:3y>623=9ki01?9;:0gg?xu4jk0;6?u226795gc<5;=?6<ki;|q0ff<72;q6>:;51cd8971328l;7p}<be83>7}::>?1=n>4=357>4`63ty8nh4?:3y>623=9j;01?9;:0d1?xu4jo0;6?u226795f4<5;=?6<h<;|q0g5<72;q6>:;51b18971328l?7p}<c083>7}::>?1=n:4=357>4`23ty8o?4?:3y>623=9j?01?9;:0d5?xu4k:0;6?u226795f0<5;=?6<h8;|q0g1<72;q6>:;51b58971328l37p}<c483>7}::>?1=n74=357>4`f3ty8o;4?:3y>623=9jk01?9;:0da?xu4k>0;6?u226795fd<5;=?6<hl;|q0g=<72;q6>:;51ba8971328lo7p}<c883>7}::>?1=nj4=357>4`b3ty8ol4?:3y>623=9jo01?9;:0de?xu4kk0;6?u226795f`<5;=?6?>?;|q0gf<72;q6>:;51e3897132;:97p}<ce83>7}::>?1=i64=350>4g03ty8oh4?:3y>623=9l901?9<:0`1?xu4ko0;6?u226795`c<5;=86<lk;|q0`5<72;q6>:;51g;8971428i37p}<d083>7}::>?1>==4=350>4b53ty8h?4?:3y>623=:9>01?9<:0f0?xu4l:0;6?u22679653<5;=86<j;;|q0`1<72;q6>:;52148971428n>7p}<d483>7}::>?1>=94=350>4b13ty8h;4?:3y>623=:9201?9<:0f4?xu4l>0;6?u226795a?<5;=86<o7;|q0`=<72;q6>:;51ec8971428k27p}<d883>7}::>?1=il4=350>4gf3ty8hl4?:3y>623=9mi01?9<:0ca?xu4lk0;6?u226795ab<5;=86<ol;|q0`f<72;q6>:;51eg8971428ko7p}<de83>7}::>?1=ih4=350>4gb3ty8hh4?:3y>623=9l:01?9<:0ce?xu4lo0;6?u226795`7<5;=86<l?;|q0a5<72;q6>:;51d08971428h:7p}<e083>7}::>?1=h:4=350>4d43ty8i?4?:3y>623=9l?01?9<:0`7?xu4m:0;6?u226795`0<5;=86<l:;|q0a1<72;q6>:;51d58971428h=7p}<e483>7}::>?1=h64=350>4d03ty8i;4?:3y>623=9l301?9<:0`;?xu4m>0;6?u226795`g<5;=86<l6;|q0a=<72;q6>:;51d`8971428hj7p}<e883>7}::>?1=hm4=350>4de3ty8il4?:3y>623=9ln01?9<:0``?xu4mk0;6?u226795``<5;=86<lj;|q0af<72;q6>:;51g28971428hm7p}<ee83>7}::>?1=k?4=350>4e73ty8ih4?:3y>623=9o801?9<:0a2?xu4mo0;6?u226795c5<5;=86<m=;|q0b5<72;q6>:;51g68971428i87p}<f083>7}::>?1=k;4=350>4e33ty8j?4?:3y>623=9o<01?9<:0a6?xu4n:0;6?u226795c1<5;=86<m9;|q0b1<72;q6>:;51g:8971428i<7p}<f483>7}::>?1=ko4=350>4e>3ty8j;4?:3y>623=9oh01?9<:0ab?xu4n>0;6?u226795ce<5;=86<mm;|q0b=<72;q6>:;51gf8971428ih7p}<f883>7}::>?1=kk4=350>4ec3ty8jl4?:3y>623=9ol01?9<:0af?xu4nk0;6?u22679656<5;=86<mi;|q0bf<72;q6>:;52108971428n:7p}<fe83>7}::>?1=>l4=350>=1<uz9mi7>52z?130<6;j16>:=5939~w6`a2909w0<85;30`>;5?:02h6s|41294?4|5;=>6<=i;<047?g?3ty?<<4?:3y>623=9=:01?9<:c08yv27:3:1>v3=748204=::>91n>5rs520>5<5s48<97?;2:?136<e<2wx8=:50;0x971228>870<83;`6?xu38<0;6?u22679512<5;=86o84}r632?6=:r79;84>449>625=j>1v9>8:181840=3;?:63=728;<>{t<921<7<t=356>420348<?766;|q74<<72;q6>:;515:8971421k0q~:?a;296~;5?<0:8l522619<g=z{=:i6=4={<041?73j279;>47c:p05e=838p1?9::06`?840;32o7p};0e83>7}::>?1=9j4=350>=c<uz>;i7>52z?130<6<l16>:=58g9~w16a2909w0<85;37b>;5?:02<6s|40294?4|5;=>6<;?;<047??63ty?=<4?:3y>623=9<;01?9<:818yv26:3:1>v3=748217=::>91595rs530>5<5s48<97?:3:?136<>=2wx8<:50;0x971228?>70<83;;5?xu39<0;6?u22679500<5;=86494}r622?6=:r79;84>569>625=111v9?8:181840=3;>463=728:=>{t<821<7<t=356>43>348<?77n;|q75<<72;q6>:;514c8971420h0q~:>a;296~;5?<0:9o522619=f=z{=;i6=4>3z?130<6=m16>:=59d9>625=1o16>:=5a19>625=i816>:=5a39>625=i:16>:=5a59>625=i<16>:=5a79>625=i>16>:=5a89>625=ih16>:=5ac9>625=ij16>:=5ae9>625=il16>:=5ag9>625=j81v9?l:181840=3;8?63=868ga>{t<8n1<7<t=356>45b3483:7jj;|q75`<72;q6>:;515;897>22mo0q~:>f;296~;5?<0:99522969``=z{=8;6=4={<041?7182794>4ke:p077=838p1?9::04a?84?:3nn7p};2383>7}::>?1=:?4=3:2>ac<uz>9?7>52z?130<6?;16>5>5dd9~w1432909w0<85;347>;5?o0oi6s|43794?4|5;=>6<9;;<04a?bb3ty?>;4?:3y>623=9:>01?9k:eg8yv25?3:1>v3=748270=::>i1hh5rs50;>5<5s48<97?<6:?13g<cm2wx8?750;0x9712289<70<8a;ff?xu3:h0;6?u2267956><5;=26ik4}r61f?6=:r79;84>389>62>=ll1v9<l:181840=3;8m63=768ga>{t<;n1<7<t=356>24<5;=86>j4}r61a?6=:r79;848c:?136<312wx8?h50;0x97122>n01?9<:468yv2483:1>v3=7484a>;5?:0>46s|42394?4|5;=>6:h4=350>0?<uz>8>7>52z?130<?8279;>4:a:p065=838p1?9::93897142<h0q~:<4;296~;5?<03>63=7286g>{t<:?1<7<t=356>=5<5;=868j4}r602?6=:r79;8474:?136<2m2wx8>950;0x97122>901?9<:2g8yv2403:1>v3=74840>;5?:08j6s|42;94?4|5;=>6:;4=350>16<uz>8m7>52z?130<0>279;>4;1:p06d=838p1?9::65897142=80q~:<c;296~;5?<0<463=72877>{t<:n1<7<t=356>2?<5;=869:4}r60a?6=:r79;848b:?136<3>2wx8>h50;0x971128n370<84;3b3>{t<=:1<7<t=355>4c4348<87?m2:p017=838p1?99:0gf?840<3;ih6s|45094?4|5;==6<h6;<040?7d02wx89=50;0x97112;:870<84;3g6>{t<=>1<7<t=355>763348<87?k3:p013=838p1?99:326?840<3;o86s|45494?4|5;==6?>9;<040?7c=2wx89950;0x97112;:<70<84;3g2>{t<=21<7<t=355>76?348<87?k7:p01?=838p1?99:0f:?840<3;j46s|45c94?4|5;==6<jn;<040?7f12wx89l50;0x971128ni70<84;3be>{t<=i1<7<t=355>4bd348<87?nb:p01b=838p1?99:0fg?840<3;jo6s|45g94?4|5;==6<jj;<040?7fl2wx89h50;0x971128nm70<84;3ba>{t<<:1<7<t=355>4c7348<87?nf:p007=838p1?99:0g2?840<3;i<6s|44094?4|5;==6<k=;<040?7e92wx88=50;0x971128o?70<84;3a7>{t<<>1<7<t=355>4c2348<87?m4:p003=838p1?99:0g5?840<3;i96s|44494?4|5;==6<k8;<040?7e>2wx88950;0x971128o370<84;3a3>{t<<21<7<t=355>4c>348<87?m8:p00?=838p1?99:0gb?840<3;i56s|44c94?4|5;==6<km;<040?7ei2wx88l50;0x971128oh70<84;3af>{t<<i1<7<t=355>4cc348<87?mc:p00b=838p1?99:0ge?840<3;ii6s|44g94?4|5;==6<h?;<040?7en2wx88h50;0x971128l:70<84;3`4>{t<?:1<7<t=355>4`5348<87?l1:p037=838p1?99:0d0?840<3;h>6s|47094?4|5;==6<h;;<040?7d;2wx8;=50;0x971128l>70<84;3`0>{t<?>1<7<t=355>4`1348<87?l5:p033=838p1?99:0d4?840<3;h:6s|47494?4|5;==6<h7;<040?7d?2wx8;950;0x971128lj70<84;3`=>{t<?21<7<t=355>4`e348<87?la:p03?=838p1?99:0d`?840<3;hn6s|47c94?4|5;==6<hk;<040?7dk2wx8;l50;0x971128ln70<84;3``>{t<?i1<7<t=355>4`a348<87?le:p03b=838p1?99:323?840<3;hj6s|47g94?4|5;==6?>=;<040?7c92wx8;h50;0x9711289i70<84;:4?xu3?90;6?u2264956e<5;=?64<4}r645?6=:r79;;4>3e9>622=1m1v99=:181840>3;8j63=758b<>{t<>91<7<t=355>427348<87l=;|q731<72;q6>:85153897132k90q~:85;296~;5??0:8?522669f1=z{===6=4={<042?73;279;94m5:p021=838p1?99:067?840<3h=7p};7983>7}::><1=9;4=357>g1<uz><57>52z?133<6<?16>::5899~w11f2909w0<86;373>;5?=0356s|46`94?4|5;==6<:7;<040?>f3ty?;n4?:3y>620=9=k01?9;:9`8yv20l3:1>v3=77820g=::>>14n5rs55f>5<5s48<:7?;c:?131<?l2wx8:h50;0x971128>o70<84;:f?xu3090;6?u2264951c<5;=?65h4}r6;5?6=:r79;;4>4g9>622=191v96=:181840>3;><63=758:5>{t<191<7<t=355>436348<877<;|q7<1<72;q6>:851408971320>0q~:75;296~;5??0:9>522669=0=z{=2=6=4={<042?72=279;9466:p0=1=838p1?99:075?840<33<7p};8983>7}::><1=894=357><><uz>357>52z?133<6=116>::5989~w1>f2909w0<86;36=>;5?=02m6s|49`94?4|5;==6<;n;<040??e3ty?4n4?:3y>620=9<h01?9;:8a8yv2?l3:1=>u2264950b<5;=?64k4=357><`<5;=?6l>4=357>d7<5;=?6l<4=357>d5<5;=?6l:4=357>d3<5;=?6l84=357>d1<5;=?6l74=357>dg<5;=?6ll4=357>de<5;=?6lj4=357>dc<5;=?6lh4=357>g7<uz>3i7>52z?133<6;:16>465dd9~w1>a2909w0<86;30a>;51>0oi6s|48294?4|5;==6<:6;<0:2?bb3ty?5<4?:3y>620=9<>01?7::eg8yv2>:3:1>v3=778225=::0>1hh5rs5;0>5<5s48<:7?9b:?1=6<cm2wx84:50;0x971128=:70<62;ff?xu31<0;6?u22649524<5;3:6ik4}r6:2?6=:r79;;4>729>6<6=ll1v978:181840>3;<863=8g8ga>{t<021<7<t=355>4533483i7jj;|q7=<<72;q6>:85127897>c2mo0q~:6a;296~;5??0:?;5229a9``=z{=3i6=4={<042?74?2794o4ke:p0<e=838p1?99:01;?84?i3nn7p};9e83>7}::><1=>74=3::>ac<uz>2i7>52z?133<6;h16>565dd9~w1?a2909w0<86;51?840<39o7p};a183>7}::><1;n5226690<=z{=k:6=4={<042?1c348<87;;;|q7e7<72;q6>:857d9>622==11v9o<:181840>3=m70<84;7:?xu3i=0;6?u22649<5=::>>19l5rs5c6>5<5s48<:76>;<040?3e3ty?m;4?:3y>620=0;16>::55b9~w1g02909w0<86;:0?840<3?o7p};a983>7}::><1495226691`=z{=k26=4={<042?14348<87=j;|q7ed<72;q6>:85759>622=;o1v9om:181840>3=>70<84;63?xu3ij0;6?u2264933=::>>18<5rs5cg>5<5s48<:798;<040?253ty?mh4?:3y>620=?116>::5429~w1ga2909w0<86;5:?840<3>?7p};b183>7}::><1;o52266903=zuz8?;7>52z\102=::>:1?>5rs366>5<5sW8?963=71805>{t:=91<7<t^360?840838m7p}=4383>7}Y:=801?9?:3g8yv4393:1>vP=409>626=:m1v?:?:181[438279;=4=c:p66`=838pR?=i;<044?4e3ty9?h4?:3y]66c<5;=;6?o4}r00`?6=:rT9?i5226296<=z{;9h6=4={_00g>;5?90946s|22`94?4|V;9i70<80;04?xu5;h0;6?uQ22c897172;<0q~<<8;296~X5;116>:>5259~w7502909wS<<7:?135<5;2wx>>850;0xZ751348<<7<=;|q170<72;qU>>;4=353>76<uz8887>52z\171=::>:1=k5rs310>5<5sW88?63=7182a>{t::81<7<t^311?84083;o7p}=3083>7}Y::;01?9?:0a8yv4483:1>vP=319>626=9k1v?<i:181[45n279;=4>a:p61c=838pR?:j;<044?5f3ty98i4?:3y]61b<5;=;6>74}r07g?6=:rT98n5226297==z{;>i6=4={_07f>;5?908;6s|25c94?4|V;>j70<80;15?xu5<00;6?uQ25;897172:?0q~<;8;296~X5<116>:>5359~w7232909wS<;4:?135<482wx>>750;0xZ75>348<<7<:;|q16`<72;qU>?k4=353>4?<uz8=47>52z\12==::>:19:5rs345>5<5sW8=:63=71861>{t:?>1<7<t^347?84083?87p}=6283>7}Y:?901?9?:408yv41:3:1>vP=639>626==81v?8>:181[419279;=4:0:p636=838pR?8?;<044?2a3ty99k4?:3y]60`<5;=;69k4}r06a?6=:rT99h5226290a=z{;?o6=4={_06`>;5?90?o6s|24a94?4|V;?h70<80;6a?xu5=k0;6?uQ24`897172=k0q~<:9;296~X5=016>:>5499~w73?2909wS<:8:?135<3?2wx>8950;0xZ730348<<7:9;|q113<72;qU>884=353>12<uz8>97>52z\110=::>:18>5rs377>5<5sW8>863=71876>{t:<91<7<t^370?84083>:7p}=5383>7}Y:<801?9?:528yv4293:1>vP=509>626=;o1v?;?:181[428279;=4<e:p63`=838pR?8i;<044?3b3ty9:h4?:3y]63c<5;=;68j4}r05`?6=:rT9:i5226291f=z{;<h6=4={_05g>;5?90>n6s|27`94?4|V;<i70<80;7b?xu5>h0;6?uQ27c897172<30q~<99;296~X5>016>:>5599~w7022909wS<95:?135<2<2wx>8o50;0xZ73f348<<7:6;|q10c<72;qU>9h4=353>6b<uz8257>52z\1=<=::>:1o55rs3g6>5<5sW8n963=718235=z{;o86=4={_0f7>;5?90::h5rs3g1>5<5sW8n>63=71822a=z{;o:6=4={_0f5>;5?90::n5rs3fe>5<5sW8oj63=71822d=z{;nn6=4={_0ga>;5?90::45rs3fg>5<5sW8oh63=71822==z{;nh6=4={_0gg>;5?90:::5rs3fa>5<5sW8on63=718223=z{;nj6=4={_0ge>;5?90::85rs3f:>5<5sW8o563=718221=z{;n36=4={_0g<>;5?90::>5rs3f4>5<5sW8o;63=718227=z{;n=6=4={_0g2>;5?90::<5rs3f7>5<5sW8o863=71821c=z{;n86=4={_0g7>;5?90:9h5rs3f1>5<5sW8o>63=71821a=z{;n:6=4={_0g5>;5?90:9o5rs3f3>5<5sW8o<63=71821d=z{;im6=4={_0`b>;5?90:945rs3af>5<5sW8hi63=71821==z{;io6=4={_0``>;5?90:9:5rs3a`>5<5sW8ho63=718213=z{;ii6=4={_0`f>;5?90:985rs3a:>5<5sW8h563=718216=z{;i36=4={_0`<>;5?90:9?5rs3a4>5<5sW8h;63=718214=z{;i=6=4={_0`2>;5?90:9=5rs3a6>5<5sW8h963=71820c=z{;i?6=4={_0`0>;5?90:8h5rs3a0>5<5sW8h?63=71820a=z{;i96=4={_0`6>;5?90:8n5rs3a2>5<5sW8h=63=71820g=z{;i;6=4={_0`4>;5?90:8l5rs3`f>5<5sW8ii63=71820==z{;ho6=4={_0a`>;5?90:8:5rs3``>5<5sW8io63=718203=z{;hi6=4={_0af>;5?90:885rs3`b>5<5sW8im63=718201=z{;h26=4={_0a=>;5?90:8>5rs3`;>5<5sW8i463=718207=z{;h<6=4={_0a3>;5?90:8<5rs3`5>5<5sW8i:63=718205=z{;h>6=4={_0a1>;5?90:?k5rs3`0>5<5sW8i?63=71827a=z{;h96=4={_0a6>;5?90:?n5rs3`2>5<5sW8i=63=71827g=z{;h;6=4={_0a4>;5?90:?l5rs3ce>5<5sW8jj63=71827<=z{;kn6=4={_0ba>;5?90:?55rs3cg>5<5sW8jh63=718272=z{;kh6=4={_0bg>;5?90:?;5rs3ca>5<5sW8jn63=718270=z{;kj6=4={_0be>;5?90:?95rs3g:>5<5sW8n563=718231=z{;o36=4={_0f<>;5?90:;>5rs3g4>5<5sW8n;63=718237=z{;o=6=4={_0f2>;5?90:;<5rs3g3>5<5sW8n<63=71822g=z{;n>6=4={_0g1>;5?90::=5rs3ab>5<5sW8hm63=718211=z{;hm6=4={_0ab>;5?90:845rs3`7>5<5sW8i863=71827`=z{;k26=4={_0b=>;5?90:?>5r}o;37?6=:rB9=k5rn827>5<5sA8:j6sa91794?4|@;;m7p`60783>7}O:8l0qc7?7;296~N59o1vb4>7:181M46n2we5=750;0xL77a3td2<l4?:3yK64`<ug3;n7>52zJ15c=zf0:h6=4={I02b>{i19n1<7<tH33e?xh>8l0;6?uG20d8yk?7n3:1>vF=1g9~j<772909wE<>f:m=47=838pD??i;|l:57<72;qC><h4}o;27?6=:rB9=k5rn837>5<5sA8:j6sa90794?4|@;;m7p`61783>7}O:8l0qc7>7;296~N59o1vb4?7:181M46n2we5<750;0xL77a3td2=l4?:3yK64`<ug3:n7>52zJ15c=zf0;h6=4={I02b>{i18n1<7<tH33e?xh>9l0;6?uG20d8yk?6n3:1>vF=1g9~j<472909wE<>f:m=77=838pD??i;|l:67<72;qC><h4}o;17?6=:rB9=k5rn807>5<5sA8:j6sa93794?4|@;;m7p`62783>7}O:8l0qc7=7;296~N59o1vb4<7:181M46n2we5?750;0xL77a3td2>l4?:3yK64`<ug39n7>52zJ15c=zf08h6=4={I02b>{i1;n1<7<tH33e?xh>:l0;6?uG20d8yk?5n3:1>vF=1g9~j<572909wE<>f:m=67=838pD??i;|l:77<72;qC><h4}o;07?6=:rB9=k5rn817>5<5sA8:j6sa92794?4|@;;m7p`63783>7}O:8l0qc7<7;296~N59o1vb4=7:181M46n2we5>750;0xL77a3td2?l4?:3yK64`<ug38n7>52zJ15c=zf09h6=4={I02b>{i1:n1<7<tH33e?xh>;l0;6?uG20d8yk?4n3:1>vF=1g9~j<272909wE<>f:m=17=838pD??i;|l:07<72;qC><h4}o;77?6=:rB9=k5rn867>5<5sA8:j6sa95794?4|@;;m7p`64783>7}O:8l0qc7;7;296~N59o1vb4:7:181M46n2we59750;0xL77a3td28l4?:3yK64`<ug3?n7>52zJ15c=zf0>h6=4={I02b>{i1=n1<7<tH33e?xh><l0;6?uG20d8yk?3n3:1>vF=1g9~j<372909wE<>f:m=07=838pD??i;|l:17<72;qC><h4}o;67?6=:rB9=k5rn877>5<5sA8:j6sa94794?4|@;;m7p`65783>7}O:8l0qc7:7;296~N59o1vb4;7:181M46n2we58750;0xL77a3td29l4?:3yK64`<ug3>n7>52zJ15c=zf0?h6=4={I02b>{i1<n1<7<tH33e?xh>=l0;6?uG20d8yk?2n3:1>vF=1g9~j<072909wE<>f:m=37=838pD??i;|l:27<72;qC><h4}o;57?6=:rB9=k5rn847>5<5sA8:j6sa97794?4|@;;m7p`66783>7}O:8l0qc797;296~N59o1vb487:181M46n2we5;750;0xL77a3td2:l4?:3yK64`<ug3=n7>52zJ15c=zf0<h6=4={I02b>{i1?n1<7<tH33e?xh>>l0;6?uG20d8yk?1n3:1>vF=1g9~j<172909wE<>f:m=27=838pD??i;|l:37<72;qC><h4}o;47?6=:rB9=k5rn857>5<5sA8:j6sa96794?4|@;;m7p`67783>7}O:8l0qc787;296~N59o1vb497:181M46n2we5:750;0xL77a3td2;l4?:3yK64`<ug3<n7>52zJ15c=zf0=h6=4={I02b>{i1>n1<7<tH33e?xh>?l0;6?uG20d8yk?0n3:1>vF=1g9~j<>72909wE<>f:m==7=838pD??i;|l:<7<72;qC><h4}o;;7?6=:rB9=k5rn6`g>5<6sA8:j6sa7cg94?7|@;;m7p`8bg83>4}O:8l0qc9l0;295~N59o1vb:m>:182M46n2we;n<50;3xL77a3td<o>4?:0yK64`<ug=h87>51zJ15c=zf>i>6=4>{I02b>{i?j<1<7?tH33e?xh0k>0;6<uG20d8yk1d03:1=vF=1g9~j2e>290:wE<>f:m3fg=83;pD??i;|l4gg<728qC><h4}o5`g?6=9rB9=k5rn6ag>5<6sA8:j6sa7bg94?7|@;;m7p`8cg83>4}O:8l0qc9k0;295~N59o1vb:j>:182M46n2we;i<50;3xL77a3td<h>4?:0yK64`<ug=o87>51zJ15c=zf>n>6=4>{I02b>{i?m<1<7?tH33e?xh0l>0;6<uG20d8yk1c03:1=vF=1g9~j2b>290:wE<>f:m3ag=83;pD??i;|l4`g<728qC><h4}o5gg?6=9rB9=k5rn6fg>5<6sA8:j6sa7eg94?7|@;;m7p`8dg83>4}O:8l0qc9j0;295~N59o1vb:k>:182M46n2we;h<50;3xL77a3td<i>4?:0yK64`<ug=n87>51zJ15c=zf>o>6=4>{I02b>{i?l<1<7?tH33e?xh0m>0;6<uG20d8yk1b03:1=vF=1g9~j2c>290:wE<>f:m3`g=83;pD??i;|l4ag<728qC><h4}o5fg?6=9rB9=k5rn6gg>5<6sA8:j6sa7dg94?7|@;;m7p`8eg83>4}O:8l0qc9i0;295~N59o1vb:h>:182M46n2we;k<50;3xL77a3td<j>4?:0yK64`<ug=m87>51zJ15c=zf>l>6=4>{I02b>{i?o<1<7?tH33e?xh0n>0;6<uG20d8yk1a03:1=vF=1g9~j2`>290:wE<>f:m3cg=83;pD??i;|l4bg<728qC><h4}o5eg?6=9rB9=k5rn6dg>5<6sA8:j6sa7gg94?7|@;;m7p`8fg83>4}O:8l0qc6?0;295~N59o1vb5>>:182M46n2we4=<50;3xL77a3td3<>4?:0yK64`<ug2;87>51zJ15c=zf1:>6=4>{I02b>{i09<1<7?tH33e?xh?8>0;6<uG20d8yk>703:1=vF=1g9~j=6>290:wE<>f:m<5g=83;pD??i;|l;4g<728qC><h4}o:3g?6=9rB9=k5rn92g>5<6sA8:j6sa81g94?7|@;;m7p`70g83>4}O:8l0qc6>0;295~N59o1vb5?>:182M46n2we4<<50;3xL77a3td3=>4?:0yK64`<ug2:87>51zJ15c=zf1;>6=4>{I02b>{i08<1<7?tH33e?xh?9>0;6<uG20d8yk>603:1=vF=1g9~j=7>290:wE<>f:m<4g=83;pD??i;|l;5g<728qC><h4}o:2g?6=9rB9=k5rn93g>5<6sA8:j6sa80g94?7|@;;m7p`71g83>4}O:8l0qc6=0;295~N59o1vb5<>:182M46n2we4?<50;3xL77a3td3>>4?:0yK64`<ug2987>51zJ15c=zf18>6=4>{I02b>{i0;<1<7?tH33e?xh?:>0;6<uG20d8yk>503:1=vF=1g9~j=4>290:wE<>f:m<7g=83;pD??i;|l;6g<728qC><h4}o:1g?6=9rB9=k5rn90g>5<6sA8:j6sa83g94?7|@;;m7p`72g83>4}O:8l0qc6<0;295~N59o1vb5=>:182M46n2we4><50;3xL77a3td3?>4?:0yK64`<ug2887>51zJ15c=zf19>6=4>{I02b>{i0:<1<7?tH33e?xh?;>0;6<uG20d8yk>403:1=vF=1g9~j=5>290:wE<>f:m<6g=83;pD??i;|l;7g<728qC><h4}o:0g?6=9rB9=k5rn91g>5<6sA8:j6sa82g94?7|@;;m7p`73g83>4}O:8l0qc6;0;295~N59o1vb5:>:182M46n2we49<50;3xL77a3td38>4?:0yK64`<ug2?87>51zJ15c=zf1>>6=4>{I02b>{i0=<1<7?tH33e?xh?<>0;6<uG20d8yk>303:1=vF=1g9~j=2>290:wE<>f:m<1g=83;pD??i;|l;0g<728qC><h4}o:7g?6=9rB9=k5rn96g>5<6sA8:j6sa85g94?7|@;;m7p`74g83>4}O:8l0qc6:0;295~N59o1vb5;>:182M46n2we48<50;3xL77a3td39>4?:0yK64`<ug2>87>51zJ15c=zf1?>6=4>{I02b>{i0<<1<7?tH33e?xh?=>0;6<uG20d8yk>203:1=vF=1g9~j=3>290:wE<>f:m<0g=83;pD??i;|l;1g<728qC><h4}o:6g?6=9rB9=k5rn97g>5<6sA8:j6sa84g94?7|@;;m7p`75g83>4}O:8l0qc690;295~N59o1vb58>:182M46n2we4;<50;3xL77a3td3:>4?:0yK64`<ug2=87>51zJ15c=zf1<>6=4>{I02b>{i0?<1<7?tH33e?xh?>>0;6<uG20d8yk>103:1=vF=1g9~j=0>290:wE<>f:m<3g=83;pD??i;|l;2g<728qC><h4}o:5g?6=9rB9=k5rn94g>5<6sA8:j6sa87g94?7|@;;m7p`76g83>4}O:8l0qc680;295~N59o1vb59>:182M46n2we4:<50;3xL77a3td3;>4?:0yK64`<ug2<87>51zJ15c=zf1=>6=4>{I02b>{i0><1<7?tH33e?xh??>0;6<uG20d8yk>003:1=vF=1g9~j=1>290:wE<>f:m<2g=83;pD??i;|l;3g<728qC><h4}o:4g?6=9rB9=k5rn95g>5<6sA8:j6sa86g94?7|@;;m7p`77g83>4}O:8l0qc670;295~N59o1vb56>:182M46n2we45<50;3xL77a3td34>4?:0yK64`<ug2387>51zJ15c=zf12>6=4>{I02b>{i01<1<7?tH33e?xh?0>0;6<uG20d8yk>?03:1=vF=1g9~j=>>290:wE<>f:m<=g=83;pD??i;|l;<g<728qC><h4}o:;g?6=9rB9=k5rn9:g>5<6sA8:j6sa89g94?7|@;;m7p`78g83>4}O:8l0qc660;295~N59o1vb57>:182M46n2we44<50;3xL77a3td35>4?:0yK64`<ug2287>51zJ15c=zf13>6=4>{I02b>{i00<1<7?tH33e?xh?1>0;6<uG20d8yk>>03:1=vF=1g9~j=?>290:wE<>f:m<<g=83;pD??i;|l;=g<728qC><h4}o::g?6=9rB9=k5rn9;g>5<6sA8:j6sa88g94?7|@;;m7p`79g83>4}O:8l0qc6n0;295~N59o1vb5o>:182M46n2we4l<50;3xL77a3td3m>4?:0yK64`<ug2j87>51zJ15c=zf1k>6=4>{I02b>{i0h<1<7?tH33e?xh?i>0;6<uG20d8yk>f03:1=vF=1g9~j=g>290:wE<>f:m<dg=83;pD??i;|l;eg<728qC><h4}o:bg?6=9rB9=k5rn9cg>5<6sA8:j6sa8`g94?7|@;;m7p`7ag83>4}O:8l0qc6m0;295~N59o1vb5l>:182M46n2we4o<50;3xL77a3td3n>4?:0yK64`<ug2i87>51zJ15c=zf1h>6=4>{I02b>{i0k<1<7?tH33e?xh?j>0;6<uG20d8yk>e03:1=vF=1g9~j=d>290:wE<>f:m<gg=83;pD??i;|l;fg<728qC><h4}o:ag?6=9rB9=k5rn9`g>5<6sA8:j6sa8cg94?7|@;;m7p`7bg83>4}O:8l0qc6l0;295~N59o1vb5m>:182M46n2we4n<50;3xL77a3td3o>4?:0yK64`<ug2h87>51zJ15c=zf1i>6=4>{I02b>{i0j<1<7?tH33e?xh?k>0;6<uG20d8yk>d03:1=vF=1g9~j=e>290:wE<>f:m<fg=83;pD??i;|l;gg<728qC><h4}o:`g?6=9rB9=k5rn9ag>5<6sA8:j6sa8bg94?7|@;;m7p`7cg83>4}O:8l0qc6k0;295~N59o1vb5j>:182M46n2we4i<50;3xL77a3td3h>4?:0yK64`<ug2o87>51zJ15c=zf1n>6=4>{I02b>{i0m<1<7?tH33e?xh?l>0;6<uG20d8yk>c03:1=vF=1g9~j=b>290:wE<>f:m<ag=83;pD??i;|l;`g<728qC><h4}o:gg?6=9rB9=k5rn9fg>5<6sA8:j6sa8eg94?7|@;;m7p`7dg83>4}O:8l0qc6j0;295~N59o1vb5k>:182M46n2we4h<50;3xL77a3td3i>4?:0yK64`<ug2n87>51zJ15c=zf1o>6=4>{I02b>{i0l<1<7?tH33e?xh?m>0;6<uG20d8yk>b03:1=vF=1g9~j=c>290:wE<>f:m<`g=83;pD??i;|l;ag<728qC><h4}o:fg?6=9rB9=k5rn9gg>5<6sA8:j6sa8dg94?7|@;;m7p`7eg83>4}O:8l0qc6i0;295~N59o1vb5h>:182M46n2we4k<50;3xL77a3td3j>4?:0yK64`<ug2m87>51zJ15c=zf1l>6=4>{I02b>{i0o<1<7?tH33e?xh?n>0;6<uG20d8yk>a03:1=vF=1g9~j=`>290:wE<>f:m<cg=83;pD??i;|l;bg<728qC><h4}o:eg?6=9rB9=k5rn9dg>5<6sA8:j6sa8gg94?7|@;;m7p`7fg83>4}O:8l0qc7?0;295~N59o1vb4>>:182M46n2we5=<50;3xL77a3twvqMNL{c6a>cb19o;3npNOBz2~DEV|uIJ
\ No newline at end of file diff --git a/src/rtl/ipcore/multiplier_s6.sym b/src/rtl/ipcore/multiplier_s6.sym new file mode 100644 index 0000000..4e151ee --- /dev/null +++ b/src/rtl/ipcore/multiplier_s6.sym @@ -0,0 +1,21 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="multiplier_s6">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2015-7-10T14:52:9</timestamp>
+ <pin polarity="Input" x="0" y="80" name="a[31:0]" />
+ <pin polarity="Input" x="0" y="144" name="b[31:0]" />
+ <pin polarity="Input" x="0" y="240" name="clk" />
+ <pin polarity="Output" x="576" y="80" name="p[63:0]" />
+ <graph>
+ <text style="fontsize:40;fontname:Arial" x="32" y="32">multiplier_s6</text>
+ <rect width="512" x="32" y="32" height="384" />
+ <line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin a[31:0]" />
+ <line x2="32" y1="144" y2="144" style="linewidth:W" x1="0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin b[31:0]" />
+ <line x2="32" y1="240" y2="240" x1="0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="240" type="pin clk" />
+ <line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin p[63:0]" />
+ </graph>
+</symbol>
diff --git a/src/rtl/ipcore/multiplier_s6.v b/src/rtl/ipcore/multiplier_s6.v new file mode 100644 index 0000000..7a7cb5e --- /dev/null +++ b/src/rtl/ipcore/multiplier_s6.v @@ -0,0 +1,1485 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: P.20131013 +// \ \ Application: netgen +// / / Filename: multiplier_s6.v +// /___/ /\ Timestamp: Fri Jul 10 17:52:08 2015 +// \ \ / \ +// \___\/\___\ +// +// Command : -w -sim -ofmt verilog E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/multiplier_s6.ngc E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/multiplier_s6.v +// Device : 6slx45csg324-3 +// Input file : E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/multiplier_s6.ngc +// Output file : E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/multiplier_s6.v +// # of Modules : 1 +// Design Name : multiplier_s6 +// Xilinx : e:\Xilinx\14.7\ISE_DS\ISE\ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module multiplier_s6 ( + clk, a, b, p +)/* synthesis syn_black_box syn_noprune=1 */; + input clk; + input [31 : 0] a; + input [31 : 0] b; + output [63 : 0] p; + + // synthesis translate_off + + wire \blk00000001/sig000001c7 ; + wire \blk00000001/sig000001c6 ; + wire \blk00000001/sig000001c5 ; + wire \blk00000001/sig000001c4 ; + wire \blk00000001/sig000001c3 ; + wire \blk00000001/sig000001c2 ; + wire \blk00000001/sig000001c1 ; + wire \blk00000001/sig000001c0 ; + wire \blk00000001/sig000001bf ; + wire \blk00000001/sig000001be ; + wire \blk00000001/sig000001bd ; + wire \blk00000001/sig000001bc ; + wire \blk00000001/sig000001bb ; + wire \blk00000001/sig000001ba ; + wire \blk00000001/sig000001b9 ; + wire \blk00000001/sig000001b8 ; + wire \blk00000001/sig000001b7 ; + wire \blk00000001/sig000001b6 ; + wire \blk00000001/sig000001b5 ; + wire \blk00000001/sig000001b4 ; + wire \blk00000001/sig000001b3 ; + wire \blk00000001/sig000001b2 ; + wire \blk00000001/sig000001b1 ; + wire \blk00000001/sig000001b0 ; + wire \blk00000001/sig000001af ; + wire \blk00000001/sig000001ae ; + wire \blk00000001/sig000001ad ; + wire \blk00000001/sig000001ac ; + wire \blk00000001/sig000001ab ; + wire \blk00000001/sig000001aa ; + wire \blk00000001/sig000001a9 ; + wire \blk00000001/sig000001a8 ; + wire \blk00000001/sig000001a7 ; + wire \blk00000001/sig000001a6 ; + wire \blk00000001/sig000001a5 ; + wire \blk00000001/sig000001a4 ; + wire \blk00000001/sig000001a3 ; + wire \blk00000001/sig000001a2 ; + wire \blk00000001/sig000001a1 ; + wire \blk00000001/sig000001a0 ; + wire \blk00000001/sig0000019f ; + wire \blk00000001/sig0000019e ; + wire \blk00000001/sig0000019d ; + wire \blk00000001/sig0000019c ; + wire \blk00000001/sig0000019b ; + wire \blk00000001/sig0000019a ; + wire \blk00000001/sig00000199 ; + wire \blk00000001/sig00000198 ; + wire \blk00000001/sig00000197 ; + wire \blk00000001/sig00000196 ; + wire \blk00000001/sig00000195 ; + wire \blk00000001/sig00000194 ; + wire \blk00000001/sig00000193 ; + wire \blk00000001/sig00000192 ; + wire \blk00000001/sig00000191 ; + wire \blk00000001/sig00000190 ; + wire \blk00000001/sig0000018f ; + wire \blk00000001/sig0000018e ; + wire \blk00000001/sig0000018d ; + wire \blk00000001/sig0000018c ; + wire \blk00000001/sig0000018b ; + wire \blk00000001/sig0000018a ; + wire \blk00000001/sig00000189 ; + wire \blk00000001/sig00000188 ; + wire \blk00000001/sig00000187 ; + wire \blk00000001/sig00000186 ; + wire \blk00000001/sig00000185 ; + wire \blk00000001/sig00000184 ; + wire \blk00000001/sig00000183 ; + wire \blk00000001/sig00000182 ; + wire \blk00000001/sig00000181 ; + wire \blk00000001/sig00000180 ; + wire \blk00000001/sig0000017f ; + wire \blk00000001/sig0000017e ; + wire \blk00000001/sig0000017d ; + wire \blk00000001/sig0000017c ; + wire \blk00000001/sig0000017b ; + wire \blk00000001/sig0000017a ; + wire \blk00000001/sig00000179 ; + wire \blk00000001/sig00000178 ; + wire \blk00000001/sig00000177 ; + wire \blk00000001/sig00000176 ; + wire \blk00000001/sig00000175 ; + wire \blk00000001/sig00000174 ; + wire \blk00000001/sig00000173 ; + wire \blk00000001/sig00000172 ; + wire \blk00000001/sig00000171 ; + wire \blk00000001/sig00000170 ; + wire \blk00000001/sig0000016f ; + wire \blk00000001/sig0000016e ; + wire \blk00000001/sig0000016d ; + wire \blk00000001/sig0000016c ; + wire \blk00000001/sig0000016b ; + wire \blk00000001/sig0000016a ; + wire \blk00000001/sig00000169 ; + wire \blk00000001/sig00000168 ; + wire \blk00000001/sig00000167 ; + wire \blk00000001/sig00000166 ; + wire \blk00000001/sig00000165 ; + wire \blk00000001/sig00000164 ; + wire \blk00000001/sig00000163 ; + wire \blk00000001/sig00000162 ; + wire \blk00000001/sig00000161 ; + wire \blk00000001/sig00000160 ; + wire \blk00000001/sig0000015f ; + wire \blk00000001/sig0000015e ; + wire \blk00000001/sig0000015d ; + wire \blk00000001/sig0000015c ; + wire \blk00000001/sig0000015b ; + wire \blk00000001/sig0000015a ; + wire \blk00000001/sig00000159 ; + wire \blk00000001/sig00000158 ; + wire \blk00000001/sig00000157 ; + wire \blk00000001/sig00000156 ; + wire \blk00000001/sig00000155 ; + wire \blk00000001/sig00000154 ; + wire \blk00000001/sig00000153 ; + wire \blk00000001/sig00000152 ; + wire \blk00000001/sig00000151 ; + wire \blk00000001/sig00000150 ; + wire \blk00000001/sig0000014f ; + wire \blk00000001/sig0000014e ; + wire \blk00000001/sig0000014d ; + wire \blk00000001/sig0000014c ; + wire \blk00000001/sig0000014b ; + wire \blk00000001/sig0000014a ; + wire \blk00000001/sig00000149 ; + wire \blk00000001/sig00000148 ; + wire \blk00000001/sig00000147 ; + wire \blk00000001/sig00000146 ; + wire \blk00000001/sig00000145 ; + wire \blk00000001/sig00000144 ; + wire \blk00000001/sig00000143 ; + wire \blk00000001/sig00000142 ; + wire \blk00000001/sig00000141 ; + wire \blk00000001/sig00000140 ; + wire \blk00000001/sig0000013f ; + wire \blk00000001/sig0000013e ; + wire \blk00000001/sig0000013d ; + wire \blk00000001/sig0000013c ; + wire \blk00000001/sig0000013b ; + wire \blk00000001/sig0000013a ; + wire \blk00000001/sig00000139 ; + wire \blk00000001/sig00000138 ; + wire \blk00000001/sig00000137 ; + wire \blk00000001/sig00000136 ; + wire \blk00000001/sig00000135 ; + wire \blk00000001/sig00000134 ; + wire \blk00000001/sig00000133 ; + wire \blk00000001/sig00000132 ; + wire \blk00000001/sig00000131 ; + wire \blk00000001/sig00000130 ; + wire \blk00000001/sig0000012f ; + wire \blk00000001/sig0000012e ; + wire \blk00000001/sig0000012d ; + wire \blk00000001/sig0000012c ; + wire \blk00000001/sig0000012b ; + wire \blk00000001/sig0000012a ; + wire \blk00000001/sig00000129 ; + wire \blk00000001/sig00000128 ; + wire \blk00000001/sig00000127 ; + wire \blk00000001/sig00000126 ; + wire \blk00000001/sig00000125 ; + wire \blk00000001/sig00000124 ; + wire \blk00000001/sig00000123 ; + wire \blk00000001/sig00000122 ; + wire \blk00000001/sig00000121 ; + wire \blk00000001/sig00000120 ; + wire \blk00000001/sig0000011f ; + wire \blk00000001/sig0000011e ; + wire \blk00000001/sig0000011d ; + wire \blk00000001/sig0000011c ; + wire \blk00000001/sig0000011b ; + wire \blk00000001/sig0000011a ; + wire \blk00000001/sig00000119 ; + wire \blk00000001/sig00000118 ; + wire \blk00000001/sig00000117 ; + wire \blk00000001/sig00000116 ; + wire \blk00000001/sig00000115 ; + wire \blk00000001/sig00000114 ; + wire \blk00000001/sig00000113 ; + wire \blk00000001/sig00000112 ; + wire \blk00000001/sig00000111 ; + wire \blk00000001/sig00000110 ; + wire \blk00000001/sig0000010f ; + wire \blk00000001/sig0000010e ; + wire \blk00000001/sig0000010d ; + wire \blk00000001/sig0000010c ; + wire \blk00000001/sig0000010b ; + wire \blk00000001/sig0000010a ; + wire \blk00000001/sig00000109 ; + wire \blk00000001/sig00000108 ; + wire \blk00000001/sig00000107 ; + wire \blk00000001/sig00000106 ; + wire \blk00000001/sig00000105 ; + wire \blk00000001/sig00000104 ; + wire \blk00000001/sig00000103 ; + wire \blk00000001/sig00000102 ; + wire \blk00000001/sig00000101 ; + wire \blk00000001/sig00000100 ; + wire \blk00000001/sig000000ff ; + wire \blk00000001/sig000000fe ; + wire \blk00000001/sig000000fd ; + wire \blk00000001/sig000000fc ; + wire \blk00000001/sig000000fb ; + wire \blk00000001/sig000000fa ; + wire \blk00000001/sig000000f9 ; + wire \blk00000001/sig000000f8 ; + wire \blk00000001/sig000000f7 ; + wire \blk00000001/sig000000f6 ; + wire \blk00000001/sig000000f5 ; + wire \blk00000001/sig000000f4 ; + wire \blk00000001/sig000000f3 ; + wire \blk00000001/sig000000f2 ; + wire \blk00000001/sig000000f1 ; + wire \blk00000001/sig000000f0 ; + wire \blk00000001/sig000000ef ; + wire \blk00000001/sig000000ee ; + wire \blk00000001/sig000000ed ; + wire \blk00000001/sig000000ec ; + wire \blk00000001/sig000000eb ; + wire \blk00000001/sig000000ea ; + wire \blk00000001/sig000000e9 ; + wire \blk00000001/sig000000e8 ; + wire \blk00000001/sig000000e7 ; + wire \blk00000001/sig000000e6 ; + wire \blk00000001/sig000000e5 ; + wire \blk00000001/sig000000e4 ; + wire \blk00000001/sig000000e3 ; + wire \blk00000001/sig000000e2 ; + wire \blk00000001/sig000000e1 ; + wire \blk00000001/sig000000e0 ; + wire \blk00000001/sig000000df ; + wire \blk00000001/sig000000de ; + wire \blk00000001/sig000000dd ; + wire \blk00000001/sig000000dc ; + wire \blk00000001/sig000000db ; + wire \blk00000001/sig000000da ; + wire \blk00000001/sig000000d9 ; + wire \blk00000001/sig000000d8 ; + wire \blk00000001/sig000000d7 ; + wire \blk00000001/sig000000d6 ; + wire \blk00000001/sig000000d5 ; + wire \blk00000001/sig000000d4 ; + wire \blk00000001/sig000000d3 ; + wire \blk00000001/sig000000d2 ; + wire \blk00000001/sig000000d1 ; + wire \blk00000001/sig000000d0 ; + wire \blk00000001/sig000000cf ; + wire \blk00000001/sig000000ce ; + wire \blk00000001/sig000000cd ; + wire \blk00000001/sig000000cc ; + wire \blk00000001/sig000000cb ; + wire \blk00000001/sig000000ca ; + wire \blk00000001/sig000000c9 ; + wire \blk00000001/sig000000c8 ; + wire \blk00000001/sig000000c7 ; + wire \blk00000001/sig000000c6 ; + wire \blk00000001/sig000000c5 ; + wire \blk00000001/sig000000c4 ; + wire \blk00000001/sig000000c3 ; + wire \blk00000001/sig000000c2 ; + wire \blk00000001/sig000000c1 ; + wire \blk00000001/sig000000c0 ; + wire \blk00000001/sig000000bf ; + wire \blk00000001/sig000000be ; + wire \blk00000001/sig000000bd ; + wire \blk00000001/sig000000bc ; + wire \blk00000001/sig000000bb ; + wire \blk00000001/sig000000ba ; + wire \blk00000001/sig000000b9 ; + wire \blk00000001/sig000000b8 ; + wire \blk00000001/sig000000b7 ; + wire \blk00000001/sig000000b6 ; + wire \blk00000001/sig000000b5 ; + wire \blk00000001/sig000000b4 ; + wire \blk00000001/sig000000b3 ; + wire \blk00000001/sig000000b2 ; + wire \blk00000001/sig000000b1 ; + wire \blk00000001/sig000000b0 ; + wire \blk00000001/sig000000af ; + wire \blk00000001/sig000000ae ; + wire \blk00000001/sig000000ad ; + wire \blk00000001/sig000000ac ; + wire \blk00000001/sig000000ab ; + wire \blk00000001/sig000000aa ; + wire \blk00000001/sig000000a9 ; + wire \blk00000001/sig000000a8 ; + wire \blk00000001/sig000000a7 ; + wire \blk00000001/sig000000a6 ; + wire \blk00000001/sig000000a5 ; + wire \blk00000001/sig000000a4 ; + wire \blk00000001/sig000000a3 ; + wire \blk00000001/sig000000a2 ; + wire \blk00000001/sig000000a1 ; + wire \blk00000001/sig000000a0 ; + wire \blk00000001/sig0000009f ; + wire \blk00000001/sig0000009e ; + wire \blk00000001/sig0000009d ; + wire \blk00000001/sig0000009c ; + wire \blk00000001/sig0000009b ; + wire \blk00000001/sig0000009a ; + wire \blk00000001/sig00000099 ; + wire \blk00000001/sig00000098 ; + wire \blk00000001/sig00000097 ; + wire \blk00000001/sig00000096 ; + wire \blk00000001/sig00000095 ; + wire \blk00000001/sig00000094 ; + wire \blk00000001/sig00000093 ; + wire \blk00000001/sig00000092 ; + wire \blk00000001/sig00000091 ; + wire \blk00000001/sig00000090 ; + wire \blk00000001/sig0000008f ; + wire \blk00000001/sig0000008e ; + wire \blk00000001/sig0000008d ; + wire \blk00000001/sig0000008c ; + wire \blk00000001/sig0000008b ; + wire \blk00000001/sig0000008a ; + wire \blk00000001/sig00000089 ; + wire \blk00000001/sig00000088 ; + wire \blk00000001/sig00000087 ; + wire \blk00000001/sig00000086 ; + wire \blk00000001/sig00000085 ; + wire \blk00000001/sig00000084 ; + wire \blk00000001/sig00000083 ; + wire \blk00000001/sig00000082 ; + wire \NLW_blk00000001/blk00000007_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<47>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<46>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<45>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<44>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<43>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<42>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<41>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<40>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<39>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<38>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<37>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<36>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<35>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<34>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<33>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<32>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<31>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<30>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<29>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<28>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<27>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<26>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<25>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<24>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<23>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<22>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<21>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<20>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<19>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<18>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<17>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<16>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<15>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<14>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<13>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<12>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<11>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<10>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<9>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<8>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<7>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<6>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<5>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<4>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<3>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<2>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<1>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_C<0>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<35>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<34>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<33>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<32>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<31>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<30>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<29>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<28>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<27>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<26>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<25>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<24>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<23>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<22>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<21>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<20>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<19>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<18>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<17>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<16>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<15>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<14>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<13>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<12>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<11>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<10>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<9>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<8>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<7>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<6>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<5>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<4>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<3>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<2>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<1>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000007_M<0>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<47>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<46>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<45>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<44>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<43>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<42>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<41>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<40>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<39>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<38>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<37>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<36>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<35>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<34>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<33>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<32>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<31>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<30>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<29>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<28>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<27>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<26>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<25>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<24>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<23>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<22>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<21>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<20>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<19>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<18>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<17>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<16>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<15>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<14>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<13>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<12>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<11>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<10>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<9>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<8>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<7>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<6>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<5>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<4>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<3>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<2>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<1>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_C<0>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<35>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<34>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<33>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<32>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<31>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<30>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<29>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<28>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<27>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<26>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<25>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<24>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<23>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<22>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<21>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<20>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<19>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<18>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<17>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<16>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<15>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<14>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<13>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<12>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<11>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<10>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<9>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<8>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<7>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<6>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<5>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<4>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<3>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<2>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<1>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000006_M<0>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<47>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<46>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<45>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<44>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<43>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<42>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<41>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<40>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<39>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<38>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<37>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<36>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<35>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<34>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<33>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<32>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<31>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<30>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<29>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<28>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<27>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<26>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<25>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<24>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<23>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<22>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<21>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<20>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<19>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<18>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<17>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<16>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<15>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<14>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<13>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<12>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<11>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<10>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<9>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<8>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<7>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<6>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<5>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<4>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<3>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<2>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<1>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_P<0>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<35>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<34>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<33>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<32>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<31>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<30>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<29>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<28>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<27>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<26>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<25>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<24>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<23>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<22>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<21>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<20>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<19>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<18>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<17>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<16>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<15>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<14>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<13>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<12>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<11>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<10>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<9>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<8>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<7>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<6>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<5>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<4>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<3>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<2>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<1>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000005_M<0>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<47>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<46>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<45>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<44>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<43>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<42>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<41>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<40>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<39>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<38>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<37>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<36>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<35>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<33>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<32>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<31>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<30>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<35>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<34>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<33>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<32>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<31>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<30>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<29>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<28>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<27>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<26>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<25>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<24>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<23>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<22>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<21>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<20>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<19>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<18>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<17>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<16>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<15>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<14>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<13>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<12>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<11>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<10>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<9>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<8>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<7>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<6>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<5>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<4>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<3>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<2>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<1>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<0>_UNCONNECTED ; + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000029 ( + .C(clk), + .D(\blk00000001/sig000001a5 ), + .Q(p[0]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000028 ( + .C(clk), + .D(\blk00000001/sig000001a6 ), + .Q(p[1]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000027 ( + .C(clk), + .D(\blk00000001/sig000001a7 ), + .Q(p[2]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000026 ( + .C(clk), + .D(\blk00000001/sig000001a8 ), + .Q(p[3]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000025 ( + .C(clk), + .D(\blk00000001/sig000001a9 ), + .Q(p[4]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000024 ( + .C(clk), + .D(\blk00000001/sig000001aa ), + .Q(p[5]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000023 ( + .C(clk), + .D(\blk00000001/sig000001ab ), + .Q(p[6]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000022 ( + .C(clk), + .D(\blk00000001/sig000001ac ), + .Q(p[7]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000021 ( + .C(clk), + .D(\blk00000001/sig000001ad ), + .Q(p[8]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000020 ( + .C(clk), + .D(\blk00000001/sig000001ae ), + .Q(p[9]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000001f ( + .C(clk), + .D(\blk00000001/sig000001af ), + .Q(p[10]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000001e ( + .C(clk), + .D(\blk00000001/sig000001b0 ), + .Q(p[11]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000001d ( + .C(clk), + .D(\blk00000001/sig000001b1 ), + .Q(p[12]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000001c ( + .C(clk), + .D(\blk00000001/sig000001b2 ), + .Q(p[13]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000001b ( + .C(clk), + .D(\blk00000001/sig000001b3 ), + .Q(p[14]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000001a ( + .C(clk), + .D(\blk00000001/sig000001b4 ), + .Q(p[15]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000019 ( + .C(clk), + .D(\blk00000001/sig000001b5 ), + .Q(p[16]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000018 ( + .C(clk), + .D(\blk00000001/sig00000133 ), + .Q(p[17]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000017 ( + .C(clk), + .D(\blk00000001/sig00000134 ), + .Q(p[18]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000016 ( + .C(clk), + .D(\blk00000001/sig00000135 ), + .Q(p[19]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000015 ( + .C(clk), + .D(\blk00000001/sig00000136 ), + .Q(p[20]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000014 ( + .C(clk), + .D(\blk00000001/sig00000137 ), + .Q(p[21]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000013 ( + .C(clk), + .D(\blk00000001/sig00000138 ), + .Q(p[22]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000012 ( + .C(clk), + .D(\blk00000001/sig00000139 ), + .Q(p[23]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000011 ( + .C(clk), + .D(\blk00000001/sig0000013a ), + .Q(p[24]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000010 ( + .C(clk), + .D(\blk00000001/sig0000013b ), + .Q(p[25]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000000f ( + .C(clk), + .D(\blk00000001/sig0000013c ), + .Q(p[26]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000000e ( + .C(clk), + .D(\blk00000001/sig0000013d ), + .Q(p[27]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000000d ( + .C(clk), + .D(\blk00000001/sig0000013e ), + .Q(p[28]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000000c ( + .C(clk), + .D(\blk00000001/sig0000013f ), + .Q(p[29]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000000b ( + .C(clk), + .D(\blk00000001/sig00000140 ), + .Q(p[30]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000000a ( + .C(clk), + .D(\blk00000001/sig00000141 ), + .Q(p[31]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000009 ( + .C(clk), + .D(\blk00000001/sig00000142 ), + .Q(p[32]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000008 ( + .C(clk), + .D(\blk00000001/sig00000143 ), + .Q(p[33]) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 0 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CREG ( 0 ), + .DREG ( 0 ), + .MREG ( 0 ), + .OPMODEREG ( 0 ), + .PREG ( 0 ), + .RSTTYPE ( "SYNC" ), + .CARRYOUTREG ( 0 )) + \blk00000001/blk00000007 ( + .CECARRYIN(\blk00000001/sig000000b3 ), + .RSTC(\blk00000001/sig000000b3 ), + .RSTCARRYIN(\blk00000001/sig000000b3 ), + .CED(\blk00000001/sig000000b3 ), + .RSTD(\blk00000001/sig000000b3 ), + .CEOPMODE(\blk00000001/sig000000b3 ), + .CEC(\blk00000001/sig000000b3 ), + .CARRYOUTF(\NLW_blk00000001/blk00000007_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000001/sig000000b3 ), + .RSTM(\blk00000001/sig000000b3 ), + .CLK(clk), + .RSTB(\blk00000001/sig000000b3 ), + .CEM(\blk00000001/sig000000b3 ), + .CEB(\blk00000001/sig000000b2 ), + .CARRYIN(\blk00000001/sig000000b3 ), + .CEP(\blk00000001/sig000000b3 ), + .CEA(\blk00000001/sig000000b2 ), + .CARRYOUT(\NLW_blk00000001/blk00000007_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000001/sig000000b3 ), + .RSTP(\blk00000001/sig000000b3 ), + .B({\blk00000001/sig000000b3 , b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), + .BCOUT({\blk00000001/sig000001c7 , \blk00000001/sig000001c6 , \blk00000001/sig000001c5 , \blk00000001/sig000001c4 , \blk00000001/sig000001c3 , +\blk00000001/sig000001c2 , \blk00000001/sig000001c1 , \blk00000001/sig000001c0 , \blk00000001/sig000001bf , \blk00000001/sig000001be , +\blk00000001/sig000001bd , \blk00000001/sig000001bc , \blk00000001/sig000001bb , \blk00000001/sig000001ba , \blk00000001/sig000001b9 , +\blk00000001/sig000001b8 , \blk00000001/sig000001b7 , \blk00000001/sig000001b6 }), + .PCIN({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 }), + .C({\NLW_blk00000001/blk00000007_C<47>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<46>_UNCONNECTED , +\NLW_blk00000001/blk00000007_C<45>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<44>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<43>_UNCONNECTED , +\NLW_blk00000001/blk00000007_C<42>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<41>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<40>_UNCONNECTED , +\NLW_blk00000001/blk00000007_C<39>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<38>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<37>_UNCONNECTED , +\NLW_blk00000001/blk00000007_C<36>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<35>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<34>_UNCONNECTED , +\NLW_blk00000001/blk00000007_C<33>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<32>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<31>_UNCONNECTED , +\NLW_blk00000001/blk00000007_C<30>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<29>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<28>_UNCONNECTED , +\NLW_blk00000001/blk00000007_C<27>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<26>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<25>_UNCONNECTED , +\NLW_blk00000001/blk00000007_C<24>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<23>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<22>_UNCONNECTED , +\NLW_blk00000001/blk00000007_C<21>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<20>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<19>_UNCONNECTED , +\NLW_blk00000001/blk00000007_C<18>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<17>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<16>_UNCONNECTED , +\NLW_blk00000001/blk00000007_C<15>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<14>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<13>_UNCONNECTED , +\NLW_blk00000001/blk00000007_C<12>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<11>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<10>_UNCONNECTED , +\NLW_blk00000001/blk00000007_C<9>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<8>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<7>_UNCONNECTED , +\NLW_blk00000001/blk00000007_C<6>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<5>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<4>_UNCONNECTED , +\NLW_blk00000001/blk00000007_C<3>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<2>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<1>_UNCONNECTED , +\NLW_blk00000001/blk00000007_C<0>_UNCONNECTED }), + .P({\blk00000001/sig000001a4 , \blk00000001/sig000001a3 , \blk00000001/sig000001a2 , \blk00000001/sig000001a1 , \blk00000001/sig000001a0 , +\blk00000001/sig0000019f , \blk00000001/sig0000019e , \blk00000001/sig0000019d , \blk00000001/sig0000019c , \blk00000001/sig0000019b , +\blk00000001/sig0000019a , \blk00000001/sig00000199 , \blk00000001/sig00000198 , \blk00000001/sig00000197 , \blk00000001/sig00000196 , +\blk00000001/sig00000195 , \blk00000001/sig00000194 , \blk00000001/sig00000193 , \blk00000001/sig00000192 , \blk00000001/sig00000191 , +\blk00000001/sig00000190 , \blk00000001/sig0000018f , \blk00000001/sig0000018e , \blk00000001/sig0000018d , \blk00000001/sig0000018c , +\blk00000001/sig0000018b , \blk00000001/sig0000018a , \blk00000001/sig00000189 , \blk00000001/sig00000188 , \blk00000001/sig00000187 , +\blk00000001/sig00000186 , \blk00000001/sig000001b5 , \blk00000001/sig000001b4 , \blk00000001/sig000001b3 , \blk00000001/sig000001b2 , +\blk00000001/sig000001b1 , \blk00000001/sig000001b0 , \blk00000001/sig000001af , \blk00000001/sig000001ae , \blk00000001/sig000001ad , +\blk00000001/sig000001ac , \blk00000001/sig000001ab , \blk00000001/sig000001aa , \blk00000001/sig000001a9 , \blk00000001/sig000001a8 , +\blk00000001/sig000001a7 , \blk00000001/sig000001a6 , \blk00000001/sig000001a5 }), + .OPMODE({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b2 }), + .D({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 }), + .PCOUT({\blk00000001/sig00000185 , \blk00000001/sig00000184 , \blk00000001/sig00000183 , \blk00000001/sig00000182 , \blk00000001/sig00000181 , +\blk00000001/sig00000180 , \blk00000001/sig0000017f , \blk00000001/sig0000017e , \blk00000001/sig0000017d , \blk00000001/sig0000017c , +\blk00000001/sig0000017b , \blk00000001/sig0000017a , \blk00000001/sig00000179 , \blk00000001/sig00000178 , \blk00000001/sig00000177 , +\blk00000001/sig00000176 , \blk00000001/sig00000175 , \blk00000001/sig00000174 , \blk00000001/sig00000173 , \blk00000001/sig00000172 , +\blk00000001/sig00000171 , \blk00000001/sig00000170 , \blk00000001/sig0000016f , \blk00000001/sig0000016e , \blk00000001/sig0000016d , +\blk00000001/sig0000016c , \blk00000001/sig0000016b , \blk00000001/sig0000016a , \blk00000001/sig00000169 , \blk00000001/sig00000168 , +\blk00000001/sig00000167 , \blk00000001/sig00000166 , \blk00000001/sig00000165 , \blk00000001/sig00000164 , \blk00000001/sig00000163 , +\blk00000001/sig00000162 , \blk00000001/sig00000161 , \blk00000001/sig00000160 , \blk00000001/sig0000015f , \blk00000001/sig0000015e , +\blk00000001/sig0000015d , \blk00000001/sig0000015c , \blk00000001/sig0000015b , \blk00000001/sig0000015a , \blk00000001/sig00000159 , +\blk00000001/sig00000158 , \blk00000001/sig00000157 , \blk00000001/sig00000156 }), + .A({\blk00000001/sig000000b3 , a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), + .M({\NLW_blk00000001/blk00000007_M<35>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<34>_UNCONNECTED , +\NLW_blk00000001/blk00000007_M<33>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<32>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<31>_UNCONNECTED , +\NLW_blk00000001/blk00000007_M<30>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<29>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<28>_UNCONNECTED , +\NLW_blk00000001/blk00000007_M<27>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<26>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<25>_UNCONNECTED , +\NLW_blk00000001/blk00000007_M<24>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<23>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<22>_UNCONNECTED , +\NLW_blk00000001/blk00000007_M<21>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<20>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<19>_UNCONNECTED , +\NLW_blk00000001/blk00000007_M<18>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<17>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<16>_UNCONNECTED , +\NLW_blk00000001/blk00000007_M<15>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<14>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<13>_UNCONNECTED , +\NLW_blk00000001/blk00000007_M<12>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<11>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<10>_UNCONNECTED , +\NLW_blk00000001/blk00000007_M<9>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<8>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<7>_UNCONNECTED , +\NLW_blk00000001/blk00000007_M<6>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<5>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<4>_UNCONNECTED , +\NLW_blk00000001/blk00000007_M<3>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<2>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<1>_UNCONNECTED , +\NLW_blk00000001/blk00000007_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 0 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CREG ( 0 ), + .DREG ( 0 ), + .MREG ( 0 ), + .OPMODEREG ( 0 ), + .PREG ( 0 ), + .RSTTYPE ( "SYNC" ), + .CARRYOUTREG ( 0 )) + \blk00000001/blk00000006 ( + .CECARRYIN(\blk00000001/sig000000b3 ), + .RSTC(\blk00000001/sig000000b3 ), + .RSTCARRYIN(\blk00000001/sig000000b3 ), + .CED(\blk00000001/sig000000b3 ), + .RSTD(\blk00000001/sig000000b3 ), + .CEOPMODE(\blk00000001/sig000000b3 ), + .CEC(\blk00000001/sig000000b3 ), + .CARRYOUTF(\NLW_blk00000001/blk00000006_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000001/sig000000b3 ), + .RSTM(\blk00000001/sig000000b3 ), + .CLK(clk), + .RSTB(\blk00000001/sig000000b3 ), + .CEM(\blk00000001/sig000000b3 ), + .CEB(\blk00000001/sig000000b2 ), + .CARRYIN(\blk00000001/sig000000b3 ), + .CEP(\blk00000001/sig000000b3 ), + .CEA(\blk00000001/sig000000b2 ), + .CARRYOUT(\NLW_blk00000001/blk00000006_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000001/sig000000b3 ), + .RSTP(\blk00000001/sig000000b3 ), + .B({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , b[31], b[30], b[29], b[28], b[27], b[26], b[25], b[24], b[23] +, b[22], b[21], b[20], b[19], b[18], b[17]}), + .BCOUT({\blk00000001/sig00000155 , \blk00000001/sig00000154 , \blk00000001/sig00000153 , \blk00000001/sig00000152 , \blk00000001/sig00000151 , +\blk00000001/sig00000150 , \blk00000001/sig0000014f , \blk00000001/sig0000014e , \blk00000001/sig0000014d , \blk00000001/sig0000014c , +\blk00000001/sig0000014b , \blk00000001/sig0000014a , \blk00000001/sig00000149 , \blk00000001/sig00000148 , \blk00000001/sig00000147 , +\blk00000001/sig00000146 , \blk00000001/sig00000145 , \blk00000001/sig00000144 }), + .PCIN({\blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 , \blk00000001/sig000000e0 , \blk00000001/sig000000df , +\blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc , \blk00000001/sig000000db , \blk00000001/sig000000da , +\blk00000001/sig000000d9 , \blk00000001/sig000000d8 , \blk00000001/sig000000d7 , \blk00000001/sig000000d6 , \blk00000001/sig000000d5 , +\blk00000001/sig000000d4 , \blk00000001/sig000000d3 , \blk00000001/sig000000d2 , \blk00000001/sig000000d1 , \blk00000001/sig000000d0 , +\blk00000001/sig000000cf , \blk00000001/sig000000ce , \blk00000001/sig000000cd , \blk00000001/sig000000cc , \blk00000001/sig000000cb , +\blk00000001/sig000000ca , \blk00000001/sig000000c9 , \blk00000001/sig000000c8 , \blk00000001/sig000000c7 , \blk00000001/sig000000c6 , +\blk00000001/sig000000c5 , \blk00000001/sig000000c4 , \blk00000001/sig000000c3 , \blk00000001/sig000000c2 , \blk00000001/sig000000c1 , +\blk00000001/sig000000c0 , \blk00000001/sig000000bf , \blk00000001/sig000000be , \blk00000001/sig000000bd , \blk00000001/sig000000bc , +\blk00000001/sig000000bb , \blk00000001/sig000000ba , \blk00000001/sig000000b9 , \blk00000001/sig000000b8 , \blk00000001/sig000000b7 , +\blk00000001/sig000000b6 , \blk00000001/sig000000b5 , \blk00000001/sig000000b4 }), + .C({\NLW_blk00000001/blk00000006_C<47>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<46>_UNCONNECTED , +\NLW_blk00000001/blk00000006_C<45>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<44>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<43>_UNCONNECTED , +\NLW_blk00000001/blk00000006_C<42>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<41>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<40>_UNCONNECTED , +\NLW_blk00000001/blk00000006_C<39>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<38>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<37>_UNCONNECTED , +\NLW_blk00000001/blk00000006_C<36>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<35>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<34>_UNCONNECTED , +\NLW_blk00000001/blk00000006_C<33>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<32>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<31>_UNCONNECTED , +\NLW_blk00000001/blk00000006_C<30>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<29>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<28>_UNCONNECTED , +\NLW_blk00000001/blk00000006_C<27>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<26>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<25>_UNCONNECTED , +\NLW_blk00000001/blk00000006_C<24>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<23>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<22>_UNCONNECTED , +\NLW_blk00000001/blk00000006_C<21>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<20>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<19>_UNCONNECTED , +\NLW_blk00000001/blk00000006_C<18>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<17>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<16>_UNCONNECTED , +\NLW_blk00000001/blk00000006_C<15>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<14>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<13>_UNCONNECTED , +\NLW_blk00000001/blk00000006_C<12>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<11>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<10>_UNCONNECTED , +\NLW_blk00000001/blk00000006_C<9>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<8>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<7>_UNCONNECTED , +\NLW_blk00000001/blk00000006_C<6>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<5>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<4>_UNCONNECTED , +\NLW_blk00000001/blk00000006_C<3>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<2>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<1>_UNCONNECTED , +\NLW_blk00000001/blk00000006_C<0>_UNCONNECTED }), + .P({\blk00000001/sig00000132 , \blk00000001/sig00000131 , \blk00000001/sig00000130 , \blk00000001/sig0000012f , \blk00000001/sig0000012e , +\blk00000001/sig0000012d , \blk00000001/sig0000012c , \blk00000001/sig0000012b , \blk00000001/sig0000012a , \blk00000001/sig00000129 , +\blk00000001/sig00000128 , \blk00000001/sig00000127 , \blk00000001/sig00000126 , \blk00000001/sig00000125 , \blk00000001/sig00000124 , +\blk00000001/sig00000123 , \blk00000001/sig00000122 , \blk00000001/sig00000121 , \blk00000001/sig00000120 , \blk00000001/sig0000011f , +\blk00000001/sig0000011e , \blk00000001/sig0000011d , \blk00000001/sig0000011c , \blk00000001/sig0000011b , \blk00000001/sig0000011a , +\blk00000001/sig00000119 , \blk00000001/sig00000118 , \blk00000001/sig00000117 , \blk00000001/sig00000116 , \blk00000001/sig00000115 , +\blk00000001/sig00000114 , \blk00000001/sig00000143 , \blk00000001/sig00000142 , \blk00000001/sig00000141 , \blk00000001/sig00000140 , +\blk00000001/sig0000013f , \blk00000001/sig0000013e , \blk00000001/sig0000013d , \blk00000001/sig0000013c , \blk00000001/sig0000013b , +\blk00000001/sig0000013a , \blk00000001/sig00000139 , \blk00000001/sig00000138 , \blk00000001/sig00000137 , \blk00000001/sig00000136 , +\blk00000001/sig00000135 , \blk00000001/sig00000134 , \blk00000001/sig00000133 }), + .OPMODE({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b2 , \blk00000001/sig000000b3 , \blk00000001/sig000000b2 }), + .D({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 }), + .PCOUT({\blk00000001/sig00000113 , \blk00000001/sig00000112 , \blk00000001/sig00000111 , \blk00000001/sig00000110 , \blk00000001/sig0000010f , +\blk00000001/sig0000010e , \blk00000001/sig0000010d , \blk00000001/sig0000010c , \blk00000001/sig0000010b , \blk00000001/sig0000010a , +\blk00000001/sig00000109 , \blk00000001/sig00000108 , \blk00000001/sig00000107 , \blk00000001/sig00000106 , \blk00000001/sig00000105 , +\blk00000001/sig00000104 , \blk00000001/sig00000103 , \blk00000001/sig00000102 , \blk00000001/sig00000101 , \blk00000001/sig00000100 , +\blk00000001/sig000000ff , \blk00000001/sig000000fe , \blk00000001/sig000000fd , \blk00000001/sig000000fc , \blk00000001/sig000000fb , +\blk00000001/sig000000fa , \blk00000001/sig000000f9 , \blk00000001/sig000000f8 , \blk00000001/sig000000f7 , \blk00000001/sig000000f6 , +\blk00000001/sig000000f5 , \blk00000001/sig000000f4 , \blk00000001/sig000000f3 , \blk00000001/sig000000f2 , \blk00000001/sig000000f1 , +\blk00000001/sig000000f0 , \blk00000001/sig000000ef , \blk00000001/sig000000ee , \blk00000001/sig000000ed , \blk00000001/sig000000ec , +\blk00000001/sig000000eb , \blk00000001/sig000000ea , \blk00000001/sig000000e9 , \blk00000001/sig000000e8 , \blk00000001/sig000000e7 , +\blk00000001/sig000000e6 , \blk00000001/sig000000e5 , \blk00000001/sig000000e4 }), + .A({\blk00000001/sig000000b3 , a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), + .M({\NLW_blk00000001/blk00000006_M<35>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<34>_UNCONNECTED , +\NLW_blk00000001/blk00000006_M<33>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<32>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<31>_UNCONNECTED , +\NLW_blk00000001/blk00000006_M<30>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<29>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<28>_UNCONNECTED , +\NLW_blk00000001/blk00000006_M<27>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<26>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<25>_UNCONNECTED , +\NLW_blk00000001/blk00000006_M<24>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<23>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<22>_UNCONNECTED , +\NLW_blk00000001/blk00000006_M<21>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<20>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<19>_UNCONNECTED , +\NLW_blk00000001/blk00000006_M<18>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<17>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<16>_UNCONNECTED , +\NLW_blk00000001/blk00000006_M<15>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<14>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<13>_UNCONNECTED , +\NLW_blk00000001/blk00000006_M<12>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<11>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<10>_UNCONNECTED , +\NLW_blk00000001/blk00000006_M<9>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<8>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<7>_UNCONNECTED , +\NLW_blk00000001/blk00000006_M<6>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<5>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<4>_UNCONNECTED , +\NLW_blk00000001/blk00000006_M<3>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<2>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<1>_UNCONNECTED , +\NLW_blk00000001/blk00000006_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 0 ), + .B1REG ( 0 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CREG ( 0 ), + .DREG ( 0 ), + .MREG ( 0 ), + .OPMODEREG ( 0 ), + .PREG ( 0 ), + .RSTTYPE ( "SYNC" ), + .CARRYOUTREG ( 0 )) + \blk00000001/blk00000005 ( + .CECARRYIN(\blk00000001/sig000000b3 ), + .RSTC(\blk00000001/sig000000b3 ), + .RSTCARRYIN(\blk00000001/sig000000b3 ), + .CED(\blk00000001/sig000000b3 ), + .RSTD(\blk00000001/sig000000b3 ), + .CEOPMODE(\blk00000001/sig000000b3 ), + .CEC(\blk00000001/sig000000b3 ), + .CARRYOUTF(\NLW_blk00000001/blk00000005_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000001/sig000000b3 ), + .RSTM(\blk00000001/sig000000b3 ), + .CLK(clk), + .RSTB(\blk00000001/sig000000b3 ), + .CEM(\blk00000001/sig000000b3 ), + .CEB(\blk00000001/sig000000b3 ), + .CARRYIN(\blk00000001/sig000000b3 ), + .CEP(\blk00000001/sig000000b3 ), + .CEA(\blk00000001/sig000000b2 ), + .CARRYOUT(\NLW_blk00000001/blk00000005_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000001/sig000000b3 ), + .RSTP(\blk00000001/sig000000b3 ), + .B({\blk00000001/sig000001c7 , \blk00000001/sig000001c6 , \blk00000001/sig000001c5 , \blk00000001/sig000001c4 , \blk00000001/sig000001c3 , +\blk00000001/sig000001c2 , \blk00000001/sig000001c1 , \blk00000001/sig000001c0 , \blk00000001/sig000001bf , \blk00000001/sig000001be , +\blk00000001/sig000001bd , \blk00000001/sig000001bc , \blk00000001/sig000001bb , \blk00000001/sig000001ba , \blk00000001/sig000001b9 , +\blk00000001/sig000001b8 , \blk00000001/sig000001b7 , \blk00000001/sig000001b6 }), + .BCOUT({\NLW_blk00000001/blk00000005_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<16>_UNCONNECTED , +\NLW_blk00000001/blk00000005_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<14>_UNCONNECTED , +\NLW_blk00000001/blk00000005_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<12>_UNCONNECTED , +\NLW_blk00000001/blk00000005_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<10>_UNCONNECTED , +\NLW_blk00000001/blk00000005_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<8>_UNCONNECTED , +\NLW_blk00000001/blk00000005_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<6>_UNCONNECTED , +\NLW_blk00000001/blk00000005_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<4>_UNCONNECTED , +\NLW_blk00000001/blk00000005_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<2>_UNCONNECTED , +\NLW_blk00000001/blk00000005_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000001/sig00000185 , \blk00000001/sig00000184 , \blk00000001/sig00000183 , \blk00000001/sig00000182 , \blk00000001/sig00000181 , +\blk00000001/sig00000180 , \blk00000001/sig0000017f , \blk00000001/sig0000017e , \blk00000001/sig0000017d , \blk00000001/sig0000017c , +\blk00000001/sig0000017b , \blk00000001/sig0000017a , \blk00000001/sig00000179 , \blk00000001/sig00000178 , \blk00000001/sig00000177 , +\blk00000001/sig00000176 , \blk00000001/sig00000175 , \blk00000001/sig00000174 , \blk00000001/sig00000173 , \blk00000001/sig00000172 , +\blk00000001/sig00000171 , \blk00000001/sig00000170 , \blk00000001/sig0000016f , \blk00000001/sig0000016e , \blk00000001/sig0000016d , +\blk00000001/sig0000016c , \blk00000001/sig0000016b , \blk00000001/sig0000016a , \blk00000001/sig00000169 , \blk00000001/sig00000168 , +\blk00000001/sig00000167 , \blk00000001/sig00000166 , \blk00000001/sig00000165 , \blk00000001/sig00000164 , \blk00000001/sig00000163 , +\blk00000001/sig00000162 , \blk00000001/sig00000161 , \blk00000001/sig00000160 , \blk00000001/sig0000015f , \blk00000001/sig0000015e , +\blk00000001/sig0000015d , \blk00000001/sig0000015c , \blk00000001/sig0000015b , \blk00000001/sig0000015a , \blk00000001/sig00000159 , +\blk00000001/sig00000158 , \blk00000001/sig00000157 , \blk00000001/sig00000156 }), + .C({\blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , +\blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , +\blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , +\blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a3 , \blk00000001/sig000001a2 , +\blk00000001/sig000001a1 , \blk00000001/sig000001a0 , \blk00000001/sig0000019f , \blk00000001/sig0000019e , \blk00000001/sig0000019d , +\blk00000001/sig0000019c , \blk00000001/sig0000019b , \blk00000001/sig0000019a , \blk00000001/sig00000199 , \blk00000001/sig00000198 , +\blk00000001/sig00000197 , \blk00000001/sig00000196 , \blk00000001/sig00000195 , \blk00000001/sig00000194 , \blk00000001/sig00000193 , +\blk00000001/sig00000192 , \blk00000001/sig00000191 , \blk00000001/sig00000190 , \blk00000001/sig0000018f , \blk00000001/sig0000018e , +\blk00000001/sig0000018d , \blk00000001/sig0000018c , \blk00000001/sig0000018b , \blk00000001/sig0000018a , \blk00000001/sig00000189 , +\blk00000001/sig00000188 , \blk00000001/sig00000187 , \blk00000001/sig00000186 }), + .P({\NLW_blk00000001/blk00000005_P<47>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<46>_UNCONNECTED , +\NLW_blk00000001/blk00000005_P<45>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<44>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<43>_UNCONNECTED , +\NLW_blk00000001/blk00000005_P<42>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<41>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<40>_UNCONNECTED , +\NLW_blk00000001/blk00000005_P<39>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<38>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<37>_UNCONNECTED , +\NLW_blk00000001/blk00000005_P<36>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<34>_UNCONNECTED , +\NLW_blk00000001/blk00000005_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<31>_UNCONNECTED , +\NLW_blk00000001/blk00000005_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<28>_UNCONNECTED , +\NLW_blk00000001/blk00000005_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<25>_UNCONNECTED , +\NLW_blk00000001/blk00000005_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<22>_UNCONNECTED , +\NLW_blk00000001/blk00000005_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<19>_UNCONNECTED , +\NLW_blk00000001/blk00000005_P<18>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<17>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<16>_UNCONNECTED , +\NLW_blk00000001/blk00000005_P<15>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<14>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<13>_UNCONNECTED , +\NLW_blk00000001/blk00000005_P<12>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<11>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<10>_UNCONNECTED , +\NLW_blk00000001/blk00000005_P<9>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<8>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<7>_UNCONNECTED , +\NLW_blk00000001/blk00000005_P<6>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<5>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<4>_UNCONNECTED , +\NLW_blk00000001/blk00000005_P<3>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<2>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<1>_UNCONNECTED , +\NLW_blk00000001/blk00000005_P<0>_UNCONNECTED }), + .OPMODE({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b2 , +\blk00000001/sig000000b2 , \blk00000001/sig000000b3 , \blk00000001/sig000000b2 }), + .D({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 }), + .PCOUT({\blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 , \blk00000001/sig000000e0 , \blk00000001/sig000000df , +\blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc , \blk00000001/sig000000db , \blk00000001/sig000000da , +\blk00000001/sig000000d9 , \blk00000001/sig000000d8 , \blk00000001/sig000000d7 , \blk00000001/sig000000d6 , \blk00000001/sig000000d5 , +\blk00000001/sig000000d4 , \blk00000001/sig000000d3 , \blk00000001/sig000000d2 , \blk00000001/sig000000d1 , \blk00000001/sig000000d0 , +\blk00000001/sig000000cf , \blk00000001/sig000000ce , \blk00000001/sig000000cd , \blk00000001/sig000000cc , \blk00000001/sig000000cb , +\blk00000001/sig000000ca , \blk00000001/sig000000c9 , \blk00000001/sig000000c8 , \blk00000001/sig000000c7 , \blk00000001/sig000000c6 , +\blk00000001/sig000000c5 , \blk00000001/sig000000c4 , \blk00000001/sig000000c3 , \blk00000001/sig000000c2 , \blk00000001/sig000000c1 , +\blk00000001/sig000000c0 , \blk00000001/sig000000bf , \blk00000001/sig000000be , \blk00000001/sig000000bd , \blk00000001/sig000000bc , +\blk00000001/sig000000bb , \blk00000001/sig000000ba , \blk00000001/sig000000b9 , \blk00000001/sig000000b8 , \blk00000001/sig000000b7 , +\blk00000001/sig000000b6 , \blk00000001/sig000000b5 , \blk00000001/sig000000b4 }), + .A({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , a[31], a[30], a[29], a[28], a[27], a[26], a[25], a[24], a[23] +, a[22], a[21], a[20], a[19], a[18], a[17]}), + .M({\NLW_blk00000001/blk00000005_M<35>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<34>_UNCONNECTED , +\NLW_blk00000001/blk00000005_M<33>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<32>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<31>_UNCONNECTED , +\NLW_blk00000001/blk00000005_M<30>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<29>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<28>_UNCONNECTED , +\NLW_blk00000001/blk00000005_M<27>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<26>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<25>_UNCONNECTED , +\NLW_blk00000001/blk00000005_M<24>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<23>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<22>_UNCONNECTED , +\NLW_blk00000001/blk00000005_M<21>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<20>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<19>_UNCONNECTED , +\NLW_blk00000001/blk00000005_M<18>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<17>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<16>_UNCONNECTED , +\NLW_blk00000001/blk00000005_M<15>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<14>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<13>_UNCONNECTED , +\NLW_blk00000001/blk00000005_M<12>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<11>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<10>_UNCONNECTED , +\NLW_blk00000001/blk00000005_M<9>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<8>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<7>_UNCONNECTED , +\NLW_blk00000001/blk00000005_M<6>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<5>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<4>_UNCONNECTED , +\NLW_blk00000001/blk00000005_M<3>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<2>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<1>_UNCONNECTED , +\NLW_blk00000001/blk00000005_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 0 ), + .B1REG ( 0 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CREG ( 0 ), + .DREG ( 0 ), + .MREG ( 0 ), + .OPMODEREG ( 0 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" ), + .CARRYOUTREG ( 0 )) + \blk00000001/blk00000004 ( + .CECARRYIN(\blk00000001/sig000000b3 ), + .RSTC(\blk00000001/sig000000b3 ), + .RSTCARRYIN(\blk00000001/sig000000b3 ), + .CED(\blk00000001/sig000000b3 ), + .RSTD(\blk00000001/sig000000b3 ), + .CEOPMODE(\blk00000001/sig000000b3 ), + .CEC(\blk00000001/sig000000b3 ), + .CARRYOUTF(\NLW_blk00000001/blk00000004_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000001/sig000000b3 ), + .RSTM(\blk00000001/sig000000b3 ), + .CLK(clk), + .RSTB(\blk00000001/sig000000b3 ), + .CEM(\blk00000001/sig000000b3 ), + .CEB(\blk00000001/sig000000b3 ), + .CARRYIN(\blk00000001/sig000000b3 ), + .CEP(\blk00000001/sig000000b2 ), + .CEA(\blk00000001/sig000000b2 ), + .CARRYOUT(\NLW_blk00000001/blk00000004_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000001/sig000000b3 ), + .RSTP(\blk00000001/sig000000b3 ), + .B({\blk00000001/sig00000155 , \blk00000001/sig00000154 , \blk00000001/sig00000153 , \blk00000001/sig00000152 , \blk00000001/sig00000151 , +\blk00000001/sig00000150 , \blk00000001/sig0000014f , \blk00000001/sig0000014e , \blk00000001/sig0000014d , \blk00000001/sig0000014c , +\blk00000001/sig0000014b , \blk00000001/sig0000014a , \blk00000001/sig00000149 , \blk00000001/sig00000148 , \blk00000001/sig00000147 , +\blk00000001/sig00000146 , \blk00000001/sig00000145 , \blk00000001/sig00000144 }), + .BCOUT({\NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED , +\NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED , +\NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED , +\NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED , +\NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED , +\NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED , +\NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED , +\NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED , +\NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000001/sig00000113 , \blk00000001/sig00000112 , \blk00000001/sig00000111 , \blk00000001/sig00000110 , \blk00000001/sig0000010f , +\blk00000001/sig0000010e , \blk00000001/sig0000010d , \blk00000001/sig0000010c , \blk00000001/sig0000010b , \blk00000001/sig0000010a , +\blk00000001/sig00000109 , \blk00000001/sig00000108 , \blk00000001/sig00000107 , \blk00000001/sig00000106 , \blk00000001/sig00000105 , +\blk00000001/sig00000104 , \blk00000001/sig00000103 , \blk00000001/sig00000102 , \blk00000001/sig00000101 , \blk00000001/sig00000100 , +\blk00000001/sig000000ff , \blk00000001/sig000000fe , \blk00000001/sig000000fd , \blk00000001/sig000000fc , \blk00000001/sig000000fb , +\blk00000001/sig000000fa , \blk00000001/sig000000f9 , \blk00000001/sig000000f8 , \blk00000001/sig000000f7 , \blk00000001/sig000000f6 , +\blk00000001/sig000000f5 , \blk00000001/sig000000f4 , \blk00000001/sig000000f3 , \blk00000001/sig000000f2 , \blk00000001/sig000000f1 , +\blk00000001/sig000000f0 , \blk00000001/sig000000ef , \blk00000001/sig000000ee , \blk00000001/sig000000ed , \blk00000001/sig000000ec , +\blk00000001/sig000000eb , \blk00000001/sig000000ea , \blk00000001/sig000000e9 , \blk00000001/sig000000e8 , \blk00000001/sig000000e7 , +\blk00000001/sig000000e6 , \blk00000001/sig000000e5 , \blk00000001/sig000000e4 }), + .C({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , +\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , +\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , +\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000131 , \blk00000001/sig00000130 , +\blk00000001/sig0000012f , \blk00000001/sig0000012e , \blk00000001/sig0000012d , \blk00000001/sig0000012c , \blk00000001/sig0000012b , +\blk00000001/sig0000012a , \blk00000001/sig00000129 , \blk00000001/sig00000128 , \blk00000001/sig00000127 , \blk00000001/sig00000126 , +\blk00000001/sig00000125 , \blk00000001/sig00000124 , \blk00000001/sig00000123 , \blk00000001/sig00000122 , \blk00000001/sig00000121 , +\blk00000001/sig00000120 , \blk00000001/sig0000011f , \blk00000001/sig0000011e , \blk00000001/sig0000011d , \blk00000001/sig0000011c , +\blk00000001/sig0000011b , \blk00000001/sig0000011a , \blk00000001/sig00000119 , \blk00000001/sig00000118 , \blk00000001/sig00000117 , +\blk00000001/sig00000116 , \blk00000001/sig00000115 , \blk00000001/sig00000114 }), + .P({\NLW_blk00000001/blk00000004_P<47>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<46>_UNCONNECTED , +\NLW_blk00000001/blk00000004_P<45>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<44>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<43>_UNCONNECTED , +\NLW_blk00000001/blk00000004_P<42>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<41>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<40>_UNCONNECTED , +\NLW_blk00000001/blk00000004_P<39>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<38>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<37>_UNCONNECTED , +\NLW_blk00000001/blk00000004_P<36>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED , +\NLW_blk00000001/blk00000004_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<31>_UNCONNECTED , +\NLW_blk00000001/blk00000004_P<30>_UNCONNECTED , p[63], p[62], p[61], p[60], p[59], p[58], p[57], p[56], p[55], p[54], p[53], p[52], p[51], p[50], +p[49], p[48], p[47], p[46], p[45], p[44], p[43], p[42], p[41], p[40], p[39], p[38], p[37], p[36], p[35], p[34]}), + .OPMODE({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b2 , +\blk00000001/sig000000b2 , \blk00000001/sig000000b3 , \blk00000001/sig000000b2 }), + .D({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , +\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 }), + .PCOUT({\blk00000001/sig00000082 , \blk00000001/sig00000083 , \blk00000001/sig00000084 , \blk00000001/sig00000085 , \blk00000001/sig00000086 , +\blk00000001/sig00000087 , \blk00000001/sig00000088 , \blk00000001/sig00000089 , \blk00000001/sig0000008a , \blk00000001/sig0000008b , +\blk00000001/sig0000008c , \blk00000001/sig0000008d , \blk00000001/sig0000008e , \blk00000001/sig0000008f , \blk00000001/sig00000090 , +\blk00000001/sig00000091 , \blk00000001/sig00000092 , \blk00000001/sig00000093 , \blk00000001/sig00000094 , \blk00000001/sig00000095 , +\blk00000001/sig00000096 , \blk00000001/sig00000097 , \blk00000001/sig00000098 , \blk00000001/sig00000099 , \blk00000001/sig0000009a , +\blk00000001/sig0000009b , \blk00000001/sig0000009c , \blk00000001/sig0000009d , \blk00000001/sig0000009e , \blk00000001/sig0000009f , +\blk00000001/sig000000a0 , \blk00000001/sig000000a1 , \blk00000001/sig000000a2 , \blk00000001/sig000000a3 , \blk00000001/sig000000a4 , +\blk00000001/sig000000a5 , \blk00000001/sig000000a6 , \blk00000001/sig000000a7 , \blk00000001/sig000000a8 , \blk00000001/sig000000a9 , +\blk00000001/sig000000aa , \blk00000001/sig000000ab , \blk00000001/sig000000ac , \blk00000001/sig000000ad , \blk00000001/sig000000ae , +\blk00000001/sig000000af , \blk00000001/sig000000b0 , \blk00000001/sig000000b1 }), + .A({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , a[31], a[30], a[29], a[28], a[27], a[26], a[25], a[24], a[23] +, a[22], a[21], a[20], a[19], a[18], a[17]}), + .M({\NLW_blk00000001/blk00000004_M<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<34>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<33>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<32>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<31>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<30>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<29>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<28>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<27>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<26>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<25>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<24>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<23>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<22>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<21>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<20>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<19>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<18>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<16>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<14>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<13>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<12>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<10>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<8>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<7>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<6>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<4>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<2>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<1>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<0>_UNCONNECTED }) + ); + GND \blk00000001/blk00000003 ( + .G(\blk00000001/sig000000b3 ) + ); + VCC \blk00000001/blk00000002 ( + .P(\blk00000001/sig000000b2 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/src/rtl/ipcore/multiplier_s6.veo b/src/rtl/ipcore/multiplier_s6.veo new file mode 100644 index 0000000..fede3ea --- /dev/null +++ b/src/rtl/ipcore/multiplier_s6.veo @@ -0,0 +1,65 @@ +/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used solely *
+* for design, simulation, implementation and creation of design files *
+* limited to Xilinx devices or technologies. Use with non-Xilinx *
+* devices or technologies is expressly prohibited and immediately *
+* terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
+* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
+* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
+* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
+* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
+* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
+* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
+* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
+* PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support appliances, *
+* devices, or systems. Use in such applications are expressly *
+* prohibited. *
+* *
+* (c) Copyright 1995-2015 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+
+/*******************************************************************************
+* Generated from core with identifier: xilinx.com:ip:mult_gen:11.2 *
+* *
+* Multiplication is a fundamental DSP operation. This core allows *
+* parallel and constant-coefficient multipliers to be generated. The *
+* user can specify if dedicated hardware multipliers, slice logic or a *
+* combination of resources should be utilized. *
+*******************************************************************************/
+
+// Interfaces:
+// a_intf
+// clk_intf
+// sclr_intf
+// ce_intf
+// b_intf
+// zero_detect_intf
+// p_intf
+// pcasc_intf
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+multiplier_s6 your_instance_name (
+ .clk(clk), // input clk
+ .a(a), // input [31 : 0] a
+ .b(b), // input [31 : 0] b
+ .p(p) // output [63 : 0] p
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file multiplier_s6.v when simulating
+// the core, multiplier_s6. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/src/rtl/ipcore/multiplier_s6.xco b/src/rtl/ipcore/multiplier_s6.xco new file mode 100644 index 0000000..5dcc8fd --- /dev/null +++ b/src/rtl/ipcore/multiplier_s6.xco @@ -0,0 +1,68 @@ +##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Fri Jul 10 14:51:47 2015
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:mult_gen:11.2
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Multiplier xilinx.com:ip:mult_gen:11.2
+# END Select
+# BEGIN Parameters
+CSET ccmimp=Distributed_Memory
+CSET clockenable=false
+CSET component_name=multiplier_s6
+CSET constvalue=129
+CSET internaluser=0
+CSET multiplier_construction=Use_Mults
+CSET multtype=Parallel_Multiplier
+CSET optgoal=Speed
+CSET outputwidthhigh=63
+CSET outputwidthlow=0
+CSET pipestages=2
+CSET portatype=Unsigned
+CSET portawidth=32
+CSET portbtype=Unsigned
+CSET portbwidth=32
+CSET roundpoint=0
+CSET sclrcepriority=SCLR_Overrides_CE
+CSET syncclear=false
+CSET use_custom_output_width=false
+CSET userounding=false
+CSET zerodetect=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2013-07-22T11:36:26Z
+# END Extra information
+GENERATE
+# CRC: 66788057
diff --git a/src/rtl/ipcore/multiplier_s6.xise b/src/rtl/ipcore/multiplier_s6.xise new file mode 100644 index 0000000..483e01a --- /dev/null +++ b/src/rtl/ipcore/multiplier_s6.xise @@ -0,0 +1,73 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="multiplier_s6.ngc" xil_pn:type="FILE_NGC"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="multiplier_s6.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/> + </file> + </files> + + <properties> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|multiplier_s6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="multiplier_s6.ngc" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/multiplier_s6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_DesignName" xil_pn:value="multiplier_s6" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-07-10T17:52:14" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7F8BDEE2A3114E3F8A92547B65F9CA26" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/src/rtl/ipcore/multiplier_s6/doc/mult_gen_ds255.pdf b/src/rtl/ipcore/multiplier_s6/doc/mult_gen_ds255.pdf Binary files differnew file mode 100644 index 0000000..b589be0 --- /dev/null +++ b/src/rtl/ipcore/multiplier_s6/doc/mult_gen_ds255.pdf diff --git a/src/rtl/ipcore/multiplier_s6/doc/mult_gen_v11_2_readme.txt b/src/rtl/ipcore/multiplier_s6/doc/mult_gen_v11_2_readme.txt new file mode 100644 index 0000000..e50dfe8 --- /dev/null +++ b/src/rtl/ipcore/multiplier_s6/doc/mult_gen_v11_2_readme.txt @@ -0,0 +1,184 @@ +CHANGE LOG for Xilinx LogiCORE Multiplier 11.2 + +Release Date: October 2, 2013 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + + This file contains the change log for all released versions of the Xilinx + LogiCORE IP Multiplier. + + For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/multiplier.htm + + For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + + For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + + +2. DEVICE SUPPORT + + 2.1. ISE + + The following device families are supported by the core for this release: + + All Series 7 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Virtex-4 devices + All Spartan-3 devices + + +3. NEW FEATURE HISTORY + + 3.1 ISE + + v11.2 + - Ongoing new device support. + + +4. RESOLVED ISSUES + + 4.1 ISE + + - N/A + + +5. KNOWN ISSUES & LIMITATIONS + + The following are known issues for this core at time of release: + + 5.1 ISE + - Output bus indices in .ASY file do not match instantiation template bus indices + when a custom output width is selected. + - The indices of the P output bus will be P[X:Y] in the .ASY file and P[X-Y:0] in + the core instantiation template. + - Affects schematic flow only. + - Manually editing the .ASY file to correct the bus width can work around this issue. + - CR456322 and CR435084 + - Answer Record 30807 + + - Block Memory resource estimates may be inaccurate for constant-coefficient multipliers + with large constants and large A input widths (> 35 bits) + - The map report should be consulted to determine the true block memory count + - CR469169 + - Answer Record 30810 + + - For a comprehensive listing of Known Issues for this core, please see the IP + Release Notes Guide, + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +6. TECHNICAL SUPPORT & FEEDBACK + + To obtain technical support, create a WebCase at www.xilinx.com/support. + Questions are routed to a team with expertise using this product. + Please feel free to leave feedback on this IP under the "Leave Feedback" + menu item in Vivado/PlanAhead. + + Xilinx provides technical support for use of this product when used + according to the guidelines described in the core documentation, and + cannot guarantee timing, functionality, or support of this product for + designs that do not follow specified guidelines. + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +02/10/2013 Xilinx, Inc. 11.2 ISE 14.7 support and Production support for Series 7 +06/19/2012 Xilinx, Inc. 11.2 ISE 14.6 support +03/20/2012 Xilinx, Inc. 11.2 ISE 14.5 support. +12/18/2012 Xilinx, Inc. 11.2 ISE 14.4 and Vivado 2012.4 support +10/16/2012 Xilinx, Inc. 11.2 ISE 14.3 and Vivado 2012.3 support +07/25/2012 Xilinx, Inc. 11.2 ISE 14.2 and Vivado 2012.2 support +04/24/2012 Xilinx, Inc. 11.2 ISE 14.1 and Vivado 2012.1 support +01/11/2012 Xilinx, Inc. 11.2 ISE 13.4 support +10/19/2011 Xilinx, Inc. 11.2 ISE 13.3 support +06/22/2011 Xilinx, Inc. 11.2 ISE 13.2 support, Artix-7 support +03/01/2011 Xilinx, Inc. 11.2 ISE 13.1 support, Virtex-7 and Kintex-7 support +10/29/2010 Xilinx, Inc. 11.2 ISE 7 Series Monthly Snapshot - (O.28), ISE 13.0.2 support +07/30/2010 Xilinx, Inc. 11.2 ISE 13.0.1, Virtex-7 and Kintex-7 support +04/19/2010 Xilinx, Inc. 11.2 ISE 12.1, Virtex-6Q and Spartan-6Q support +12/02/2009 Xilinx, Inc. 11.2 ISE 11.4 support, Spartan-6L and Automotive Spartan6 support +09/16/2009 Xilinx, Inc. 11.2 ISE 11.3 support, area optimized LUT multiplier +04/24/2009 Xilinx, Inc. 11.0 ISE 11.1 support, Virtex-6, Spartan-6 support +04/25/2008 Xilinx, Inc. 10.1 ISE 10.1 support +================================================================================ + + +8. LEGAL DISCLAIMER + + (c) Copyright 2000 - 2013 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + diff --git a/src/rtl/ipcore/multiplier_s6/doc/mult_gen_v11_2_vinfo.html b/src/rtl/ipcore/multiplier_s6/doc/mult_gen_v11_2_vinfo.html new file mode 100644 index 0000000..ebe6f62 --- /dev/null +++ b/src/rtl/ipcore/multiplier_s6/doc/mult_gen_v11_2_vinfo.html @@ -0,0 +1,195 @@ +<HTML> +<HEAD> +<TITLE>mult_gen_v11_2_vinfo</TITLE> +<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1"> +</HEAD> +<BODY> +<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1"> +CHANGE LOG for Xilinx LogiCORE Multiplier 11.2 + +Release Date: October 2, 2013 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + + This file contains the change log for all released versions of the Xilinx + LogiCORE IP Multiplier. + + For the latest core updates, see the product page at: + + <A HREF="http://www.xilinx.com/products/ipcenter/multiplier.htm">www.xilinx.com/products/ipcenter/multiplier.htm</A> + + For installation instructions for this release, please go to: + + <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A> + + For system requirements: + + <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A> + + +2. DEVICE SUPPORT + + 2.1. ISE + + The following device families are supported by the core for this release: + + All Series 7 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Virtex-4 devices + All Spartan-3 devices + + +3. NEW FEATURE HISTORY + + 3.1 ISE + + v11.2 + - Ongoing new device support. + + +4. RESOLVED ISSUES + + 4.1 ISE + + - N/A + + +5. KNOWN ISSUES & LIMITATIONS + + The following are known issues for this core at time of release: + + 5.1 ISE + - Output bus indices in .ASY file do not match instantiation template bus indices + when a custom output width is selected. + - The indices of the P output bus will be P[X:Y] in the .ASY file and P[X-Y:0] in + the core instantiation template. + - Affects schematic flow only. + - Manually editing the .ASY file to correct the bus width can work around this issue. + - CR456322 and CR435084 + - Answer Record 30807 + + - Block Memory resource estimates may be inaccurate for constant-coefficient multipliers + with large constants and large A input widths (> 35 bits) + - The map report should be consulted to determine the true block memory count + - CR469169 + - Answer Record 30810 + + - For a comprehensive listing of Known Issues for this core, please see the IP + Release Notes Guide, + + <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A> + + +6. TECHNICAL SUPPORT & FEEDBACK + + To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A> + Questions are routed to a team with expertise using this product. + Please feel free to leave feedback on this IP under the "Leave Feedback" + menu item in Vivado/PlanAhead. + + Xilinx provides technical support for use of this product when used + according to the guidelines described in the core documentation, and + cannot guarantee timing, functionality, or support of this product for + designs that do not follow specified guidelines. + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A> + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +02/10/2013 Xilinx, Inc. 11.2 ISE 14.7 support and Production support for Series 7 +06/19/2012 Xilinx, Inc. 11.2 ISE 14.6 support +03/20/2012 Xilinx, Inc. 11.2 ISE 14.5 support. +12/18/2012 Xilinx, Inc. 11.2 ISE 14.4 and Vivado 2012.4 support +10/16/2012 Xilinx, Inc. 11.2 ISE 14.3 and Vivado 2012.3 support +07/25/2012 Xilinx, Inc. 11.2 ISE 14.2 and Vivado 2012.2 support +04/24/2012 Xilinx, Inc. 11.2 ISE 14.1 and Vivado 2012.1 support +01/11/2012 Xilinx, Inc. 11.2 ISE 13.4 support +10/19/2011 Xilinx, Inc. 11.2 ISE 13.3 support +06/22/2011 Xilinx, Inc. 11.2 ISE 13.2 support, Artix-7 support +03/01/2011 Xilinx, Inc. 11.2 ISE 13.1 support, Virtex-7 and Kintex-7 support +10/29/2010 Xilinx, Inc. 11.2 ISE 7 Series Monthly Snapshot - (O.28), ISE 13.0.2 support +07/30/2010 Xilinx, Inc. 11.2 ISE 13.0.1, Virtex-7 and Kintex-7 support +04/19/2010 Xilinx, Inc. 11.2 ISE 12.1, Virtex-6Q and Spartan-6Q support +12/02/2009 Xilinx, Inc. 11.2 ISE 11.4 support, Spartan-6L and Automotive Spartan6 support +09/16/2009 Xilinx, Inc. 11.2 ISE 11.3 support, area optimized LUT multiplier +04/24/2009 Xilinx, Inc. 11.0 ISE 11.1 support, Virtex-6, Spartan-6 support +04/25/2008 Xilinx, Inc. 10.1 ISE 10.1 support +================================================================================ + + +8. LEGAL DISCLAIMER + + (c) Copyright 2000 - 2013 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + +</FONT> +</PRE> +</BODY> +</HTML> diff --git a/src/rtl/ipcore/multiplier_s6_flist.txt b/src/rtl/ipcore/multiplier_s6_flist.txt new file mode 100644 index 0000000..4896d2e --- /dev/null +++ b/src/rtl/ipcore/multiplier_s6_flist.txt @@ -0,0 +1,14 @@ +# Output products list for <multiplier_s6>
+multiplier_s6.asy
+multiplier_s6.gise
+multiplier_s6.ngc
+multiplier_s6.sym
+multiplier_s6.v
+multiplier_s6.veo
+multiplier_s6.xco
+multiplier_s6.xise
+multiplier_s6\doc\mult_gen_ds255.pdf
+multiplier_s6\doc\mult_gen_v11_2_readme.txt
+multiplier_s6\doc\mult_gen_v11_2_vinfo.html
+multiplier_s6_flist.txt
+multiplier_s6_xmdf.tcl
diff --git a/src/rtl/ipcore/multiplier_s6_xmdf.tcl b/src/rtl/ipcore/multiplier_s6_xmdf.tcl new file mode 100644 index 0000000..d528e82 --- /dev/null +++ b/src/rtl/ipcore/multiplier_s6_xmdf.tcl @@ -0,0 +1,83 @@ +# The package naming convention is <core_name>_xmdf
+package provide multiplier_s6_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::multiplier_s6_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::multiplier_s6_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name multiplier_s6
+}
+# ::multiplier_s6_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::multiplier_s6_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6/doc/mult_gen_ds255.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6/doc/mult_gen_v11_2_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6/doc/mult_gen_v11_2_vinfo.html
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6.sym
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module multiplier_s6
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/src/rtl/ipcore/subtractor_s6.asy b/src/rtl/ipcore/subtractor_s6.asy new file mode 100644 index 0000000..560370c --- /dev/null +++ b/src/rtl/ipcore/subtractor_s6.asy @@ -0,0 +1,25 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 subtractor_s6 +RECTANGLE Normal 32 32 256 416 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName a[31:0] +PINATTR Polarity IN +LINE Wide 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName b[31:0] +PINATTR Polarity IN +LINE Normal 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName c_in +PINATTR Polarity IN +LINE Normal 288 80 256 80 +PIN 288 80 RIGHT 36 +PINATTR PinName c_out +PINATTR Polarity OUT +LINE Wide 288 112 256 112 +PIN 288 112 RIGHT 36 +PINATTR PinName s[31:0] +PINATTR Polarity OUT +
diff --git a/src/rtl/ipcore/subtractor_s6.gise b/src/rtl/ipcore/subtractor_s6.gise new file mode 100644 index 0000000..c2a3b35 --- /dev/null +++ b/src/rtl/ipcore/subtractor_s6.gise @@ -0,0 +1,53 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="subtractor_s6.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="subtractor_s6.asy" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="subtractor_s6.sym" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="subtractor_s6.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">
+ <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1436912095">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8902187064276878470" xil_pn:start_ts="1436912095">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7048037620017930327" xil_pn:start_ts="1436912095">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1436912095">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3171076194908862408" xil_pn:start_ts="1436912095">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ </transforms>
+
+</generated_project>
diff --git a/src/rtl/ipcore/subtractor_s6.ncf b/src/rtl/ipcore/subtractor_s6.ncf new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/rtl/ipcore/subtractor_s6.ncf diff --git a/src/rtl/ipcore/subtractor_s6.ngc b/src/rtl/ipcore/subtractor_s6.ngc new file mode 100644 index 0000000..4a930b6 --- /dev/null +++ b/src/rtl/ipcore/subtractor_s6.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$3g544<,[o}e~g`n;"2*73>(-80!<??;0:9MKVR\3K7=:4?>0285=<NFY__6O2>7;2=56=603CE\XZ5BBKM841=87;;7<65IORVP?B;9>0;2<;4198LQQVR\3HHCXZ31683:46<;;0BB][[:@>05?699918>7GAPTV9F956294:<6==:HLSQQ<f4:;1<3??;209MKVR\3h7?<4?>03877<H]]Z^X7]33083:47<;;0DYY^ZT;q?74<768;0?;4@UURVP?K;;<0;2<>4498JJUSS2J6?;7>11297<?OIX\^1\NGA<5594;763=21CXZ_UU8S811=87;>7965OTVSQQ<WKF__09950?g82vj<<ixk><;-230?=<NFY__6B^BOEG?3?69=2K;^HI:;@3QAB2<I5:596O311<6?D:697?0M1?=>49B8459=2K7=90:;@>21;3<I5;=2:5N<0594;3<I5;<285N<0:=1>G;904?7L2>>49B8769=2K7><0:;@>16;3<I588285N<36=1>G;:<4>7L2=6?78E9406<1J0?615:C?6<833H69285N<22=3>G;;80;285N<23=0>G;;7>0M1:14:C?1;2<I5<586O37?68E9>9<2K753=4AEF6?G6UMN?0N<\JG59A85823K6:<3;4B=32:0=E488596L312<6?G:6<7?0N1?:>49A8409?2H7=:4?>49A8419=2H7=50:;C>2=;2<J5;596L321<6?G:597?0N1<=>49A8759=2H7>90:;C>11;3<J58=285M<35=1>D;:14>7O2=9?68F949=2H7?=08;C>05?69=2H7?<0;;C>0:1=E4=4?7O2:>59A83833K6<295M<9<7?G:>6>1IOD@30?:8FFOI48:546LLIO>25;><JJCE0<<18:@@MK:6;720NNGA<06=<>DDAG6:9364BBKM8409i2HHEC2>7;2=<>DDAG6:;394BBKM84803KIBB1<17:@@MK:46>1IOD@34?58FFOI4<4<7OMFN=4=3>DDAG6<2:5MCHL?<;1<JJCE0407;CALQQ:7601IOB[[<02==>DDG\^7=<06;CALQQ:6:730NNAZT=30:<=EKF__0<:19:@@KPR;9<427OM@UU>22;d<JJE^X1?8:1<:?GEH]]6:;364BBMVP97902HHCXZ32?:8FFIR\59546LLOTV?0;><JJE^X1;18:@@KPR;>720NNAZT=5=<>DDG\^74364BBMVP9?902H^_RGAFN48F\VF[Z>0O1>15:A?55823J6:=3;4C=31:0=D489596M315<6?F:6=7?0O1?9>49@8419=2I7=50:;B>2=;2<K5;596M321<6?F:597?0O1<=>49@8759=2I7>90:;B>11;3<K58=285L<35=1>E;:14>7N2=9?68G949=2I7?=0:;B>05;3<K599285L<21=1>E;;=4>7N2<5?78G9516<1H0>915:A?7=823J6853:4C=1=1>E;<94>7N2;1?78G9256<1H09=15:A?01823J6?93;4C=65:2=D4==1<3;4C=64:1=D4=4?7N2:>59@83833J6<295L<9<7?F:>6>1HM_\VIOc8GDTUQ@DYIJo4C@PQ]LHTME20OL\]YNWW=>EFZ[SDYYHm;BCQV\IR\[OL>6MJ3:AFE6=DMK90OHM6;BG@EWT^AG90OHJ<;BGN<>EBGYGDHH=4CDR26>EOMJAT@DMJNRG\P\VB;2IGG95LLJ25?FJL91:=7NBD2626?FJL:Q20OAE=X0:31>EKC0:>7NBDA058GIMF9M8<7NBDA0F73>EKCH;O485LLJ@21>EKCJ;>7NBDD078GIMC^j1H@FJY_EKUMAC23JF@JU64CMIE\4>712IDA@G[TDF20>EHZLULICK]AUKLJZOINF=0O_KNTDF7?FTBO=1HSD@:;B]LQQ2<L5:596J311<6?A:697?0H1?=>49G8459=2N7=90:;E>21;3<L5;=2:5K<0594;3<L5;<295K<0<7?A:56=1O0>0;;E>7:1=C4<4?7I29>59G82833M63295K<8<7?ATBO>1O_]:7A038C6=@FM<0@BOKEE48HJELMM=0@BIFC@N7?H:76<1F0<>15:O?54823D6:>3;4M=30:0=J48>596C314<6?H:6>7?0A1?8>49N84>9=2G7=40;;L>2:0=J4;:596C320<6?H:5:7?0A1<<>49N8729=2G7>80:;L>12;3<E58<285B<3:=1>K;:04?7@2=>49N8669=2G7?<0:;L>06;3<E598285B<26=3>K;;<0;285B<27=0>K;;7>0A1:14:O?1;2<E5<586C37?68I9>9<2G753:4MSGDg>Kfbfx]i}fooa8Ilhhz_oydaa7:LFPRIUC>1D\@AKE4;8KUKHLL6;245@PLMGA97912E[ABJJ<3<:?JVJGMO7?374OQOL@@:3601D\@AKE=7==>IWEFNN0;0m;NRNKAC;?3:556A_MNFF828>3FZFCIK]EF34?JVSADCQIR^]ILKWMSCTWGMHm6Amftq`eqiu92Zh7] =0012445XD=1[0=0:;Q>24;3<X5;:285_<00=1>V;9:4>7]2>4?78T9726<1[0<815:R?52823Y6:43;4P=3::1=W484>7]2=0?78T9466<1[0?<15:R?66823Y6983;4P=06:0=W4;<596^326<6?U:507?0\1<6>59S87823Y68<3;4P=12:0=W4:8596^332<6?U:4<7?0\1=:>49S8609=2Z7?:0:;Q>0<;3<X592295_<2<6?U:387?0\1:>>49S8149=2Z78>0:;Q>70;3<X5>>285_<54=3>V;<>0;285_<55=0>V;<7>0\1;14:R?2;2<X5=586^38?68T9?9<2ZJ^Y94PBKM858?3YIBB1??>99SGLH;98437]MFN=31:==WK@D7=>07;QAJJ973611[OD@314<;?UENF5;=255_CHL?528?3YIBB1?7>99SGLH;904<7]MFN=3=<>VDAG69<364PBKM877902ZHEC2=2?:8TFOI4;9546^LIO>10;><XJCE0?;18:R@MK:5>720\NGA<35=<>VDAG694364PBKM87?9?2ZHEC2=>99SGLH;;9437]MFN=12:==WK@D7??07;QAJJ954611[OD@335<;?UENF59>255_CHL?738?3YIBB1=8>99SGLH;;1437]MFN=1::2=WK@D7?364PBKM816902ZHEC2;1?:8TFOI4=8546^LIO>77;><XJCE09:18:R@MK:3=720\NGA<54=e>VDAG6?;7>18:R@MK:3?7=0\NGA<5<4?UENF5?5;6^LIO>5:2=WK@D7;394PBKM8=803YIBB1718:R@KPR;8730\NAZT=33:<=WKF__0<?19:R@KPR;9;427]M@UU>27;?<XJE^X1?;>89SGJSS48?556^LOTV?538>3YIDYY2>7?;8TFIR\5;3245_CNWW84?902ZHCXZ31?;8TFIR\58;245_CNWW877912ZHCXZ323<:?UEH]]69?374PBMVP943601[OB[[<37==>VDG\^7>;06;QALQQ:5?730\NAZT=0;:<=WKF__0?718:R@KPR;:730\NAZT=13:<=WKF__0>?19:R@KPR;;;427]M@UU>07;?<XJE^X1=;>89SGJSS4:?556^LOTV?738>3YIDYY2<7?;8TFIR\593245_CNWW86?902ZHCXZ33?;8TFIR\5>;245_CNWW817912ZHCXZ343<:?UEH]]6??374PBMVP923601[OB[[<57==>VDG\^78;0m;QALQQ:3?3:556^LOTV?028?3YIDYY2;>99SGJSS4<437]M@UU>5:==WKF__0:07;QALQQ:?611[OB[[<8<b?UOIWK_XEIVm;QKM[GSTFHGN86^]EF48TVBHFL>0^^ZN4:PPPG2<ZZ^Hm6\\TBCQV\OI<2XXXI:4RRVN=>TT\FZFCIK;;SQWT2=U[]^R\H:4S=2=1>U;994>7^2>1?78W9756<1X0<=15:Q?51823Z6:93;4S=35:0=T48=596]319<6?V:617>0_1?15:Q?65823Z69=3;4S=01:0=T4;9596]325<6?V:5=7?0_1<9>49P8719=2Y7>50:;R>1=;2<[58596]331<4?V:493:596]330<7?V:46=1X090;;R>6:1=T4?4?7^28>59P8=833Z62295\CMP25>UOZLMTIUZ]ABV\JBEb3ZBYIJQBIO]PM_C23ZCEEY64SJKS[UOI>2YDY_MJ4:QPAQ0<[]K_Y^:4SXL@0>R^XLi0Y^K]_WKPMGJB;2\HO45YIDU\P\VB9m1SEAGAX,ZGF%6)9)Y_YO.?.0"BWFON>2RXXAGMb:Z\GJTBW@DMC;5Wdc]J`c=_laU[~dcYesqjkk773QnfS@oeosTfvvohf8:0TicPMhllvScu{`ee?6V|t29Zav2<i5:596o311<6?d:697?0m1?=>49b8459=2k7=90:;`>21;3<i5;=285n<05=1>g;914>7l2>9?68e979=2k7>=0:;`>15;3<i589285n<31=1>g;:=4>7l2=5?78e9416<1j0?915:c?6=823h6953:4a=0=1>g;;94<7l2<1;2=1>g;;84?7l2<>59b81833h6>295n<7<7?d:06=1j050;;`>::1=e494>7o2>0?78f9766<1i0<<15:`?56823k6:83;4b=36:0=e48<596l316<6?g:607?0n1?6>59a84823k69<3;4b=02:0=e4;8596l322<6?g:5<7?0n1<:>49a8709=2h7>:0:;c>1<;3<j582295m<3<6?g:487=0n1=>:1<6?g:497>0n1=14:`?0;2<j5?586l36?68f919<2h743:4b=;=53=eayUo}:7_`fgwpdX{pddo5mlj23456788h0nae?0123454e3kf`<=>?0120f>dkc9:;<=>?4d9`[dbc{|hTz<?P03c8gZgclziS{?>_1.#\ljnfq*HC_K/Gdlfvdrhz);?":?=;b]b`aurjV|:=R>Pxrv7?fYnf<1hSb{{8:ldggsndm80bb:4s=2=1>u;994>7~2>1?78w9756<1x0<=15:q?51823z6:93;4s=35:0=t48=596}319<6?v:617>01?15:q?65823z69=3;4s=01:0=t4;9596}325<6?v:5=7?01<9>49p8719=2y7>50:;r>1=;2<{58596}331<4?v:493:596}330<7?v:46=1x090;;r>6:1=t4?4?7~28>59p8=833z622o5|if23456788h0di?0123454e3zcl<=>?0120f>uno9:;<=>?4c9pmb6789:;<8l4she3456789<i7~gh01234560j2ybk=>?0123<g=tan:;<=>?08`8wla789:;<=om;rkd456789:in6}fg1234567kk1xej>?01234ad<{`m;<=>?01ga?vo`89:;<=>ib:qjc56789::<o5|if23456798h0di?0123444e3zcl<=>?0130f>uno9:;<=>>4c9pmb6789:;=8l4she3456788<i7~gh01234570j2ybk=>?0122<g=tan:;<=>?18`8wla789:;<<om;rkd456789;in6}fg1234566kk1xej>?01235ad<{`m;<=>?00ga?vo`89:;<=?ib:qjc56789:9<o5|if234567:8h0di?0123474e3zcl<=>?0100f>uno9:;<=>=4c9pmb6789:;>8l4she345678;<i7~gh01234540j2ybk=>?0121<g=tan:;<=>?28`8wla789:;<?om;rkd4567898in6}fg1234565kk1xej>?01236ad<{`m;<=>?03ga?vo`89:;<=<ib:qjc56789:8<o5|if234567;8h0di?0123464e3zcl<=>?0110f>uno9:;<=><4c9pmb6789:;?8l4she345678:<i7~gh01234550j2ybk=>?0120<g=tan:;<=>?38`8wla789:;<>om;rkd4567899in6}fg1234564kk1xej>?01237ad<{`m;<=>?02ga?vo`89:;<==ib:qjc56789:?<o5|if234567<8h0di?0123414e3zcl<=>?0160f>uno9:;<=>;4c9pmb6789:;88l4she345678=<i7~gh01234520j2ybk=>?0127<g=tan:;<=>?48`8wla789:;<9om;rkd456789>in6}fg1234563kk1xej>?01230ad<{`m;<=>?05ga?vo`89:;<=:ib:qjc56789:><o5|if234567=8h0di?0123404e3zcl<=>?0170f>uno9:;<=>:4c9pmb6789:;98l4she345678<<i7~gh01234530j2ybk=>?0126<g=tan:;<=>?58`8wla789:;<8om;rkd456789?in6}fg1234562kk1xej>?01231ad<{`m;<=>?04ga?vo`89:;<=;ib:qjc56789:=<o5|if234567>8h0di?0123434e3zcl<=>?0140f>uno9:;<=>94e9pqgruij~d~R}91b58wpdszhicQ|6-a\eabt}kU}=<Q?,za\eZr~xl7: nQn_vkgpm;4:%iTmijPmnff94*dWhceeyQyam?3(fYeWjeeyoat<2/gZdX|pzn1<"l_c]ueisb59:;<=>?0123456789:;<=>?012345678%iTnRyfduj>77*dWkey~byPlnu>4)eXjpzj~Qcov?3(fYdmVe}i|fddq\f|vf{z7: nQle^muawtnllyTnb}=1.`[mgtWks{m~}20-a\lduXkVce1<"l_icp[fYh}}7: nQgar]`a86+kVbjR}lls?3(fYoizUxecg{=1.`[mgtWzynx0>#c^knticjmg~jxdaa=0.`[igsmgir1="l_nww[roc|a78>!mPsbnq[jpbz{coi~Q|sdv>5)eX{`dbxRxnl<2/gZpbzkexeyw20-a\|acqajomm`gcy<qsewrff?w:j6}zbupbgqiuWz<'oRokdrwa[s76W9&pq95y1/220>~eayUjhi}zb^t1[5Y{};j7ulfp^fpt1>XimnxyoQy2^2\|vr602rie}Qksq6;eZquiyzn~Rx=_132?ÆͺµÏ´ÜÀɰȼ¾Ò»·¿1<ÆÆÁij±Âk;ÐÀ¼ÔɸвÌɱ°´k4ÑýÓȻѳÀÊ·ÉÈsO@q156>FGp;ni6K49:0yP`d<58?0:>k4>325:f3<5;?3>wc<?4;38j7622?1/>=<51gd8yVb?2;:=6<<i:0103<d12;9=585\f48111<72898;4l9:315=d=Tl109994?:0103<d12;9=5o5\f4826a<5ll0:?>96b78173?d3Zn36<<k:3ff>454?0h=6?=99b9g6ad=83;1=v]ka;032?75n3;8?:7m6;002<3<~];m;7>51;3921}Tlh09<;4>2g82761>j?09?;7:;%3ea?`03_8;?7<tu03f>4=r98l1<6s+173957=e:mh1<78=:0856~N6nj1/=kl52e`8^=5=;r31m7m5}%035?4282.h97<kd:&g=?4ck2.:j94>;%3e7?47?2c9><4?:%3`1?4582d:o94?;:k15c<72-;h97<=0:l2g1<632c9=i4?:%3`1?4582d:o94=;:k15f<72-;h97<=0:l2g1<432c9=o4?:%3`1?4582d:o94;;:k15d<72-;h97<=0:l2g1<232c9=44?:%3`1?4582d:o949;:k15=<72-;h97<=0:l2g1<032c9=:4?:%3`1?4582d:o947;:k153<72-;h97<=0:l2g1<>32c9=84?:%3`1?4582d:o94n;:k151<72-;h97<=0:l2g1<e32c9=?4?:%3`1?4582d:o94l;:k154<72-;h97<=0:l2g1<c32c9==4?:%3`1?4582d:o94j;:k14c<72-;h97<=0:l2g1<a32c9<h4?:%3`1?4582d:o94>0:9j65b=83.:o84=219m5f2=9810e?>l:18'5f3=:;:0b<m;:008?l47j3:1(<m::303?k7d<3;876g=0`83>!7d=389<6`>c5820>=n:931<7*>c48165=i9j>1=854i30;>5<#9j?1>?>4n0a7>40<3`89;7>5$0a6>7473g;h87?8;:k163<72-;h97<=0:l2g1<6021b>?;50;&2g0<5:91e=n:51898m743290/=n;52328j4e328k07d<=3;29 4e22;8;7c?l4;3a?>o5:;0;6)?l5;014>h6k=0:o65f20g94?"6k<09>=5a1b695a=<a;;86=4+1b79676<f8i?6<k4;h03<?6=,8i>6?<?;o3`0?7a32c98?4?:%3`1?4392d:o94?;:k105<72-;h97<;1:l2g1<632c9?h4?:%3`1?4392d:o94=;:k17a<72-;h97<;1:l2g1<432c9?n4?:%3`1?4392d:o94;;:k17g<72-;h97<;1:l2g1<232c9?l4?:%3`1?4392d:o949;:k17<<72-;h97<;1:l2g1<032c9?54?:%3`1?4392d:o947;:k172<72-;h97<;1:l2g1<>32c9?;4?:%3`1?4392d:o94n;:k170<72-;h97<;1:l2g1<e32c9?>4?:%3`1?4392d:o94l;:k177<72-;h97<;1:l2g1<c32c9?<4?:%3`1?4392d:o94j;:k175<72-;h97<;1:l2g1<a32c9>k4?:%3`1?4392d:o94>0:9j67c=83.:o84=409m5f2=9810e?<k:18'5f3=:=;0b<m;:008?l45k3:1(<m::362?k7d<3;876g=2c83>!7d=38?=6`>c5820>=n:;k1<7*>c48104=i9j>1=854i36:>5<#9j?1>9?4n0a7>40<3`8?47>5$0a6>7263g;h87?8;:k102<72-;h97<;1:l2g1<6021b>9850;&2g0<5<81e=n:51898m722290/=n;52538j4e328k07d<;4;29 4e22;>:7c?l4;3a?>o5<:0;6)?l5;075>h6k=0:o65f22d94?"6k<098<5a1b695a=<a;9?6=4+1b79617<f8i?6<k4;h01=?6=,8i>6?:>;o3`0?7a32c99?4?::m12c<72-;h97<9e:l2g1<732e9:i4?:%3`1?41m2d:o94>;:m12g<72-;h97<9e:l2g1<532e9:l4?:%3`1?41m2d:o94<;:m12<<72-;h97<9e:l2g1<332e9:54?:%3`1?41m2d:o94:;:m122<72-;h97<9e:l2g1<132e9:;4?:%3`1?41m2d:o948;:m120<72-;h97<9e:l2g1<?32e9:94?:%3`1?41m2d:o946;:m126<72-;h97<9e:l2g1<f32e9:?4?:%3`1?41m2d:o94m;:m125<72-;h97<9e:l2g1<d32e99k4?:%3`1?41m2d:o94k;:m11`<72-;h97<9e:l2g1<b32e99i4?:%3`1?41m2d:o94i;:m11f<72-;h97<9e:l2g1<6821d>8l50;&2g0<5>l1e=n:51098k73f290/=n;527g8j4e328807b<:9;29 4e22;<n7c?l4;30?>i5=10;6)?l5;05a>h6k=0:865`24594?"6k<09:h5a1b6950=<g;==6=4+1b7963c<f8i?6<84;n041?6=,8i>6?8j;o3`0?7032e9;94?:%3`1?41m2d:o94>8:9l625=83.:o84=6d9m5f2=9010c?9=:18'5f3=:?o0b<m;:0c8?j4093:1(<m::34f?k7d<3;i76a=7183>!7d=38=i6`>c582g>=h:?i1<7*>c4812`=i9j>1=i54o342>5<#9j?1>;k4n0a7>4c<3f8>:7>5$0a6>70b3g;h87?i;:m116<722h98o4?:7;97?03sA;mo6*>fc8114=]0:08w:47:c8~ 7c32;o87)<j5;0f6>o483:1(<m::3d8j4e32910e?k50;&2g0<5n2d:o94>;:k1g?6=,8i>6?h4n0a7>7=<a;h1<7*>c481b>h6k=0876g=a;29 4e22;l0b<m;:598m7?=83.:o84=f:l2g1<232c947>5$0a6>7`<f8i?6;54i3594?"6k<09j6`>c584?>o5>3:1(<m::3d8j4e32110e?;50;&2g0<5n2d:o946;:k10?6=,8i>6?h4n0a7>d=<a;91<7*>c481b>h6k=0i76g=1;29 4e22;l0b<m;:b98m76=83.:o84=f:l2g1<c32c:j7>5$0a6>7`<f8i?6h54i0f94?"6k<09j6`>c58e?>o6k3:1(<m::3d8j4e328:07d?m:18'5f3=:o1e=n:51098m4g=83.:o84=f:l2g1<6:21b=44?:%3`1?4a3g;h87?<;:k2<?6=,8i>6?h4n0a7>42<3`;<6=4+1b796c=i9j>1=854i2594?"6k<09j6`>c5822>=n;?0;6)?l5;0e?k7d<3;<76g<5;29 4e22;l0b<m;:0:8?l53290/=n;52g9m5f2=9010e>=50;&2g0<5n2d:o94>a:9j77<72-;h97<i;o3`0?7e32c8=7>5$0a6>7`<f8i?6<m4;h0g>5<#9j?1>k5a1b695a=<a;81<7*>c481b>h6k=0:i65f1783>!7d=38m7c?l4;3e?>o2=3:1(<m::468j4e32910e8=50;&2g0<2<2d:o94>;:k65?6=,8i>68:4n0a7>7=<a<:1<7*>c4860>h6k=0876g;f;29 4e22<>0b<m;:598m1c=83.:o84:4:l2g1<232c?h7>5$0a6>02<f8i?6;54i5a94?"6k<0>86`>c584?>o3j3:1(<m::468j4e32110e9o50;&2g0<2<2d:o946;:k7=?6=,8i>68:4n0a7>d=<a=21<7*>c4860>h6k=0i76g;6;29 4e22<>0b<m;:b98m13=83.:o84:4:l2g1<c32c?87>5$0a6>02<f8i?6h54i5094?"6k<0>86`>c58e?>o393:1(<m::468j4e328:07d:?:18'5f3===1e=n:51098m6`=83.:o84:4:l2g1<6:21b?h4?:%3`1?333g;h87?<;:k0`?6=,8i>68:4n0a7>42<3`9h6=4+1b7911=i9j>1=854i4a94?"6k<0>86`>c5822>=n=k0;6)?l5;77?k7d<3;<76g:a;29 4e22<>0b<m;:0:8?l3>290/=n;5559m5f2=9010e8650;&2g0<2<2d:o94>a:9j12<72-;h97;;;o3`0?7e32c>:7>5$0a6>02<f8i?6<m4;h71>5<#9j?1995a1b695a=<a==1<7*>c4860>h6k=0:i65f3c83>!7d=3??7c?l4;3e?>od>3:17d=7:188mae=831bnn4?::k;0?6=3`;m>7>5;h3e<?6=3`;m97>5;n3fe?6=,8i>6<k6;o3`0?6<3f;n47>5$0a6>4c>3g;h87?4;n3f2?6=,8i>6<k6;o3`0?4<3f;n97>5$0a6>4c>3g;h87=4;n3f0?6=,8i>6<k6;o3`0?2<3f;n?7>5$0a6>4c>3g;h87;4;n3f6?6=,8i>6<k6;o3`0?0<3f;n=7>5$0a6>4c>3g;h8794;n3f4?6=,8i>6<k6;o3`0?><3f;oj7>5$0a6>4c>3g;h8774;n3ga?6=,8i>6<k6;o3`0?g<3f;oh7>5$0a6>4c>3g;h87l4;n3gf?6=,8i>6<k6;o3`0?e<3f;om7>5$0a6>4c>3g;h87j4;n3g=?6=,8i>6<k6;o3`0?c<3f;o47>5$0a6>4c>3g;h87h4;n3g3?6=,8i>6<k6;o3`0?7732e:h;4?:%3`1?7b12d:o94>1:9l5a3=83.:o84>e89m5f2=9;10c<j;:18'5f3=9l30b<m;:018?j7c;3:1(<m::0g:?k7d<3;?76a>d383>!7d=3;n56`>c5821>=h9o;1<7*>c482a<=i9j>1=;54o0d3>5<#9j?1=h74n0a7>41<3f;nj7>5$0a6>4c>3g;h87?7;:m2a`<72-;h97?j9:l2g1<6121d=hj50;&2g0<6m01e=n:51`98k4cd290/=n;51d;8j4e328h07b?jb;29 4e228o27c?l4;3`?>i6m>0;6)?l5;3f=>h6k=0:h65`1ea94?"6k<0:i45a1b695`=<g8n:6=4+1b795`?<f8i?6<h4;nfg>5<<j;>h6=4>:183!7aj3;mh6F=019K5ce<g88n6=44}c07`?6=93:1<v*>fc8e0>N5891C=km4og194?=zj;>n6=4>5`83>5}#9oh1j?5G2128L4`d3S286ou>3;4954<a2=086h4>0;796?b=u-;9o7<:5:l20?6<f8?1<6`<9;28j6g=82di;7>4$c:9577<fmh1<6`i1;28j47c291e=?l50:l2g3<73-;o<7?ia:laf?6<aj:1<75f1bc94?=n9jh1<75fc083>>o6kj0;66gl3;29?lda2900coo50;9j5fc=831b=nj50;9jg3<722c:o44?::k`6?6=3`hn6=44ic494?=nk=0;66gmd;29?jd>2900e<m7:188m4ea2900e9:50;&2g0<3;2d:o94?;:k76?6=,8i>69=4n0a7>4=<a=;1<7*>c4877>h6k=0976g;0;29 4e22=90b<m;:298m6`=83.:o84;3:l2g1<332c8i7>5$0a6>15<f8i?6854i2f94?"6k<0??6`>c585?>o4k3:1(<m::518j4e32>10e8m50;&2g0<3;2d:o947;:k6f?6=,8i>69=4n0a7><=<a<k1<7*>c4877>h6k=0j76g:9;29 4e22=90b<m;:c98m0>=83.:o84;3:l2g1<d32c>;7>5$0a6>15<f8i?6i54i4494?"6k<0??6`>c58f?>o2:3:1(<m::518j4e32o10e9950;&2g0<3;2d:o94>0:9j7g<72-;h97:<;o3`0?7632e<57>5$0a6>2><f8i?6=54o6594?"6k<0<46`>c582?>i0>3:1(<m::6:8j4e32;10c:;50;&2g0<002d:o94<;:m40?6=,8i>6:64n0a7>1=<g>91<7*>c484<>h6k=0>76a82;29 4e22>20b<m;:798k27=83.:o8488:l2g1<032e3>7>5$0a6>2><f8i?6554o9394?"6k<0<46`>c58:?>i?83:1(<m::6:8j4e32h10c:h50;&2g0<002d:o94m;:m4a?6=,8i>6:64n0a7>f=<g>n1<7*>c484<>h6k=0o76a8c;29 4e22>20b<m;:d98k2d=83.:o8488:l2g1<a32e<m7>5$0a6>2><f8i?6<>4;n53>5<#9j?1;55a1b6954=<a82h6=4+1b795=d<f8i?6=54i0:b>5<#9j?1=5l4n0a7>4=<a8226=4+1b795=d<f8i?6?54i0:;>5<#9j?1=5l4n0a7>6=<a82<6=4+1b795=d<f8i?6954i0:5>5<#9j?1=5l4n0a7>0=<a82>6=4+1b795=d<f8i?6;54i0:7>5<#9j?1=5l4n0a7>2=<a8296=4+1b795=d<f8i?6554i0:2>5<#9j?1=5l4n0a7><=<a82;6=4+1b795=d<f8i?6l54i05e>5<#9j?1=5l4n0a7>g=<a8=n6=4+1b795=d<f8i?6n54i05g>5<#9j?1=5l4n0a7>a=<a8=h6=4+1b795=d<f8i?6h54i05a>5<#9j?1=5l4n0a7>c=<a8=j6=4+1b795=d<f8i?6<>4;h34=?6=,8i>6<6m;o3`0?7632c:;:4?:%3`1?7?j2d:o94>2:9j520=83.:o84>8c9m5f2=9:10e<9::18'5f3=91h0b<m;:068?l70<3:1(<m::0:a?k7d<3;>76g>7283>!7d=3;3n6`>c5822>=n9>81<7*>c482<g=i9j>1=:54i052>5<#9j?1=5l4n0a7>4><3`;<<7>5$0a6>4>e3g;h87?6;:k22c<72-;h97?7b:l2g1<6i21b=;k50;&2g0<60k1e=n:51c98m40d290/=n;519`8j4e328i07d?9b;29 4e2282i7c?l4;3g?>o6>h0;6)?l5;3;f>h6k=0:i65f17;94?"6k<0:4o5a1b695c=<a8<36=4+1b795=d<f8i?6?>4;h353?6=,8i>6<6m;o3`0?4632c::;4?:%3`1?7?j2d:o94=2:9j533=83.:o84>8c9m5f2=::10e<8;:18'5f3=91h0b<m;:368?l71;3:1(<m::0:a?k7d<38>76g>9383>!7d=3;3n6`>c5812>=n90;1<7*>c482<g=i9j>1>:54i0;3>5<#9j?1=5l4n0a7>7><3`;3j7>5$0a6>4>e3g;h87<6;:k2<`<72-;h97?7b:l2g1<5i21b=5j50;&2g0<60k1e=n:52c98m4>4290/=n;519`8j4e32;i07d?88;29 4e2282i7c?l4;0g?>o6>m0;6)?l5;3;f>h6k=09i65f17094?"6k<0:4o5a1b696c=<ahl1<7*>c48ba>h6k=0;76gnd;29 4e22ho0b<m;:098mde=83.:o84ne:l2g1<532cjn7>5$0a6>dc<f8i?6>54i`c94?"6k<0ji6`>c587?>of13:1(<m::`g8j4e32<10el650;&2g0<fm2d:o949;:kb3?6=,8i>6lk4n0a7>2=<ah?1<7*>c48ba>h6k=0376gn4;29 4e22ho0b<m;:898md5=83.:o84ne:l2g1<f32cj>7>5$0a6>dc<f8i?6o54i`394?"6k<0ji6`>c58`?>of83:1(<m::`g8j4e32m10e4h50;&2g0<fm2d:o94j;:k:a?6=,8i>6lk4n0a7>c=<a0n1<7*>c48ba>h6k=0:<65f9b83>!7d=3kn7c?l4;32?>o>i3:1(<m::`g8j4e328807d76:18'5f3=il1e=n:51298m<>=83.:o84ne:l2g1<6<21b5:4?:%3`1?gb3g;h87?:;:k:2?6=,8i>6lk4n0a7>40<3`3>6=4+1b79e`=i9j>1=:54i8694?"6k<0ji6`>c582<>=n1:0;6)?l5;cf?k7d<3;276g62;29 4e22ho0b<m;:0c8?l?6290/=n;5ad9m5f2=9k10e5h50;&2g0<fm2d:o94>c:9j<`<72-;h97oj;o3`0?7c32c3h7>5$0a6>dc<f8i?6<k4;h:`>5<#9j?1mh5a1b695c=<a1h1<7*>c48ba>h6k=09<65f8`83>!7d=3kn7c?l4;02?>o?13:1(<m::`g8j4e32;807d67:18'5f3=il1e=n:52298m=1=83.:o84ne:l2g1<5<21b4;4?:%3`1?gb3g;h87<:;:ka1?6=,8i>6lk4n0a7>70<3`h?6=4+1b79e`=i9j>1>:54ic194?"6k<0ji6`>c581<>=nj;0;6)?l5;cf?k7d<38276gm1;29 4e22ho0b<m;:3c8?ld7290/=n;5ad9m5f2=:k10el850;&2g0<fm2d:o94=c:9j=g<72-;h97oj;o3`0?4c32c2<7>5$0a6>dc<f8i?6?k4;h:6>5<#9j?1mh5a1b696c=<g8?j6=4+1b7950?<f8i?6=54o07;>5<#9j?1=874n0a7>4=<g8?<6=4+1b7950?<f8i?6?54o075>5<#9j?1=874n0a7>6=<g8?>6=4+1b7950?<f8i?6954o077>5<#9j?1=874n0a7>0=<g8?86=4+1b7950?<f8i?6;54o071>5<#9j?1=874n0a7>2=<g8?;6=4+1b7950?<f8i?6554o06e>5<#9j?1=874n0a7><=<g8>n6=4+1b7950?<f8i?6l54o06g>5<#9j?1=874n0a7>g=<g8>h6=4+1b7950?<f8i?6n54o06a>5<#9j?1=874n0a7>a=<g8>j6=4+1b7950?<f8i?6h54o06:>5<#9j?1=874n0a7>c=<g8>36=4+1b7950?<f8i?6<>4;n373?6=,8i>6<;6;o3`0?7632e:884?:%3`1?7212d:o94>2:9l512=83.:o84>589m5f2=9:10c<:<:18'5f3=9<30b<m;:068?j73:3:1(<m::07:?k7d<3;>76a>4083>!7d=3;>56`>c5822>=h9=:1<7*>c4821<=i9j>1=:54o01e>5<#9j?1=874n0a7>4><3f;8i7>5$0a6>43>3g;h87?6;:m27a<72-;h97?:9:l2g1<6i21d=>m50;&2g0<6=01e=n:51c98k45f290/=n;514;8j4e328i07b?<9;29 4e228?27c?l4;3g?>i6;10;6)?l5;36=>h6k=0:i65`12594?"6k<0:945a1b695c=<g89=6=4+1b7950?<f8i?6?>4;n301?6=,8i>6<;6;o3`0?4632e:?94?:%3`1?7212d:o94=2:9l565=83.:o84>589m5f2=::10c<==:18'5f3=9<30b<m;:368?j7493:1(<m::07:?k7d<38>76a>6183>!7d=3;>56`>c5812>=h9<l1<7*>c4821<=i9j>1>:54o07f>5<#9j?1=874n0a7>7><3f;>h7>5$0a6>43>3g;h87<6;:m21f<72-;h97?:9:l2g1<5i21d=8l50;&2g0<6=01e=n:52c98k436290/=n;514;8j4e32;i07b?;6;29 4e228?27c?l4;0g?>i6;k0;6)?l5;36=>h6k=09i65`12294?"6k<0:945a1b696c=<a88j6=4+1b7957?<f8i?6=54i00;>5<#9j?1=?74n0a7>4=<a88<6=4+1b7957?<f8i?6?54i005>5<#9j?1=?74n0a7>6=<a88>6=4+1b7957?<f8i?6954i007>5<#9j?1=?74n0a7>0=<a8886=4+1b7957?<f8i?6;54i001>5<#9j?1=?74n0a7>2=<al=1<7*>c48f2>h6k=0;76gj5;29 4e22l<0b<m;:098m`2=83.:o84j6:l2g1<532cn?7>5$0a6>`0<f8i?6>54id094?"6k<0n:6`>c587?>ob93:1(<m::d48j4e32<10eh>50;&2g0<b>2d:o949;:kgb?6=,8i>6h84n0a7>2=<ao:1<7*>c48f2>h6k=0376gjf;29 4e22l<0b<m;:898m`c=83.:o84j6:l2g1<f32cnh7>5$0a6>`0<f8i?6o54ida94?"6k<0n:6`>c58`?>obj3:1(<m::d48j4e32m10eho50;&2g0<b>2d:o94j;:kf=?6=,8i>6h84n0a7>c=<al21<7*>c48f2>h6k=0:<65fdd83>!7d=3o=7c?l4;32?>i6jm0;6)?l5;3ag>h6k=0;76a>bc83>!7d=3;io6`>c582?>i6jh0;6)?l5;3ag>h6k=0976a>b883>!7d=3;io6`>c580?>i6j10;6)?l5;3ag>h6k=0?76a>b683>!7d=3;io6`>c586?>i6j?0;6)?l5;3ag>h6k=0=76a>b483>!7d=3;io6`>c584?>i6j:0;6)?l5;3ag>h6k=0376a>b383>!7d=3;io6`>c58:?>i6j80;6)?l5;3ag>h6k=0j76a>b183>!7d=3;io6`>c58a?>i6io0;6)?l5;3ag>h6k=0h76a>ad83>!7d=3;io6`>c58g?>i6im0;6)?l5;3ag>h6k=0n76a>ab83>!7d=3;io6`>c58e?>i6ik0;6)?l5;3ag>h6k=0:<65`1`c94?"6k<0:nn5a1b6954=<g8k36=4+1b795ge<f8i?6<<4;n3b3?6=,8i>6<ll;o3`0?7432e:m;4?:%3`1?7ek2d:o94>4:9l5d3=83.:o84>bb9m5f2=9<10c<o;:18'5f3=9ki0b<m;:048?j7f;3:1(<m::0``?k7d<3;<76a>a383>!7d=3;io6`>c582<>=h9h;1<7*>c482ff=i9j>1=454o0c3>5<#9j?1=om4n0a7>4g<3f;2j7>5$0a6>4dd3g;h87?m;:m2=a<72-;h97?mc:l2g1<6k21d=4m50;&2g0<6jj1e=n:51e98k4?e290/=n;51ca8j4e328o07b?6a;29 4e228hh7c?l4;3e?>i6100;6)?l5;3ag>h6k=09<65`18:94?"6k<0:nn5a1b6964=<g83<6=4+1b795ge<f8i?6?<4;n3:2?6=,8i>6<ll;o3`0?4432e:584?:%3`1?7ek2d:o94=4:9l5<2=83.:o84>bb9m5f2=:<10c<m<:18'5f3=9ki0b<m;:348?j7d:3:1(<m::0``?k7d<38<76a>c083>!7d=3;io6`>c581<>=h9j:1<7*>c482ff=i9j>1>454o0`e>5<#9j?1=om4n0a7>7g<3f;ii7>5$0a6>4dd3g;h87<m;:m2f1<72-;h97?mc:l2g1<5k21d=l750;&2g0<6jj1e=n:52e98k4?b290/=n;51ca8j4e32;o07b?63;29 4e228hh7c?l4;0e?>o6n3:1(<m::0g8j4e32910e<j50;&2g0<6m2d:o94>;:k2g?6=,8i>6<k4n0a7>7=<a8h1<7*>c482a>h6k=0876g>a;29 4e228o0b<m;:598m4?=83.:o84>e:l2g1<232c:47>5$0a6>4c<f8i?6;54i0594?"6k<0:i6`>c584?>o4?3:1(<m::0g8j4e32110e>850;&2g0<6m2d:o946;:k01?6=,8i>6<k4n0a7>d=<a:>1<7*>c482a>h6k=0i76g<3;29 4e228o0b<m;:b98m64=83.:o84>e:l2g1<c32c8=7>5$0a6>4c<f8i?6h54i3f94?"6k<0:i6`>c58e?>o5:3:1(<m::0g8j4e328:07d?9:18'5f3=9l1e=n:51098k472290/=n;51068j4e32910c<?<:18'5f3=98>0b<m;:098k475290/=n;51068j4e32;10c<?>:18'5f3=98>0b<m;:298k477290/=n;51068j4e32=10c<>i:18'5f3=98>0b<m;:498k46c290/=n;51068j4e32?10c<>l:18'5f3=98>0b<m;:698k46e290/=n;51068j4e32110c<>n:18'5f3=98>0b<m;:898k46>290/=n;51068j4e32h10c<>7:18'5f3=98>0b<m;:c98k460290/=n;51068j4e32j10c<>9:18'5f3=98>0b<m;:e98k462290/=n;51068j4e32l10c<>;:18'5f3=98>0b<m;:g98k465290/=n;51068j4e328:07b??1;29 4e228;?7c?l4;32?>i6890;6)?l5;320>h6k=0:>65`fg83>!7d=3;:86`>c5827>=hnl0;6)?l5;320>h6k=0:865`fe83>!7d=3;:86`>c5821>=hnj0;6)?l5;320>h6k=0::65`fc83>!7d=3;:86`>c5823>=hnh0;6)?l5;320>h6k=0:465`f883>!7d=3;:86`>c582=>=h98i1<7*>c48251=i9j>1=l54o03a>5<#9j?1=<:4n0a7>4d<3f;:m7>5$0a6>4733g;h87?l;:m25<<72-;h97?>4:l2g1<6l21d=<650;&2g0<69=1e=n:51d98k470290/=n;51068j4e328l07b?>6;29 4e228;?7c?l4;03?>i68l0;6)?l5;320>h6k=09=65`11194?"6k<0:=95a1b6967=<go21<7*>c48251=i9j>1>>54i7494?"6k<0=96`>c583?M7a>21b:94?:%3`1?023g;h87?4H0d5?>o1;3:1(<m::778j4e32;1C=k84;h41>5<#9j?1:85a1b697>N6n?10e;?50;&2g0<1=2d:o94;;I3e2>=n>90;6)?l5;46?k7d<3?0D<h9;:k6b?6=,8i>6;;4n0a7>3=O9o<07d;j:18'5f3=><1e=n:57:J2b3=<a?l1<7*>c4851>h6k=037E?i6:9j2`<72-;h978:;o3`0??<@8l=76g9d;29 4e22??0b<m;:`9K5c0<3`<h6=4+1b7920=i9j>1n6F>f798m3d=83.:o8495:l2g1<d3A;m:65f6`83>!7d=3<>7c?l4;f8L4`132c=57>5$0a6>33<f8i?6h5G1g48?l0?290/=n;5649m5f2=n2B:j;54i7594?"6k<0=96`>c5824>N6n?10e8j50;&2g0<1=2d:o94>1:J2b3=<uz8<;7>52z\04>;5<l02h6s|26:94?4|V;o01?:j:8a8yv4013:1>vP=c:?10`<>i2wx>:o50;0xZ7d<5;>n6474}r04f?6=:rT9m63=4d8:<>{t:>i1<7<t^3;8972b20=0q~<8d;296~X502798h466:p62c=838pR?94=36f><3<uz8<j7>52z\12>;5<l0286s|29294?4|V;?01?:j:818yv4?93:1>vP=4:?10`<>:2wx>5<50;0xZ75<5;>n64?4}r0;7?6=:rT9=63=4d8;b>{t:1>1<7<t^328972b21o0q~<75;296~X6n2798h47d:p6=0=838pR<j4=36f>=e<uz83;7>52z\2g>;5<l03n6s|29:94?4|V8h01?:j:9c8yv4?13:1>vP>a:?10`<?12wx>5o50;0xZ4?<5;>n6564}r0;f?6=:rT:463=4d8;3>{t:1i1<7<t^058972b21<0q~<7d;296~X4?2798h4m5:p6=c=838pR>84=36f>g2<uz83j7>52z\01>;5<l0i?6s|28294?4|V:>01?:j:c08yv4>93:1>vP<3:?10`<e92wx>4<50;0xZ64<5;>n6o>4}r0:7?6=:rT8=63=4d8b2>{t:0>1<7<t^3f8972b20h0q~<65;296~X5:2798h460:p6<0=838pR<84=36f>=3<uz82;7>52z\61>;5<l0:m6s|28:94?4|V<901?:j:0;8yv4>13:1>vP:1:?10`<602wx>4o50;0xZ06<5;>n6<94}r0:f?6=:rT?j63=4d803>{t:0i1<7<t^5g8972b2:<0q~<6d;296~X3l2798h4<5:p6<c=838pR9m4=36f>62<uz82j7>52z\7f>;5<l08?6s|2`294?4|V=k01?:j:208yv4f93:1>vP;9:?10`<492wx>l<50;0xZ1><5;>n6?j4}r0b7?6=:rT?:63=4d816>{t:h>1<7<t^578972b28<0q~<n5;296~X3<2798h4;4:p6d0=838pR9<4=36f>14<uz8j;7>52z\75>;5<l0?=6s|2`:94?4|V=:01?:j:528yv4f13:1>vP<f:?10`<4n2wx>lo50;0xZ6c<5;>n6>k4}r0bf?6=:rT8h63=4d80`>{t:hi1<7<t^2a8972b2:i0q~<nd;296~X2k2798h4:c:p6dc=838pR8l4=36f>0d<uz8jj7>52z\6e>;5<l0>m6s|2c294?4|V<301?:j:4;8yv4e93:1>vP:8:?10`<202wx>o<50;0xZ01<5;>n6894}r0a7?6=:rT>:63=4d862>{t:k>1<7<t^408972b2<80q~<m5;296~X3?2798h4;7:p6g0=838pR>l4=36f>6d<uz8i;7>52z\gg>;5<l0:>:5rs3`;>5<5sW;nm63=4d820==z{;h26=4={_3f<>;5<l0:8:5rs3`b>5<5sW;n:63=4d8200=z{;hi6=4={_3f1>;5<l0:895rs3``>5<5sW;n863=4d8206=z{;ho6=4={_3f7>;5<l0:8?5rs3`f>5<5sW;n>63=4d8204=z{;hm6=4={_3f5>;5<l0:8=5rs3a3>5<5sW;n<63=4d827c=z{;i:6=4={_3gb>;5<l0:?h5rs3a1>5<5sW;oi63=4d827a=z{;i86=4={_3g`>;5<l0:?n5rs3a7>5<5sW;on63=4d827d=z{;i>6=4={_3ge>;5<l0:?45rs3a5>5<5sW;o563=4d827==z{;i<6=4={_3g<>;5<l0:?:5rs3a;>5<5sW;o;63=4d8273=z{;i26=4={_3g2>;5<l0:?85rs3ab>5<5sW;o963=4d8271=z{;ii6=4={_3g0>;5<l0:?>5rs3a`>5<5sW;o?63=4d8277=z{;io6=4={_3g6>;5<l0:?<5rs3af>5<5sW;m=63=4d8225=z{;im6=4={_3e4>;5<l0:9k5rs3f3>5<5sW;nj63=4d821`=z{;n:6=4={_3fa>;5<l0:9i5rs3f1>5<5sW;nh63=4d821f=z{;n86=4={_3fg>;5<l0:9o5rs3f7>5<5sW;nn63=4d8214=z{;n>6=4={_3f3>;5<l0:8;5rs3f5>5<5sW;oo63=4d827g=z{;n<6=4={_3g5>;5<l0:?=5rs3f;>5<5sWno70<;e;37=>{t:m31<78t=36`>44b348?i7?=2:?10`<6::16>9k513c8972b288?70<;e;311>{t:mk1<78m{<07`?`4348?i7?=6:?10`<6:116>9k5dd9>61c=m116>9k5e89>61c=mh16>9k5ec9>61c=mj16>9k5ee9>61c=ml16>9k5eg9>61c=n916>9k5dg9>61c=m916>9k5e09>61c=m;16>9k5e29>61c=m=16>9k5e49>61c=m>16>9k59d9>61c=1o16>9k5a19>61c=i816>9k5a39>61c=i:16>9k5a59>61c=i<16>9k5a69>61c=i116>9k5a89>61c=ih16>9k5ac9>61c=ij16>9k5ae9>61c=io16>9k51c9>61c=9j16>9k51e9>61c=9o16>9k5b79>61c=jm16>9k5bd9>61c=jo16>9k5c19>61c=k816>9k5c39>61c=k:16>9k5c59>61c=k?16>9k51708972b28<o70<;e;34<>;5<l0:4>5225g95=b<5;>n6<6j;<07a?7?n2798h4>919>61c=90;01?:j:0;1?843m3;=?63=4d8221=::=o1=;;4=36f>401348?i7?97:?10`<6>116>9k517;8972b28<j70<;e;35f>;5<l0::n5225g953c<5;>n6<8i;<07a?7082798h4>709>61c=9>801?:j:050?843m3;<863=4d8230=::=o1=:84=36f>410348?i7?89:?10`<6?h16>9k516`8972b28=h70<;e;34`>;5<l0:;h5225g952`<5;>n6<6?;<07a?7?92798h4>839>61c=91>01?:j:0:6?843m3;3:63=4d82<2=::=o1=564=36f>4>>348?i7?7a:?10`<60j16>9k51b:8972b28i270<;e;3`e>;5<l0:oo5225g95fe<5;>n6<mk;<07a?7dm2798h4>cg9~yv4593:1>vP=209>61d=;91v??i:181[46n2798o4=e:p64b=838pR??k;<07f?4d3ty9=n4?:3y]64e<5;>i6?l4}r02f?6=:rT9=o5225`96d=z{;;j6=4={_02e>;5<k0956s|20;94?4|V;;270<;b;0;?xu5910;6?uQ20:8972e2;=0q~<>7;296~X59>16>9l5279~w7712909wS<>6:?10g<5=2wx><;50;0xZ772348?n7<;;|q151<72;qU><:4=36a>75<uz8:>7>52z\157=::=h1><5rs332>5<5sW8:=63=4c814>{t:8:1<7<t^333?843j3;m7p}=0g83>7}Y:9l01?:m:0f8yv47m3:1>vP=0d9>61d=9j1v?>k:181[47l2798o4>b:p65e=838pR?>l;<07f?7f3ty9<o4?:3y]65d<5;>i6<74}r03e?6=:rT9<l5225`95==z{;:26=4={_03=>;5<k0:;6s|23:94?4|V;8370<;b;14?xu5:>0;6?uQ2358972e2:<0q~<=6;296~X5:?16>9l5349~w7422909wS<=5:?10g<4<2wx>?:50;0xZ743348?n7=<;|q166<72;qU>?=4=36a>64<uz89>7>52z\167=::=h1?<5rs33f>5<5sW8:i63=4c81`>{t:891<7<t^330?843j3897p}=0983>7}Y:9201?:m:048yv43:3:1>vP=439>61d==<1v?:?:181[4382798o4:3:p66c=838pR?=j;<07f?363ty9?i4?:3y]66b<5;>i68>4}r00g?6=:rT9?n5225`90c=z{;9i6=4={_00f>;5<k0?i6s|22c94?4|V;9j70<;b;6g?xu5;00;6?uQ22;8972e2=i0q~<<8;296~X5;116>9l54c9~w7502909wS<<7:?10g<3i2wx>>850;0xZ751348?n7:6;|q170<72;qU>>;4=36a>1><uz88?7>52z\176=::=h18;5rs311>5<5sW88>63=4c871>{t::;1<7<t^312?843j3>?7p}=3183>7}Y:::01?:m:508yv45n3:1>vP=2g9>61d=<81v?<j:181[45m2798o4;0:p67b=838pR?<k;<07f?5a3ty9>n4?:3y]67e<5;>i6>k4}r01f?6=:rT9>o5225`97a=z{;8j6=4={_01e>;5<k08o6s|25;94?4|V;>270<;b;7`?xu5<10;6?uQ25:8972e2<h0q~<;7;296~X5<>16>9l55`9~w7212909wS<;6:?10g<212wx>9;50;0xZ722348?n7;7;|q101<72;qU>9:4=36a>01<uz8??7>52z\106=::=h19;5rs31e>5<5sW88j63=4c866>{t::>1<7<t^317?843j3><7p}=2883>7}Y:;301?:m:2`8yv42:3:1>vP=539>61d=lj1v?8i:181[41n2798o4>e`9~w70c2909wS<9d:?10g<6m11v?8m:181[41j2798o4>e79~w70f2909wS<9a:?10g<6m<1v?86:181[4112798o4>e59~w70?2909wS<98:?10g<6m:1v?88:181[41?2798o4>e39~w7012909wS<96:?10g<6m81v?8::181[41=2798o4>e19~w7032909wS<94:?10g<6lo1v?8<:181[41;2798o4>dd9~w7052909wS<92:?10g<6lm1v?8?:181[4182798o4>dc9~w73a2909wS<:f:?10g<6lh1v?;j:181[42m2798o4>d89~w73c2909wS<:d:?10g<6l11v?;l:181[42k2798o4>d69~w73e2909wS<:b:?10g<6l?1v?;n:181[42i2798o4>d49~w73>2909wS<:9:?10g<6l=1v?;7:181[4202798o4>d29~w7302909wS<:7:?10g<6l;1v?99:181[40>2798o4>f09~w7122909wS<85:?10g<6n91v?9;:181[40<2798o4>eg9~w7142909wS<83:?10g<6ml1v?9=:181[40:2798o4>ee9~w7162909wS<81:?10g<6mj1v?9?:181[4082798o4>ec9~w70d2909wS<9c:?10g<6m>1v?8>:181[4192798o4>db9~w7312909wS<:6:?10g<6l81v?;<:181[42;2798o4kd:~j7?d2909wE?ic:m6<b=838pD<hl;|l1=`<72;qC=km4}o0:b?6=:rB:jn5rn3c3>5<5sA;mo6sa2`394?4|@8lh7p`=a383>7}O9oi0qc<n3;296~N6nj1vb?o;:181M7ak2we>l;50;0xL4`d3td9m;4?:3yK5ce<ug8j;7>52zJ2bf=zf;k36=4={I3eg>{i:h31<7<tH0d`?xh5ih0;6?uG1ga8yk4fj3:1>vF>fb9~j7gd2909wE?ic:m6db=838pD<hl;|l1e`<72;qC=km4}o0bb?6=:rB:jn5rn3`3>5<5sA;mo6sa2c394?4|@8lh7p`=b383>7}O9oi0qc<m3;296~N6nj1vb?l;:181M7ak2we>o;50;0xL4`d3td9n;4?:3yK5ce<ug8i;7>52zJ2bf=zf;h36=4={I3eg>{i:k31<7<tH0d`?xh5jh0;6?uG1ga8yk4ej3:1>vF>fb9~j7dd2909wE?ic:m6gb=838pD<hl;|l1f`<72;qC=km4}o0ab?6=:rB:jn5rn3a3>5<5sA;mo6sa2b394?4|@8lh7p`=c383>7}O9oi0qc<l3;296~N6nj1vb?m;:181M7ak2we>n;50;0xL4`d3td9o;4?:3yK5ce<ug8h;7>52zJ2bf=zf;i36=4={I3eg>{i:j31<7<tH0d`?xh5kh0;6?uG1ga8yk4dj3:1>vF>fb9~j7ed2909wE?ic:m6fb=838pD<hl;|l1g`<72;qC=km4}o0`b?6=:rB:jn5rn3f3>5<5sA;mo6sa2e394?4|@8lh7p`=d383>7}O9oi0qc<k3;296~N6nj1vb?j;:181M7ak2we>i;50;0xL4`d3td9h;4?:3yK5ce<ug8o;7>52zJ2bf=zf;n36=4={I3eg>{i:m31<7<tH0d`?xh5lh0;6?uG1ga8yk4cj3:1>vF>fb9~j7bd2909wE?ic:m6ab=838pD<hl;|l1``<72;qC=km4}o0gb?6=:rB:jn5rn3g3>5<5sA;mo6sa2d394?4|@8lh7p`=e383>7}O9oi0qc<j3;296~N6nj1vb?k;:181M7ak2we>h;50;0xL4`d3td9i;4?:3yK5ce<ug8n;7>52zJ2bf=zf;o36=4={I3eg>{i:l31<7<tH0d`?xh5mh0;6?uG1ga8yk4bj3:1>vF>fb9~j7cd2909wE?ic:m6`b=838pD<hl;|l1a`<72;qC=km4}o0fb?6=:rB:jn5rn3d3>5<5sA;mo6sa2g394?4|@8lh7p`=f383>7}O9oi0qc<i3;296~N6nj1vb?h;:181M7ak2we>k;50;0xL4`d3td9j;4?:3yK5ce<ug8m;7>52zJ2bf=zf;l36=4={I3eg>{i:o31<7<tH0d`?xh5nh0;6?uG1ga8yk4aj3:1>vF>fb9~j7`d2909wE?ic:m6cb=838pD<hl;|l1=d<728qC=km4}o0:f?6=9rB:jn5r}|CDF}4>;0?4;8m5dc~DED|8tJK\vsO@
\ No newline at end of file diff --git a/src/rtl/ipcore/subtractor_s6.sym b/src/rtl/ipcore/subtractor_s6.sym new file mode 100644 index 0000000..23973dc --- /dev/null +++ b/src/rtl/ipcore/subtractor_s6.sym @@ -0,0 +1,24 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="subtractor_s6">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2015-7-10T14:50:53</timestamp>
+ <pin polarity="Input" x="0" y="80" name="a[31:0]" />
+ <pin polarity="Input" x="0" y="112" name="b[31:0]" />
+ <pin polarity="Input" x="0" y="208" name="c_in" />
+ <pin polarity="Output" x="288" y="80" name="c_out" />
+ <pin polarity="Output" x="288" y="112" name="s[31:0]" />
+ <graph>
+ <text style="fontsize:40;fontname:Arial" x="32" y="32">subtractor_s6</text>
+ <rect width="224" x="32" y="32" height="384" />
+ <line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin a[31:0]" />
+ <line x2="32" y1="112" y2="112" style="linewidth:W" x1="0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin b[31:0]" />
+ <line x2="32" y1="208" y2="208" x1="0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="208" type="pin c_in" />
+ <line x2="256" y1="80" y2="80" x1="288" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="252" y="80" type="pin c_out" />
+ <line x2="256" y1="112" y2="112" style="linewidth:W" x1="288" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="252" y="112" type="pin s[31:0]" />
+ </graph>
+</symbol>
diff --git a/src/rtl/ipcore/subtractor_s6.v b/src/rtl/ipcore/subtractor_s6.v new file mode 100644 index 0000000..f86097d --- /dev/null +++ b/src/rtl/ipcore/subtractor_s6.v @@ -0,0 +1,364 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: P.20131013 +// \ \ Application: netgen +// / / Filename: subtractor_s6.v +// /___/ /\ Timestamp: Fri Jul 10 17:50:53 2015 +// \ \ / \ +// \___\/\___\ +// +// Command : -w -sim -ofmt verilog E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/subtractor_s6.ngc E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/subtractor_s6.v +// Device : 6slx45csg324-3 +// Input file : E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/subtractor_s6.ngc +// Output file : E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/subtractor_s6.v +// # of Modules : 1 +// Design Name : subtractor_s6 +// Xilinx : e:\Xilinx\14.7\ISE_DS\ISE\ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module subtractor_s6 ( + c_in, c_out, a, b, s +)/* synthesis syn_black_box syn_noprune=1 */; + input c_in; + output c_out; + input [31 : 0] a; + input [31 : 0] b; + output [31 : 0] s; + + // synthesis translate_off + + wire \blk00000001/sig00000064 ; + wire \blk00000001/sig00000063 ; + wire \NLW_blk00000001/blk00000004_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<47>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<46>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<45>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<44>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<43>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<42>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<41>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<40>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<39>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<38>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<37>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<36>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<35>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_P<33>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<35>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<34>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<33>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<32>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<31>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<30>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<29>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<28>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<27>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<26>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<25>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<24>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<23>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<22>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<21>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<20>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<19>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<18>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<17>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<16>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<15>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<14>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<13>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<12>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<11>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<10>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<9>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<8>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<7>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<6>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<5>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<4>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<3>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<2>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<1>_UNCONNECTED ; + wire \NLW_blk00000001/blk00000004_M<0>_UNCONNECTED ; + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 0 ), + .B0REG ( 0 ), + .B1REG ( 0 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CREG ( 0 ), + .DREG ( 0 ), + .MREG ( 0 ), + .OPMODEREG ( 0 ), + .PREG ( 0 ), + .RSTTYPE ( "SYNC" ), + .CARRYOUTREG ( 0 )) + \blk00000001/blk00000004 ( + .CECARRYIN(\blk00000001/sig00000064 ), + .RSTC(\blk00000001/sig00000064 ), + .RSTCARRYIN(\blk00000001/sig00000064 ), + .CED(\blk00000001/sig00000064 ), + .RSTD(\blk00000001/sig00000064 ), + .CEOPMODE(\blk00000001/sig00000064 ), + .CEC(\blk00000001/sig00000064 ), + .CARRYOUTF(\NLW_blk00000001/blk00000004_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000001/sig00000064 ), + .RSTM(\blk00000001/sig00000064 ), + .CLK(\blk00000001/sig00000064 ), + .RSTB(\blk00000001/sig00000064 ), + .CEM(\blk00000001/sig00000064 ), + .CEB(\blk00000001/sig00000064 ), + .CARRYIN(\blk00000001/sig00000064 ), + .CEP(\blk00000001/sig00000064 ), + .CEA(\blk00000001/sig00000064 ), + .CARRYOUT(\NLW_blk00000001/blk00000004_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000001/sig00000064 ), + .RSTP(\blk00000001/sig00000064 ), + .B({b[17], b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), + .BCOUT({\NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED , +\NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED , +\NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED , +\NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED , +\NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED , +\NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED , +\NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED , +\NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED , +\NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , +\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , +\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , +\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , +\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , +\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , +\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , +\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , +\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , +\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 }), + .C({\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , +\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , +\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , +\blk00000001/sig00000064 , a[31], a[30], a[29], a[28], a[27], a[26], a[25], a[24], a[23], a[22], a[21], a[20], a[19], a[18], a[17], a[16], a[15], +a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), + .P({\NLW_blk00000001/blk00000004_P<47>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<46>_UNCONNECTED , +\NLW_blk00000001/blk00000004_P<45>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<44>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<43>_UNCONNECTED , +\NLW_blk00000001/blk00000004_P<42>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<41>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<40>_UNCONNECTED , +\NLW_blk00000001/blk00000004_P<39>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<38>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<37>_UNCONNECTED , +\NLW_blk00000001/blk00000004_P<36>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED , +\NLW_blk00000001/blk00000004_P<33>_UNCONNECTED , c_out, s[31], s[30], s[29], s[28], s[27], s[26], s[25], s[24], s[23], s[22], s[21], s[20], s[19], +s[18], s[17], s[16], s[15], s[14], s[13], s[12], s[11], s[10], s[9], s[8], s[7], s[6], s[5], s[4], s[3], s[2], s[1], s[0]}), + .OPMODE({\blk00000001/sig00000063 , \blk00000001/sig00000064 , c_in, \blk00000001/sig00000064 , \blk00000001/sig00000063 , +\blk00000001/sig00000063 , \blk00000001/sig00000063 , \blk00000001/sig00000063 }), + .D({\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , +\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , +\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , +\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 }), + .PCOUT({\NLW_blk00000001/blk00000004_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<46>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<44>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<42>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<40>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<38>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<36>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<34>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<32>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<30>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<28>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<26>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<24>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<22>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<20>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<18>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<16>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<14>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<12>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<10>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<8>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<6>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<4>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<2>_UNCONNECTED , +\NLW_blk00000001/blk00000004_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<0>_UNCONNECTED }), + .A({\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , b[31], b[30], b[29], b[28], b[27] +, b[26], b[25], b[24], b[23], b[22], b[21], b[20], b[19], b[18]}), + .M({\NLW_blk00000001/blk00000004_M<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<34>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<33>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<32>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<31>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<30>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<29>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<28>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<27>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<26>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<25>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<24>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<23>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<22>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<21>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<20>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<19>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<18>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<16>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<14>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<13>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<12>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<10>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<8>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<7>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<6>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<4>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<2>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<1>_UNCONNECTED , +\NLW_blk00000001/blk00000004_M<0>_UNCONNECTED }) + ); + GND \blk00000001/blk00000003 ( + .G(\blk00000001/sig00000064 ) + ); + VCC \blk00000001/blk00000002 ( + .P(\blk00000001/sig00000063 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/src/rtl/ipcore/subtractor_s6.veo b/src/rtl/ipcore/subtractor_s6.veo new file mode 100644 index 0000000..e78cc7a --- /dev/null +++ b/src/rtl/ipcore/subtractor_s6.veo @@ -0,0 +1,71 @@ +/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used solely *
+* for design, simulation, implementation and creation of design files *
+* limited to Xilinx devices or technologies. Use with non-Xilinx *
+* devices or technologies is expressly prohibited and immediately *
+* terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
+* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
+* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
+* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
+* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
+* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
+* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
+* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
+* PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support appliances, *
+* devices, or systems. Use in such applications are expressly *
+* prohibited. *
+* *
+* (c) Copyright 1995-2015 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+
+/*******************************************************************************
+* Generated from core with identifier: xilinx.com:ip:c_addsub:11.0 *
+* *
+* The Xilinx LogiCORE Adder Subtracter can create adders, subtracters, *
+* and adders/subtracters that operate on signed or unsigned data. In *
+* fabric, the module supports inputs ranging from 1 to 256 bits wide, *
+* and outputs ranging from 1 to 258 bits wide. I/O widths are family *
+* dependent for dsp48 implementations. *
+*******************************************************************************/
+
+// Interfaces:
+// a_intf
+// clk_intf
+// sclr_intf
+// ce_intf
+// b_intf
+// add_intf
+// c_in_intf
+// bypass_intf
+// sset_intf
+// sinit_intf
+// c_out_intf
+// s_intf
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+subtractor_s6 your_instance_name (
+ .a(a), // input [31 : 0] a
+ .b(b), // input [31 : 0] b
+ .c_in(c_in), // input c_in
+ .c_out(c_out), // output c_out
+ .s(s) // output [31 : 0] s
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file subtractor_s6.v when simulating
+// the core, subtractor_s6. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/src/rtl/ipcore/subtractor_s6.xco b/src/rtl/ipcore/subtractor_s6.xco new file mode 100644 index 0000000..3c4f664 --- /dev/null +++ b/src/rtl/ipcore/subtractor_s6.xco @@ -0,0 +1,73 @@ +##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Fri Jul 10 14:50:21 2015
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:c_addsub:11.0
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Adder_Subtracter xilinx.com:ip:c_addsub:11.0
+# END Select
+# BEGIN Parameters
+CSET a_type=Unsigned
+CSET a_width=32
+CSET add_mode=Subtract
+CSET ainit_value=0
+CSET b_constant=false
+CSET b_type=Unsigned
+CSET b_value=00000000000000000000000000000000
+CSET b_width=32
+CSET borrow_sense=Active_High
+CSET bypass=false
+CSET bypass_ce_priority=CE_Overrides_Bypass
+CSET bypass_sense=Active_High
+CSET c_in=true
+CSET c_out=true
+CSET ce=false
+CSET component_name=subtractor_s6
+CSET implementation=DSP48
+CSET latency=0
+CSET latency_configuration=Manual
+CSET out_width=32
+CSET sclr=false
+CSET sinit=false
+CSET sinit_value=0
+CSET sset=false
+CSET sync_ce_priority=Sync_Overrides_CE
+CSET sync_ctrl_priority=Reset_Overrides_Set
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2013-07-22T10:35:41Z
+# END Extra information
+GENERATE
+# CRC: aaca9d7a
diff --git a/src/rtl/ipcore/subtractor_s6.xise b/src/rtl/ipcore/subtractor_s6.xise new file mode 100644 index 0000000..9be6a8b --- /dev/null +++ b/src/rtl/ipcore/subtractor_s6.xise @@ -0,0 +1,73 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="subtractor_s6.ngc" xil_pn:type="FILE_NGC"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="subtractor_s6.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/> + </file> + </files> + + <properties> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|subtractor_s6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="subtractor_s6.ngc" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/subtractor_s6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_DesignName" xil_pn:value="subtractor_s6" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-07-10T17:51:04" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="DE7096E1188B4223AAFDCBA79BA57B43" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/src/rtl/ipcore/subtractor_s6/doc/c_addsub_v11_0_readme.txt b/src/rtl/ipcore/subtractor_s6/doc/c_addsub_v11_0_readme.txt new file mode 100644 index 0000000..9cd0739 --- /dev/null +++ b/src/rtl/ipcore/subtractor_s6/doc/c_addsub_v11_0_readme.txt @@ -0,0 +1,164 @@ +CHANGE LOG for Xilinx LogiCORE Adder/Subtracter v11.0 + +Release Date: October 2, 2013 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + + This file contains the change log for all released versions of the Xilinx + LogiCORE IP Adder/Subtracter. + + For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/Adder_Subtracter.htm + + For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + + For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + + +2. DEVICE SUPPORT + + 2.1. ISE + + The following device families are supported by the core for this release: + + All Series 7 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Virtex-4 devices + All Spartan-3 devices + + +3. NEW FEATURE HISTORY + + 3.1 ISE + + v11.0 + Ongoing new device support. + + +4. RESOLVED ISSUES + + 4.1 ISE + + - GUI would allow CE pin to be set when Latency was zero. + CE is now set false and disabled. + CR667406 + + +5. KNOWN ISSUES & LIMITATIONS + + The following are known issues for this core at time of release: + + 5.1 ISE + - None + + - For a comprehensive listing of Known Issues for this core, please see the IP + Release Notes Guide, + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +6. TECHNICAL SUPPORT & FEEDBACK + + To obtain technical support, create a WebCase at www.xilinx.com/support. + Questions are routed to a team with expertise using this product. + Please feel free to leave feedback on this IP under the "Leave Feedback" + menu item in Vivado/PlanAhead. + + Xilinx provides technical support for use of this product when used + according to the guidelines described in the core documentation, and + cannot guarantee timing, functionality, or support of this product for + designs that do not follow specified guidelines. + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +10/02/2013 Xilinx, Inc. 11.0 ISE 14.7 support and Production support for Series 7 +06/19/2012 Xilinx, Inc. 11.0 ISE 14.6 support +03/20/2012 Xilinx, Inc. 11.0 ISE 14.5 support. +10/16/2012 Xilinx, Inc. 11.0 ISE 14.3 and Vivado 2012.3 support +07/25/2012 Xilinx, Inc. 11.0 ISE 14.2 and Vivado 2012.2 support +04/24/2012 Xilinx, Inc. 11.0 ISE 14.1 and Vivado 2012.1 support +01/11/2012 Xilinx, Inc. 11.0 ISE 13.4 support +10/19/2011 Xilinx, Inc. 11.0 ISE 13.3 support +06/22/2011 Xilinx, Inc. 11.0 ISE 13.2 support, Artix-7 support +03/01/2011 Xilinx, Inc 11.0 ISE 13.1 support +04/19/2010 Xilinx, Inc. 11.0 ISE 12.1 support, Virtex-6Q and Spartan-6Q support +12/02/2009 Xilinx, Inc. 11.0 ISE 11.4 support, Spartan-6l and Automotive Spartan6 support +09/16/2009 Xilinx, Inc. 11.0 ISE 11.3 support, Virtex-6l support +04/24/2009 Xilinx, Inc. 11.0 ISE 11.1 support +09/19/2008 Xilinx, Inc. 10.0 ISE 10.1.3 support +================================================================================ + + +8. LEGAL DISCLAIMER + + (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + diff --git a/src/rtl/ipcore/subtractor_s6/doc/c_addsub_v11_0_vinfo.html b/src/rtl/ipcore/subtractor_s6/doc/c_addsub_v11_0_vinfo.html new file mode 100644 index 0000000..a043172 --- /dev/null +++ b/src/rtl/ipcore/subtractor_s6/doc/c_addsub_v11_0_vinfo.html @@ -0,0 +1,175 @@ +<HTML> +<HEAD> +<TITLE>c_addsub_v11_0_vinfo</TITLE> +<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1"> +</HEAD> +<BODY> +<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1"> +CHANGE LOG for Xilinx LogiCORE Adder/Subtracter v11.0 + +Release Date: October 2, 2013 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + + This file contains the change log for all released versions of the Xilinx + LogiCORE IP Adder/Subtracter. + + For the latest core updates, see the product page at: + + <A HREF="http://www.xilinx.com/products/ipcenter/Adder_Subtracter.htm">www.xilinx.com/products/ipcenter/Adder_Subtracter.htm</A> + + For installation instructions for this release, please go to: + + <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A> + + For system requirements: + + <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A> + + +2. DEVICE SUPPORT + + 2.1. ISE + + The following device families are supported by the core for this release: + + All Series 7 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Virtex-4 devices + All Spartan-3 devices + + +3. NEW FEATURE HISTORY + + 3.1 ISE + + v11.0 + Ongoing new device support. + + +4. RESOLVED ISSUES + + 4.1 ISE + + - GUI would allow CE pin to be set when Latency was zero. + CE is now set false and disabled. + CR667406 + + +5. KNOWN ISSUES & LIMITATIONS + + The following are known issues for this core at time of release: + + 5.1 ISE + - None + + - For a comprehensive listing of Known Issues for this core, please see the IP + Release Notes Guide, + + <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A> + + +6. TECHNICAL SUPPORT & FEEDBACK + + To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A> + Questions are routed to a team with expertise using this product. + Please feel free to leave feedback on this IP under the "Leave Feedback" + menu item in Vivado/PlanAhead. + + Xilinx provides technical support for use of this product when used + according to the guidelines described in the core documentation, and + cannot guarantee timing, functionality, or support of this product for + designs that do not follow specified guidelines. + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +10/02/2013 Xilinx, Inc. 11.0 ISE 14.7 support and Production support for Series 7 +06/19/2012 Xilinx, Inc. 11.0 ISE 14.6 support +03/20/2012 Xilinx, Inc. 11.0 ISE 14.5 support. +10/16/2012 Xilinx, Inc. 11.0 ISE 14.3 and Vivado 2012.3 support +07/25/2012 Xilinx, Inc. 11.0 ISE 14.2 and Vivado 2012.2 support +04/24/2012 Xilinx, Inc. 11.0 ISE 14.1 and Vivado 2012.1 support +01/11/2012 Xilinx, Inc. 11.0 ISE 13.4 support +10/19/2011 Xilinx, Inc. 11.0 ISE 13.3 support +06/22/2011 Xilinx, Inc. 11.0 ISE 13.2 support, Artix-7 support +03/01/2011 Xilinx, Inc 11.0 ISE 13.1 support +04/19/2010 Xilinx, Inc. 11.0 ISE 12.1 support, Virtex-6Q and Spartan-6Q support +12/02/2009 Xilinx, Inc. 11.0 ISE 11.4 support, Spartan-6l and Automotive Spartan6 support +09/16/2009 Xilinx, Inc. 11.0 ISE 11.3 support, Virtex-6l support +04/24/2009 Xilinx, Inc. 11.0 ISE 11.1 support +09/19/2008 Xilinx, Inc. 10.0 ISE 10.1.3 support +================================================================================ + + +8. LEGAL DISCLAIMER + + (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + +</FONT> +</PRE> +</BODY> +</HTML> diff --git a/src/rtl/ipcore/subtractor_s6/doc/ds214_addsub.pdf b/src/rtl/ipcore/subtractor_s6/doc/ds214_addsub.pdf Binary files differnew file mode 100644 index 0000000..6030595 --- /dev/null +++ b/src/rtl/ipcore/subtractor_s6/doc/ds214_addsub.pdf diff --git a/src/rtl/ipcore/subtractor_s6_flist.txt b/src/rtl/ipcore/subtractor_s6_flist.txt new file mode 100644 index 0000000..63b0075 --- /dev/null +++ b/src/rtl/ipcore/subtractor_s6_flist.txt @@ -0,0 +1,14 @@ +# Output products list for <subtractor_s6>
+subtractor_s6.asy
+subtractor_s6.gise
+subtractor_s6.ngc
+subtractor_s6.sym
+subtractor_s6.v
+subtractor_s6.veo
+subtractor_s6.xco
+subtractor_s6.xise
+subtractor_s6\doc\c_addsub_v11_0_readme.txt
+subtractor_s6\doc\c_addsub_v11_0_vinfo.html
+subtractor_s6\doc\ds214_addsub.pdf
+subtractor_s6_flist.txt
+subtractor_s6_xmdf.tcl
diff --git a/src/rtl/ipcore/subtractor_s6_xmdf.tcl b/src/rtl/ipcore/subtractor_s6_xmdf.tcl new file mode 100644 index 0000000..e081cd7 --- /dev/null +++ b/src/rtl/ipcore/subtractor_s6_xmdf.tcl @@ -0,0 +1,83 @@ +# The package naming convention is <core_name>_xmdf
+package provide subtractor_s6_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::subtractor_s6_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::subtractor_s6_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name subtractor_s6
+}
+# ::subtractor_s6_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::subtractor_s6_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6/doc/c_addsub_v11_0_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6/doc/c_addsub_v11_0_vinfo.html
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6/doc/ds214_addsub.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6.sym
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module subtractor_s6
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/src/rtl/ipcore/tmp/_xmsgs/netgen.xmsgs b/src/rtl/ipcore/tmp/_xmsgs/netgen.xmsgs new file mode 100644 index 0000000..00fafd8 --- /dev/null +++ b/src/rtl/ipcore/tmp/_xmsgs/netgen.xmsgs @@ -0,0 +1,12 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages> +<msg type="info" file="NetListWriters" num="633" delta="old" >The generated Verilog netlist contains Xilinx <arg fmt="%s" index="1">UNISIM</arg> simulation primitives and has to be used with <arg fmt="%s" index="2">UNISIM</arg> simulation library for correct compilation and simulation.
+</msg>
+ +</messages> +
diff --git a/src/rtl/ipcore/tmp/_xmsgs/pn_parser.xmsgs b/src/rtl/ipcore/tmp/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..b73af21 --- /dev/null +++ b/src/rtl/ipcore/tmp/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated -->
+<!-- by the Xilinx ISE software. Any direct editing or -->
+<!-- changes made to this file may result in unpredictable -->
+<!-- behavior or data corruption. It is strongly advised that -->
+<!-- users do not edit the contents of this file. -->
+<!-- -->
+<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/multiplier_s6.v" into library work</arg>
+</msg>
+
+</messages>
+
diff --git a/src/rtl/ipcore/tmp/_xmsgs/xst.xmsgs b/src/rtl/ipcore/tmp/_xmsgs/xst.xmsgs new file mode 100644 index 0000000..8f5c63c --- /dev/null +++ b/src/rtl/ipcore/tmp/_xmsgs/xst.xmsgs @@ -0,0 +1,84 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages> +<msg type="warning" file="HDLCompiler" num="321" delta="old" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\xbip_utils_v2_0\bip_utils_pkg_v2_0.vhd" Line 1836: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="321" delta="old" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\xbip_utils_v2_0\bip_utils_pkg_v2_0.vhd" Line 1842: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="321" delta="old" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\xbip_utils_v2_0\bip_utils_pkg_v2_0.vhd" Line 1848: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="321" delta="old" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\xbip_utils_v2_0\bip_utils_pkg_v2_0.vhd" Line 1849: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="321" delta="old" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\xbip_utils_v2_0\bip_utils_pkg_v2_0.vhd" Line 1850: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="321" delta="old" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\xbip_utils_v2_0\bip_utils_pkg_v2_0.vhd" Line 1851: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="321" delta="old" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\xbip_utils_v2_0\bip_utils_pkg_v2_0.vhd" Line 1852: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="746" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\mult_gen_pkg_v11_2.vhd" Line 2242: Range is empty (null range)
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="871" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 3441: Using initial value <arg fmt="%s" index="1">'0'</arg> for <arg fmt="%s" index="2">ce_opmode</arg> since it is never assigned
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 260: Net <<arg fmt="%s" index="1">c[0][1][47]</arg>> does not have a driver.
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 264: Net <<arg fmt="%s" index="1">d[0][0][17]</arg>> does not have a driver.
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 3436: Net <<arg fmt="%s" index="1">use_DSP48a.appDSP48A[0].bppDSP48A[0].cec</arg>> does not have a driver.
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 3437: Net <<arg fmt="%s" index="1">use_DSP48a.appDSP48A[0].bppDSP48A[0].ced</arg>> does not have a driver.
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 3438: Net <<arg fmt="%s" index="1">use_DSP48a.appDSP48A[0].bppDSP48A[0].cem</arg>> does not have a driver.
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 3439: Net <<arg fmt="%s" index="1">use_DSP48a.appDSP48A[0].bppDSP48A[0].cep</arg>> does not have a driver.
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 3440: Net <<arg fmt="%s" index="1">use_DSP48a.appDSP48A[0].bppDSP48A[0].ce_carryin</arg>> does not have a driver.
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 3443: Net <<arg fmt="%s" index="1">use_DSP48a.appDSP48A[0].bppDSP48A[0].cin_dsp48a</arg>> does not have a driver.
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 3435: Net <<arg fmt="%s" index="1">use_DSP48a.appDSP48A[1].bppDSP48A[0].ceb</arg>> does not have a driver.
+</msg>
+ +<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\multiplier_s6.vhd</arg>" line <arg fmt="%s" index="2">110</arg>: Output port <<arg fmt="%s" index="3">zero_detect</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
+</msg>
+ +<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\multiplier_s6.vhd</arg>" line <arg fmt="%s" index="2">110</arg>: Output port <<arg fmt="%s" index="3">pcasc</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
+</msg>
+ +<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">use_DSP48a.appDSP48A[0].bppDSP48A[0].iDSP48A</arg> in unit <arg fmt="%s" index="2">dsp</arg> of type <arg fmt="%s" index="3">DSP48A</arg> has been replaced by <arg fmt="%s" index="4">DSP48A1</arg>
+</msg>
+ +<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">use_DSP48a.appDSP48A[0].bppDSP48A[1].iDSP48A</arg> in unit <arg fmt="%s" index="2">dsp</arg> of type <arg fmt="%s" index="3">DSP48A</arg> has been replaced by <arg fmt="%s" index="4">DSP48A1</arg>
+</msg>
+ +<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">use_DSP48a.appDSP48A[1].bppDSP48A[0].iDSP48A</arg> in unit <arg fmt="%s" index="2">dsp</arg> of type <arg fmt="%s" index="3">DSP48A</arg> has been replaced by <arg fmt="%s" index="4">DSP48A1</arg>
+</msg>
+ +<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">use_DSP48a.appDSP48A[1].bppDSP48A[1].iDSP48A</arg> in unit <arg fmt="%s" index="2">dsp</arg> of type <arg fmt="%s" index="3">DSP48A</arg> has been replaced by <arg fmt="%s" index="4">DSP48A1</arg>
+</msg>
+ +<msg type="info" file="Xst" num="2169" delta="new" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
+</msg>
+ +</messages> +
diff --git a/src/rtl/ipcore/tmp/multiplier_s6.lso b/src/rtl/ipcore/tmp/multiplier_s6.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/src/rtl/ipcore/tmp/multiplier_s6.lso @@ -0,0 +1 @@ +work
diff --git a/src/rtl/ipcore/tmp/subtractor_s6.lso b/src/rtl/ipcore/tmp/subtractor_s6.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/src/rtl/ipcore/tmp/subtractor_s6.lso @@ -0,0 +1 @@ +work
diff --git a/src/rtl/modexps6_adder64_carry32.v b/src/rtl/modexps6_adder64_carry32.v new file mode 100644 index 0000000..87869d1 --- /dev/null +++ b/src/rtl/modexps6_adder64_carry32.v @@ -0,0 +1,70 @@ +`timescale 1ns / 1ps
+
+module modexps6_adder64_carry32
+ (
+ clk, t, x, y, s, c_in, c_out
+ );
+
+
+ //
+ // Ports
+ //
+ input wire clk;
+ input wire [31: 0] t;
+ input wire [31: 0] x;
+ input wire [31: 0] y;
+ output wire [31: 0] s;
+ input wire [31: 0] c_in;
+ output wire [31: 0] c_out;
+
+
+ //
+ // Multiplier
+ //
+ wire [63: 0] multiplier_out;
+
+ multiplier_s6 dsp_multiplier
+ (
+ .clk (clk),
+ .a (x),
+ .b (y),
+ .p (multiplier_out)
+ );
+
+
+ //
+ // Carry and T
+ //
+ wire [63: 0] t_ext = {{32{1'b0}}, t};
+ wire [63: 0] c_ext = {{32{1'b0}}, c_in};
+
+
+ //
+ // Sum
+ //
+ wire [63: 0] sum = multiplier_out + c_in + t;
+
+
+ //
+ // Output
+ //
+ assign s = sum[31: 0];
+ assign c_out = sum[63:32];
+
+ /*
+ reg [31: 0] s_reg;
+ reg [31: 0] c_out_reg;
+
+ assign s = s_reg;
+ assign c_out = c_out_reg;
+
+ always @(posedge clk) begin
+ //
+ s_reg <= sum[31: 0];
+ c_out_reg <= sum[63:32];
+ //
+ end
+ */
+
+
+endmodule
diff --git a/src/rtl/modexps6_buffer_core.v b/src/rtl/modexps6_buffer_core.v new file mode 100644 index 0000000..86a6a4d --- /dev/null +++ b/src/rtl/modexps6_buffer_core.v @@ -0,0 +1,202 @@ +`timescale 1ns / 1ps
+
+module modexps6_buffer_core
+ (
+ clk, + rw_coeff_bram_addr, rw_coeff_bram_wr, rw_coeff_bram_in, rw_coeff_bram_out, ro_coeff_bram_addr, ro_coeff_bram_out,
+ rw_mm_bram_addr, rw_mm_bram_wr, rw_mm_bram_in, rw_mm_bram_out, ro_mm_bram_addr, ro_mm_bram_out, + rw_nn_bram_addr, rw_nn_bram_wr, rw_nn_bram_in, ro_nn_bram_addr, ro_nn_bram_out,
+ rw_y_bram_addr, rw_y_bram_wr, rw_y_bram_in, rw_y_bram_out, + rw_r_bram_addr, rw_r_bram_wr, rw_r_bram_in, rw_r_bram_out, ro_r_bram_addr, ro_r_bram_out, + rw_t_bram_addr, rw_t_bram_wr, rw_t_bram_in, rw_t_bram_out, ro_t_bram_addr, ro_t_bram_out
+ );
+
+ //
+ // Parameters
+ //
+ parameter OPERAND_ADDR_WIDTH = 5; // 1024 / 32 = 32 -> 5 bits
+
+
+ // + // Ports + // + input wire clk; + + input wire [OPERAND_ADDR_WIDTH:0] rw_coeff_bram_addr; + input wire rw_coeff_bram_wr; + input wire [ 31:0] rw_coeff_bram_in; + output wire [ 31:0] rw_coeff_bram_out;
+
+ input wire [OPERAND_ADDR_WIDTH:0] rw_mm_bram_addr; + input wire rw_mm_bram_wr; + input wire [ 31:0] rw_mm_bram_in; + output wire [ 31:0] rw_mm_bram_out;
+
+ input wire [OPERAND_ADDR_WIDTH:0] rw_nn_bram_addr; + input wire rw_nn_bram_wr; + input wire [ 31:0] rw_nn_bram_in;
+
+ input wire [OPERAND_ADDR_WIDTH:0] rw_y_bram_addr; + input wire rw_y_bram_wr; + input wire [ 31:0] rw_y_bram_in; + output wire [ 31:0] rw_y_bram_out;
+
+ input wire [OPERAND_ADDR_WIDTH:0] rw_r_bram_addr; + input wire rw_r_bram_wr; + input wire [ 31:0] rw_r_bram_in; + output wire [ 31:0] rw_r_bram_out;
+
+ input wire [OPERAND_ADDR_WIDTH:0] rw_t_bram_addr; + input wire rw_t_bram_wr; + input wire [ 31:0] rw_t_bram_in; + output wire [ 31:0] rw_t_bram_out;
+ + input wire [OPERAND_ADDR_WIDTH:0] ro_coeff_bram_addr; + output wire [ 31:0] ro_coeff_bram_out; + + input wire [OPERAND_ADDR_WIDTH:0] ro_mm_bram_addr; + output wire [ 31:0] ro_mm_bram_out; + + input wire [OPERAND_ADDR_WIDTH:0] ro_nn_bram_addr; + output wire [ 31:0] ro_nn_bram_out;
+
+ input wire [OPERAND_ADDR_WIDTH:0] ro_r_bram_addr; + output wire [ 31:0] ro_r_bram_out; + + input wire [OPERAND_ADDR_WIDTH:0] ro_t_bram_addr; + output wire [ 31:0] ro_t_bram_out; + + + //
+ // Montgomery Coefficient
+ // + ram_1rw_1ro_readfirst #
+ (
+ .MEM_WIDTH (32), + .MEM_ADDR_BITS (OPERAND_ADDR_WIDTH+1)
+ )
+ mem_coeff
+ (
+ .clk (clk),
+ + .a_addr (rw_coeff_bram_addr), + .a_wr (rw_coeff_bram_wr), + .a_in (rw_coeff_bram_in), + .a_out (rw_coeff_bram_out), + + .b_addr (ro_coeff_bram_addr), + .b_out (ro_coeff_bram_out)
+ );
+
+
+ //
+ // Powers of Message
+ //
+ ram_1rw_1ro_readfirst #
+ (
+ .MEM_WIDTH (32), + .MEM_ADDR_BITS (OPERAND_ADDR_WIDTH+1)
+ )
+ mem_mm
+ (
+ .clk (clk),
+ + .a_addr (rw_mm_bram_addr), + .a_wr (rw_mm_bram_wr), + .a_in (rw_mm_bram_in), + .a_out (rw_mm_bram_out), + + .b_addr (ro_mm_bram_addr), + .b_out (ro_mm_bram_out)
+ );
+
+
+ //
+ // Extended Modulus
+ //
+ ram_1rw_1ro_readfirst #
+ (
+ .MEM_WIDTH (32), + .MEM_ADDR_BITS (OPERAND_ADDR_WIDTH+1)
+ )
+ mem_nn
+ (
+ .clk (clk),
+ + .a_addr (rw_nn_bram_addr), + .a_wr (rw_nn_bram_wr), + .a_in (rw_nn_bram_in), + .a_out (), + + .b_addr (ro_nn_bram_addr), + .b_out (ro_nn_bram_out)
+ );
+
+
+ //
+ // Output
+ //
+ ram_1rw_1ro_readfirst #
+ (
+ .MEM_WIDTH (32), + .MEM_ADDR_BITS (OPERAND_ADDR_WIDTH+1)
+ )
+ mem_y
+ (
+ .clk (clk),
+ + .a_addr (rw_y_bram_addr), + .a_wr (rw_y_bram_wr), + .a_in (rw_y_bram_in), + .a_out (rw_y_bram_out), + + .b_addr ({(OPERAND_ADDR_WIDTH+1){1'b0}}), + .b_out ()
+ );
+
+
+ //
+ // Result of Multiplication
+ //
+ ram_1rw_1ro_readfirst #
+ (
+ .MEM_WIDTH (32), + .MEM_ADDR_BITS (OPERAND_ADDR_WIDTH+1)
+ )
+ mem_r
+ (
+ .clk (clk),
+ + .a_addr (rw_r_bram_addr), + .a_wr (rw_r_bram_wr), + .a_in (rw_r_bram_in), + .a_out (rw_r_bram_out), + + .b_addr (ro_r_bram_addr), + .b_out (ro_r_bram_out)
+ );
+
+
+ //
+ // Temporary Buffer
+ //
+ ram_1rw_1ro_readfirst #
+ (
+ .MEM_WIDTH (32), + .MEM_ADDR_BITS (OPERAND_ADDR_WIDTH+1)
+ )
+ mem_t
+ (
+ .clk (clk),
+ + .a_addr (rw_t_bram_addr), + .a_wr (rw_t_bram_wr), + .a_in (rw_t_bram_in), + .a_out (rw_t_bram_out), + + .b_addr (ro_t_bram_addr), + .b_out (ro_t_bram_out)
+ );
+
+
+endmodule
diff --git a/src/rtl/modexps6_buffer_user.v b/src/rtl/modexps6_buffer_user.v new file mode 100644 index 0000000..6072fc9 --- /dev/null +++ b/src/rtl/modexps6_buffer_user.v @@ -0,0 +1,185 @@ +`timescale 1ns / 1ps
+
+module modexps6_buffer_user
+ (
+ clk,
+
+ bus_cs, bus_we,
+ bus_addr, bus_data_wr, bus_data_rd,
+
+ ro_modulus_bram_addr, ro_modulus_bram_out,
+ ro_message_bram_addr, ro_message_bram_out,
+ ro_exponent_bram_addr, ro_exponent_bram_out,
+ rw_result_bram_addr,
+ rw_result_bram_wr, rw_result_bram_in
+ );
+
+
+ //
+ // Parameters
+ //
+ parameter OPERAND_ADDR_WIDTH = 5; // 1024 / 32 = 32 -> 5 bits
+
+
+ //
+ // Locals
+ //
+ localparam ADDR_WIDTH_TOTAL = OPERAND_ADDR_WIDTH + 2;
+ + localparam [ 1: 0] BUS_ADDR_BANK_MODULUS = 2'b00; + localparam [ 1: 0] BUS_ADDR_BANK_MESSAGE = 2'b01; + localparam [ 1: 0] BUS_ADDR_BANK_EXPONENT = 2'b10; + localparam [ 1: 0] BUS_ADDR_BANK_RESULT = 2'b11;
+
+ //
+ // Ports
+ //
+ input wire clk;
+
+ input wire bus_cs;
+ input wire bus_we;
+ input wire [ ADDR_WIDTH_TOTAL-1:0] bus_addr;
+ input wire [ 31:0] bus_data_wr;
+ output wire [ 31:0] bus_data_rd;
+
+ input wire [OPERAND_ADDR_WIDTH-1:0] ro_modulus_bram_addr;
+ output wire [ 31:0] ro_modulus_bram_out;
+
+ input wire [OPERAND_ADDR_WIDTH-1:0] ro_message_bram_addr;
+ output wire [ 31:0] ro_message_bram_out;
+
+ input wire [OPERAND_ADDR_WIDTH-1:0] ro_exponent_bram_addr;
+ output wire [ 31:0] ro_exponent_bram_out;
+
+ input wire [OPERAND_ADDR_WIDTH-1:0] rw_result_bram_addr;
+ input wire rw_result_bram_wr;
+ input wire [ 31:0] rw_result_bram_in;
+
+
+ //
+ // Address Decoder
+ //
+ wire [OPERAND_ADDR_WIDTH-1:0] bus_addr_operand_word = bus_addr[OPERAND_ADDR_WIDTH-1:0];
+ wire [ 1:0] bus_addr_operand_bank = bus_addr[ADDR_WIDTH_TOTAL-1:ADDR_WIDTH_TOTAL-2];
+
+
+ //
+ // Modulus Memory
+ //
+ wire [31: 0] bus_data_rd_modulus;
+
+ ram_1rw_1ro_readfirst #
+ (
+ .MEM_WIDTH (32), + .MEM_ADDR_BITS (OPERAND_ADDR_WIDTH)
+ )
+ mem_modulus
+ (
+ .clk (clk),
+ + .a_addr (bus_addr_operand_word),
+ .a_wr (bus_cs & bus_we & (bus_addr_operand_bank == BUS_ADDR_BANK_MODULUS)),
+ .a_in (bus_data_wr),
+ .a_out (bus_data_rd_modulus),
+ + .b_addr (ro_modulus_bram_addr),
+ .b_out (ro_modulus_bram_out)
+ );
+
+
+ //
+ // Message Memory
+ //
+ wire [31: 0] bus_data_rd_message;
+
+ ram_1rw_1ro_readfirst #
+ (
+ .MEM_WIDTH (32), + .MEM_ADDR_BITS (OPERAND_ADDR_WIDTH)
+ )
+ mem_message
+ (
+ .clk (clk),
+ + .a_addr (bus_addr_operand_word),
+ .a_wr (bus_cs & bus_we & (bus_addr_operand_bank == BUS_ADDR_BANK_MESSAGE)),
+ .a_in (bus_data_wr),
+ .a_out (bus_data_rd_message),
+ + .b_addr (ro_message_bram_addr),
+ .b_out (ro_message_bram_out)
+ );
+
+
+ //
+ // Exponent Memory
+ //
+ wire [31: 0] bus_data_rd_exponent;
+
+ ram_1rw_1ro_readfirst #
+ (
+ .MEM_WIDTH (32), + .MEM_ADDR_BITS (OPERAND_ADDR_WIDTH)
+ )
+ mem_exponent
+ (
+ .clk (clk),
+ + .a_addr (bus_addr_operand_word),
+ .a_wr (bus_cs & bus_we & (bus_addr_operand_bank == BUS_ADDR_BANK_EXPONENT)),
+ .a_in (bus_data_wr),
+ .a_out (bus_data_rd_exponent),
+ + .b_addr (ro_exponent_bram_addr),
+ .b_out (ro_exponent_bram_out)
+ );
+
+
+ //
+ // Result Memory
+ //
+ wire [31: 0] bus_data_rd_result;
+
+ ram_1rw_1ro_readfirst #
+ (
+ .MEM_WIDTH (32), + .MEM_ADDR_BITS (OPERAND_ADDR_WIDTH)
+ )
+ mem_result
+ (
+ .clk (clk),
+ + .a_addr (rw_result_bram_addr),
+ .a_wr (rw_result_bram_wr),
+ .a_in (rw_result_bram_in),
+ .a_out (),
+ + .b_addr (bus_addr_operand_word),
+ .b_out (bus_data_rd_result)
+ );
+
+
+ //
+ // Output Selector
+ //
+ reg [ 1: 0] bus_addr_operand_bank_prev;
+ always @(posedge clk) bus_addr_operand_bank_prev = bus_addr_operand_bank;
+
+ reg [31: 0] bus_data_rd_mux;
+ assign bus_data_rd = bus_data_rd_mux;
+
+ always @(*)
+ //
+ case (bus_addr_operand_bank_prev)
+ //
+ BUS_ADDR_BANK_MODULUS: bus_data_rd_mux = bus_data_rd_modulus;
+ BUS_ADDR_BANK_MESSAGE: bus_data_rd_mux = bus_data_rd_message;
+ BUS_ADDR_BANK_EXPONENT: bus_data_rd_mux = bus_data_rd_exponent;
+ BUS_ADDR_BANK_RESULT: bus_data_rd_mux = bus_data_rd_result;
+ //
+ default: bus_data_rd_mux = {32{1'bX}};
+ //
+ endcase
+
+
+endmodule
diff --git a/src/rtl/modexps6_modinv32.v b/src/rtl/modexps6_modinv32.v new file mode 100644 index 0000000..dc08b7b --- /dev/null +++ b/src/rtl/modexps6_modinv32.v @@ -0,0 +1,116 @@ +`timescale 1ns / 1ps
+
+module modexps6_modinv32
+ (
+ clk,
+ ena, rdy,
+ n0, n0_modinv
+ );
+
+
+ //
+ // Ports
+ //
+ input wire clk;
+
+ input wire ena;
+ output wire rdy;
+
+ input wire [31: 0] n0;
+ output wire [31: 0] n0_modinv;
+
+
+ // + // Trigger + // + reg ena_dly = 1'b0;
+ wire ena_trig = ena && !ena_dly; + always @(posedge clk) ena_dly <= ena;
+
+
+ // + // Ready Register + // + reg rdy_reg = 1'b0; + assign rdy = rdy_reg;
+
+
+ //
+ // Counter
+ //
+ reg [ 7: 0] cnt = 8'd0;
+ wire [ 7: 0] cnt_zero = 8'd0;
+ wire [ 7: 0] cnt_last = 8'd132;
+ wire [ 7: 0] cnt_next = cnt + 1'b1;
+ wire [ 1: 0] cnt_phase = cnt[1:0];
+ wire [ 5: 0] cnt_cycle = cnt[7:2];
+
+ always @(posedge clk)
+ //
+ if (cnt == cnt_zero) cnt <= (!rdy_reg && ena_trig) ? cnt_next : cnt_zero;
+ else cnt <= (cnt == cnt_last) ? cnt_zero : cnt_next;
+
+
+ // + // Enable / Ready Logic + // + always @(posedge clk) + // + if (cnt == cnt_last) rdy_reg <= 1'b1; + else if ((cnt == cnt_zero) && (rdy_reg && !ena)) rdy_reg <= 1'b0;
+
+
+ //
+ // Output Register
+ //
+ reg [31: 0] n0_modinv_reg;
+ assign n0_modinv = n0_modinv_reg;
+
+
+ //
+ // Multiplier
+ //
+ wire [63: 0] multiplier_out;
+ wire [31: 0] multiplier_out_masked = multiplier_out[31: 0] & {mask_reg, 1'b1};
+
+ multiplier_s6 dsp_multiplier
+ (
+ .clk (clk),
+ .a (n0),
+ .b (n0_modinv_reg),
+ .p (multiplier_out)
+ );
+
+
+ //
+ // Mask and Power
+ //
+ reg [30: 0] mask_reg;
+ reg [31: 0] power_reg;
+
+ always @(posedge clk)
+ //
+ if (cnt_phase == 2'd1) begin
+ //
+ if (cnt_cycle == 6'd0) begin
+ //
+ mask_reg <= 31'd0;
+ power_reg <= 32'd1;
+ //
+ n0_modinv_reg <= 32'd0;
+ //
+ end else begin
+ //
+ mask_reg <= { mask_reg[29:0], 1'b1};
+ power_reg <= {power_reg[30:0], 1'b0};
+ //
+ if (multiplier_out_masked != 32'd1)
+ //
+ n0_modinv_reg <= n0_modinv_reg + power_reg;
+ //
+ end
+ //
+ end
+
+
+endmodule
diff --git a/src/rtl/modexps6_montgomery_coeff.v b/src/rtl/modexps6_montgomery_coeff.v new file mode 100644 index 0000000..c3ceeee --- /dev/null +++ b/src/rtl/modexps6_montgomery_coeff.v @@ -0,0 +1,410 @@ +`timescale 1ns / 1ps
+
+module modexps6_montgomery_coeff
+ (
+ clk, + ena, rdy, + modulus_width, + coeff_bram_addr, coeff_bram_wr, coeff_bram_in, coeff_bram_out,
+ nn_bram_addr, nn_bram_wr, nn_bram_in, + modulus_bram_addr, modulus_bram_out,
+ modinv_n0, modinv_ena, modinv_rdy
+ );
+
+
+ // + // Parameters + // + parameter MODULUS_NUM_BITS = 11; // 1024 -> 11 bits
+ parameter OPERAND_ADDR_WIDTH = 5; // 1024 / 32 = 32 -> 5 bits
+
+
+ //
+ // Locals
+ //
+ localparam [ MODULUS_NUM_BITS :0] round_count_zero = {1'b0, {MODULUS_NUM_BITS{1'b0}}};
+ localparam [OPERAND_ADDR_WIDTH :0] coeff_bram_addr_zero = {1'b0, {OPERAND_ADDR_WIDTH{1'b0}}};
+ localparam [OPERAND_ADDR_WIDTH-1:0] modulus_bram_addr_zero = {OPERAND_ADDR_WIDTH{1'b0}};
+
+
+ // + // Ports + // + input wire clk; + + input wire ena; + output wire rdy; + + input wire [ MODULUS_NUM_BITS-1:0] modulus_width; + + output wire [OPERAND_ADDR_WIDTH :0] coeff_bram_addr; + output wire coeff_bram_wr; + output wire [ 31:0] coeff_bram_in; + input wire [ 31:0] coeff_bram_out;
+
+ output wire [OPERAND_ADDR_WIDTH :0] nn_bram_addr;
+ output wire nn_bram_wr;
+ output wire [ 31:0] nn_bram_in; + + output wire [OPERAND_ADDR_WIDTH-1:0] modulus_bram_addr; + input wire [ 31:0] modulus_bram_out;
+
+ output wire [ 31:0] modinv_n0;
+ output wire modinv_ena;
+ input wire modinv_rdy;
+
+
+ // + // FSM + // + localparam FSM_STATE_IDLE = 6'd0; + + localparam FSM_STATE_INIT = 6'd10;
+
+ localparam FSM_STATE_SHIFT_READ = 6'd21;
+ localparam FSM_STATE_SHIFT_WRITE = 6'd22; +
+ localparam FSM_STATE_COMPARE_READ = 6'd31;
+ localparam FSM_STATE_COMPARE_COMPARE = 6'd32;
+
+ localparam FSM_STATE_SUBTRACT_READ = 6'd41;
+ localparam FSM_STATE_SUBTRACT_WRITE = 6'd42; +
+ localparam FSM_STATE_ROUND = 6'd50;
+ + localparam FSM_STATE_FINAL = 6'd60;
+
+ reg [ 5: 0] fsm_state = FSM_STATE_IDLE;
+
+
+ // + // Trigger + // + reg ena_dly = 1'b0;
+
+ wire ena_trig = ena && !ena_dly;
+ + always @(posedge clk) ena_dly <= ena;
+ + + // + // Ready Register + // + reg rdy_reg = 1'b0;
+ + assign rdy = rdy_reg;
+
+
+ //
+ // ModInv Control
+ //
+ reg modinv_ena_reg = 1'b0;
+ reg [31: 0] modinv_n0_reg;
+
+ assign modinv_ena = modinv_ena_reg;
+ assign modinv_n0 = modinv_n0_reg;
+
+
+ // + // Enable / Ready Logic + // + always @(posedge clk) + // + if (fsm_state == FSM_STATE_FINAL) begin
+ //
+ if (modinv_rdy) rdy_reg <= 1'b1;
+ // + end else if (fsm_state == FSM_STATE_IDLE) begin
+ //
+ if (rdy_reg && !ena) rdy_reg <= 1'b0;
+ //
+ end +
+
+ // + // Flags + // + reg reg_shift_carry = 1'b0;
+ reg reg_subtractor_borrow = 1'b0;
+
+
+ // + // Round Counter + // + reg [MODULUS_NUM_BITS:0] round_count = round_count_zero;
+ wire [MODULUS_NUM_BITS:0] round_count_last = {modulus_width, 1'b0} + 6'd63;
+ wire [MODULUS_NUM_BITS:0] round_count_next = (round_count < round_count_last) ? round_count + 1'b1 : round_count_zero; +
+
+ // + // Modulus BRAM Interface + // + reg [OPERAND_ADDR_WIDTH-1:0] modulus_bram_addr_reg = modulus_bram_addr_zero; + + assign modulus_bram_addr = modulus_bram_addr_reg;
+
+
+ // + // Coeff BRAM Interface + // + reg [OPERAND_ADDR_WIDTH:0] coeff_bram_addr_reg = coeff_bram_addr_zero; + reg coeff_bram_wr_reg = 1'b0; + + assign coeff_bram_addr = coeff_bram_addr_reg; + assign coeff_bram_wr = coeff_bram_wr_reg;
+
+
+ // + // NN BRAM Interface + // + reg [OPERAND_ADDR_WIDTH:0] nn_bram_addr_reg = coeff_bram_addr_zero; + reg nn_bram_wr_reg = 1'b0; + + assign nn_bram_addr = nn_bram_addr_reg; + assign nn_bram_wr = nn_bram_wr_reg;
+
+
+ //
+ // Hardware Subtractor
+ //
+ wire [31: 0] subtractor_out;
+ wire subtractor_out_nonzero = |subtractor_out;
+ wire subtractor_borrow_out;
+ wire subtractor_borrow_in;
+
+ assign subtractor_borrow_in = (fsm_state == FSM_STATE_COMPARE_COMPARE) ? 1'b0 : reg_subtractor_borrow;
+
+ subtractor_s6 dsp_subtractor
+ (
+ .a (coeff_bram_out),
+ .b (modulus_bram_out),
+ .s (subtractor_out),
+ .c_in (subtractor_borrow_in),
+ .c_out (subtractor_borrow_out)
+ );
+
+
+ // + // Handy Wires + //
+ wire [OPERAND_ADDR_WIDTH-1:0] modulus_width_msb = modulus_width[MODULUS_NUM_BITS-1:MODULUS_NUM_BITS-OPERAND_ADDR_WIDTH];
+
+ wire [OPERAND_ADDR_WIDTH :0] coeff_bram_addr_last = {modulus_width_msb, 1'b0}; + wire [OPERAND_ADDR_WIDTH :0] coeff_bram_addr_next_or_zero = (coeff_bram_addr_reg < coeff_bram_addr_last) ? coeff_bram_addr_reg + 1'b1 : coeff_bram_addr_zero;
+ wire [OPERAND_ADDR_WIDTH :0] coeff_bram_addr_next_or_last = (coeff_bram_addr_reg < coeff_bram_addr_last) ? coeff_bram_addr_reg + 1'b1 : coeff_bram_addr_last; + wire [OPERAND_ADDR_WIDTH :0] coeff_bram_addr_prev_or_zero = (coeff_bram_addr_reg > coeff_bram_addr_zero) ? coeff_bram_addr_reg - 1'b1 : coeff_bram_addr_zero;
+
+ wire [OPERAND_ADDR_WIDTH :0] modulus_bram_addr_last_ext = coeff_bram_addr_last - 1'b1;
+
+ wire [OPERAND_ADDR_WIDTH-1:0] modulus_bram_addr_last = modulus_bram_addr_last_ext[OPERAND_ADDR_WIDTH-1:0]; + wire [OPERAND_ADDR_WIDTH-1:0] modulus_bram_addr_next_or_zero = (modulus_bram_addr_reg < modulus_bram_addr_last) ? modulus_bram_addr_reg + 1'b1 : modulus_bram_addr_zero; + wire [OPERAND_ADDR_WIDTH-1:0] modulus_bram_addr_prev_or_zero = (modulus_bram_addr_reg > modulus_bram_addr_zero) ? modulus_bram_addr_reg - 1'b1 : modulus_bram_addr_zero;
+
+
+ //
+ // Coeff BRAM Input Logic
+ //
+ reg [31: 0] coeff_bram_in_mux;
+
+ assign coeff_bram_in = coeff_bram_in_mux;
+
+ always @(*)
+ //
+ case (fsm_state)
+
+ FSM_STATE_INIT:
+ //
+ if (coeff_bram_addr_reg == coeff_bram_addr_zero) coeff_bram_in_mux = 32'h00000001;
+ else coeff_bram_in_mux = 32'h00000000;
+
+ FSM_STATE_SHIFT_WRITE:
+ //
+ coeff_bram_in_mux = {coeff_bram_out[30:0], reg_shift_carry};
+
+ FSM_STATE_SUBTRACT_WRITE:
+ //
+ if (coeff_bram_addr_reg == coeff_bram_addr_last) coeff_bram_in_mux = 32'h00000000;
+ else coeff_bram_in_mux = subtractor_out;
+
+ default:
+ //
+ coeff_bram_in_mux = {32{1'bX}};
+
+ endcase
+
+
+ //
+ // NN BRAM Input Logic
+ //
+ reg [31: 0] nn_bram_in_mux;
+
+ assign nn_bram_in = nn_bram_in_mux;
+
+ always @(*)
+ //
+ case (fsm_state)
+
+ FSM_STATE_INIT:
+ //
+ if (coeff_bram_addr_reg == coeff_bram_addr_last) nn_bram_in_mux = {32{1'b0}};
+ else nn_bram_in_mux = modulus_bram_out;
+
+ default:
+ //
+ nn_bram_in_mux = {32{1'bX}};
+
+ endcase
+
+
+ //
+ // Comparison Functions
+ //
+ reg compare_greater_or_equal;
+ reg compare_less_than;
+
+ wire compare_done = compare_greater_or_equal | compare_less_than;
+
+ always @(*)
+ //
+ if (coeff_bram_addr_reg == coeff_bram_addr_last) compare_greater_or_equal = coeff_bram_out[0];
+ //
+ else if (coeff_bram_addr_reg == coeff_bram_addr_zero) compare_greater_or_equal = !subtractor_borrow_out;
+ //
+ else compare_greater_or_equal = !subtractor_borrow_out && subtractor_out_nonzero;
+
+ always @(*)
+ //
+ if (coeff_bram_addr_reg == coeff_bram_addr_last) compare_less_than = 1'b0;
+ //
+ else compare_less_than = subtractor_borrow_out;
+
+
+
+ //
+ // Main Logic
+ //
+ always @(posedge clk) + // + case (fsm_state) + + FSM_STATE_INIT: begin
+ //
+ coeff_bram_wr_reg <= (coeff_bram_addr_reg < coeff_bram_addr_last) ? 1'b1 : 1'b0;
+ coeff_bram_addr_reg <= coeff_bram_wr_reg ? coeff_bram_addr_next_or_zero : coeff_bram_addr_zero; + //
+ nn_bram_wr_reg <= (coeff_bram_addr_reg < coeff_bram_addr_last) ? 1'b1 : 1'b0;
+ nn_bram_addr_reg <= coeff_bram_wr_reg ? coeff_bram_addr_next_or_zero : coeff_bram_addr_zero;
+ //
+ if (!coeff_bram_wr_reg) begin
+ //
+ modinv_ena_reg <= 1'b1;
+ modinv_n0_reg <= modulus_bram_out;
+ //
+ end
+ //
+ if (modulus_bram_addr_reg == modulus_bram_addr_zero) begin
+ //
+ if (!coeff_bram_wr_reg)
+ //
+ modulus_bram_addr_reg <= modulus_bram_addr_next_or_zero;
+ //
+ end else begin
+ //
+ modulus_bram_addr_reg <= modulus_bram_addr_next_or_zero;
+ //
+ end
+ // + end +
+ FSM_STATE_SHIFT_READ: begin
+ //
+ coeff_bram_wr_reg <= 1'b1;
+ //
+ if (coeff_bram_addr_reg == coeff_bram_addr_zero)
+ //
+ reg_shift_carry <= 1'b0;
+ //
+ end
+
+ FSM_STATE_SHIFT_WRITE: begin
+ //
+ coeff_bram_wr_reg <= 1'b0;
+ coeff_bram_addr_reg <= coeff_bram_addr_next_or_last;
+ //
+ reg_shift_carry <= coeff_bram_out[31];
+ //
+ end
+
+ FSM_STATE_COMPARE_COMPARE: begin
+ //
+ coeff_bram_addr_reg <= compare_done ? coeff_bram_addr_zero : coeff_bram_addr_prev_or_zero;
+ //
+ modulus_bram_addr_reg <= compare_done ? modulus_bram_addr_zero : ((coeff_bram_addr_reg == coeff_bram_addr_last) ? modulus_bram_addr_last : modulus_bram_addr_prev_or_zero);
+ //
+ end
+
+ FSM_STATE_SUBTRACT_READ: begin
+ //
+ coeff_bram_wr_reg <= 1'b1;
+ //
+ if (coeff_bram_addr_reg == coeff_bram_addr_zero)
+ //
+ reg_subtractor_borrow <= 1'b0;
+ //
+ end
+
+ FSM_STATE_SUBTRACT_WRITE: begin
+ //
+ coeff_bram_wr_reg <= 1'b0;
+ coeff_bram_addr_reg <= coeff_bram_addr_next_or_zero;
+ //
+ modulus_bram_addr_reg <= (coeff_bram_addr_reg == coeff_bram_addr_last) ? modulus_bram_addr_zero : modulus_bram_addr_next_or_zero;
+ //
+ reg_subtractor_borrow <= subtractor_borrow_out;
+ //
+ end
+
+ FSM_STATE_ROUND: begin + //
+ round_count <= round_count_next;
+ //
+ end
+
+ FSM_STATE_FINAL: begin
+ //
+ if (modinv_rdy) modinv_ena_reg <= 1'b0;
+ //
+ end + + endcase
+
+
+ // + // FSM Transition Logic + // + always @(posedge clk) + // + case (fsm_state) + + FSM_STATE_IDLE: fsm_state <= (!rdy_reg && !modinv_rdy && ena_trig) ? FSM_STATE_INIT : FSM_STATE_IDLE; + + FSM_STATE_SHIFT_READ: fsm_state <= FSM_STATE_SHIFT_WRITE;
+ FSM_STATE_COMPARE_READ: fsm_state <= FSM_STATE_COMPARE_COMPARE;
+ FSM_STATE_SUBTRACT_READ: fsm_state <= FSM_STATE_SUBTRACT_WRITE;
+
+ FSM_STATE_INIT: fsm_state <= (coeff_bram_addr_reg < coeff_bram_addr_last) ? FSM_STATE_INIT : FSM_STATE_SHIFT_READ;
+ FSM_STATE_SHIFT_WRITE: fsm_state <= (coeff_bram_addr_reg < coeff_bram_addr_last) ? FSM_STATE_SHIFT_READ : FSM_STATE_COMPARE_READ;
+ FSM_STATE_SUBTRACT_WRITE: fsm_state <= (coeff_bram_addr_reg < coeff_bram_addr_last) ? FSM_STATE_SUBTRACT_READ : FSM_STATE_ROUND;
+
+ FSM_STATE_ROUND: fsm_state <= (round_count < round_count_last) ? FSM_STATE_SHIFT_READ : FSM_STATE_FINAL;
+ + FSM_STATE_COMPARE_COMPARE: fsm_state <= compare_done ? (compare_greater_or_equal ? FSM_STATE_SUBTRACT_READ : FSM_STATE_ROUND) : FSM_STATE_COMPARE_READ; + + FSM_STATE_FINAL: fsm_state <= modinv_rdy ? FSM_STATE_IDLE : FSM_STATE_FINAL;
+ + default: fsm_state <= FSM_STATE_IDLE; + + endcase
+
+
+endmodule
diff --git a/src/rtl/modexps6_montgomery_multiplier.v b/src/rtl/modexps6_montgomery_multiplier.v new file mode 100644 index 0000000..f22f93d --- /dev/null +++ b/src/rtl/modexps6_montgomery_multiplier.v @@ -0,0 +1,392 @@ +`timescale 1ns / 1ps
+
+module modexps6_montgomery_multiplier
+ (
+ clk, + ena, rdy, + operand_width, + x_bram_addr, x_bram_out, + y_bram_addr, y_bram_out, + n_bram_addr, n_bram_out, + z_bram_addr, z_bram_wr, z_bram_in, z_bram_out,
+ n0_modinv
+ );
+
+ //
+ // Parameters
+ //
+ parameter OPERAND_NUM_BITS = 11; // 1024 -> 11 bits
+ parameter OPERAND_ADDR_WIDTH = 5; // 1024 / 32 = 32 -> 5 bits
+
+
+ //
+ // Locals
+ //
+ localparam [OPERAND_ADDR_WIDTH:0] round_count_zero = {1'b0, {OPERAND_ADDR_WIDTH{1'b0}}};
+ localparam [OPERAND_ADDR_WIDTH:0] bram_addr_zero = {1'b0, {OPERAND_ADDR_WIDTH{1'b0}}};
+
+
+ //
+ // Ports
+ //
+ input wire clk;
+ + input wire ena;
+ output wire rdy;
+ + input wire [ OPERAND_NUM_BITS-1:0] operand_width;
+ + output wire [OPERAND_ADDR_WIDTH :0] x_bram_addr;
+ input wire [ 31:0] x_bram_out;
+ + output wire [OPERAND_ADDR_WIDTH :0] y_bram_addr;
+ input wire [ 31:0] y_bram_out;
+ + output wire [OPERAND_ADDR_WIDTH :0] n_bram_addr;
+ input wire [ 31:0] n_bram_out;
+ + output wire [OPERAND_ADDR_WIDTH :0] z_bram_addr;
+ output wire z_bram_wr;
+ output wire [ 31:0] z_bram_in;
+ input wire [ 31:0] z_bram_out;
+
+ input wire [ 31:0] n0_modinv;
+
+
+ // + // FSM + // + localparam FSM_STATE_IDLE = 6'd0; + + localparam FSM_STATE_INIT = 6'd10; + + localparam FSM_STATE_MUL_XY_CALC = 6'd21;
+ localparam FSM_STATE_MUL_XY_PIPELINE = 6'd22;
+ localparam FSM_STATE_MUL_XY_REGISTER = 6'd23;
+ localparam FSM_STATE_MUL_XY_WRITE = 6'd24;
+
+ localparam FSM_STATE_MAGIC_CALC = 6'd31;
+ localparam FSM_STATE_MAGIC_PIPELINE = 6'd32;
+ localparam FSM_STATE_MAGIC_REGISTER = 6'd33;
+
+ localparam FSM_STATE_MUL_MN_CALC = 6'd41;
+ localparam FSM_STATE_MUL_MN_PIPELINE = 6'd42;
+ localparam FSM_STATE_MUL_MN_REGISTER = 6'd43;
+ localparam FSM_STATE_MUL_MN_WRITE = 6'd44;
+
+ localparam FSM_STATE_SHIFT = 6'd50; + + localparam FSM_STATE_ROUND = 6'd55; + + localparam FSM_STATE_FINAL = 6'd60; + + reg [ 5: 0] fsm_state = FSM_STATE_IDLE;
+
+
+ // + // Trigger + // + reg ena_dly = 1'b0; + always @(posedge clk) ena_dly <= ena; + wire ena_trig = (ena == 1'b1) && (ena_dly == 1'b0); + + + // + // Ready Register + // + reg rdy_reg = 1'b0; + assign rdy = rdy_reg;
+
+
+ // + // Enable / Ready Logic + // + always @(posedge clk) + // + if (fsm_state == FSM_STATE_FINAL) begin + // + rdy_reg <= 1'b1; + // + end else if (fsm_state == FSM_STATE_IDLE) begin + // + if (rdy_reg && !ena) rdy_reg <= 1'b0; + // + end
+
+
+ // + // X, Y, N BRAM Interface + // + reg [OPERAND_ADDR_WIDTH:0] x_bram_addr_reg = bram_addr_zero; + reg [OPERAND_ADDR_WIDTH:0] y_bram_addr_reg = bram_addr_zero; + reg [OPERAND_ADDR_WIDTH:0] n_bram_addr_reg = bram_addr_zero; + + assign x_bram_addr = x_bram_addr_reg; + assign y_bram_addr = y_bram_addr_reg; + assign n_bram_addr = n_bram_addr_reg;
+
+
+ // + // Z BRAM Interface + // + reg [OPERAND_ADDR_WIDTH:0] z_bram_addr_reg = bram_addr_zero; + reg z_bram_wr_reg = 1'b0;
+ reg [ 31:0] z_bram_in_mux; + + assign z_bram_addr = z_bram_addr_reg; + assign z_bram_wr = z_bram_wr_reg;
+ assign z_bram_in = z_bram_in_mux;
+
+
+ //
+ // Handy Wires
+ //
+ wire [OPERAND_ADDR_WIDTH-1:0] operand_width_msb = operand_width[OPERAND_NUM_BITS-1:OPERAND_NUM_BITS-OPERAND_ADDR_WIDTH];
+
+ wire [OPERAND_ADDR_WIDTH :0] bram_addr_last = {operand_width_msb, 1'b1}; // +1
+
+
+ //
+ // Hardware Multiplier (X * Y)
+ //
+ reg [31: 0] multiplier_xy_carry_in;
+ wire [31: 0] multiplier_xy_out;
+ wire [31: 0] multiplier_xy_carry_out;
+
+ modexps6_adder64_carry32 dsp_multiplier_xy
+ (
+ .clk (clk),
+ .t (/*(z_bram_addr_reg < bram_addr_last) ? */z_bram_out/* : {32{1'b0}}*/),
+ .x (/*(z_bram_addr_reg < bram_addr_last) ? */x_bram_out/* : {32{1'b0}}*/),
+ .y (/*(z_bram_addr_reg < bram_addr_last) ? */y_bram_out/* : {32{1'b0}}*/),
+ .s (multiplier_xy_out),
+ .c_in (multiplier_xy_carry_in),
+ .c_out (multiplier_xy_carry_out)
+ );
+
+
+ //
+ // Hardware Multiplier (Magic)
+ //
+ wire [63: 0] multiplier_magic_out;
+ reg [31: 0] magic_value_reg;
+
+ multiplier_s6 dsp_multiplier_magic
+ (
+ .clk (clk),
+ .a (z_bram_out),
+ .b (n0_modinv),
+ .p (multiplier_magic_out)
+ );
+
+
+ //
+ // Hardware Multiplier (M * N)
+ //
+ reg [31: 0] multiplier_mn_carry_in;
+ wire [31: 0] multiplier_mn_out;
+ wire [31: 0] multiplier_mn_carry_out;
+
+ modexps6_adder64_carry32 dsp_multiplier_mn
+ (
+ .clk (clk),
+ .t (z_bram_out),
+ .x (magic_value_reg),
+ .y (/*(z_bram_addr_reg < bram_addr_last) ? */n_bram_out/* : {32{1'b0}}*/),
+ .s (multiplier_mn_out),
+ .c_in (multiplier_mn_carry_in),
+ .c_out (multiplier_mn_carry_out)
+ );
+
+
+ //
+ // Z BRAM Input Selector
+ //
+ always @(*)
+ //
+ case (fsm_state)
+
+ FSM_STATE_INIT:
+ //
+ z_bram_in_mux = {32{1'b0}};
+
+ FSM_STATE_MUL_XY_WRITE:
+ //
+ if (z_bram_addr_reg < bram_addr_last) z_bram_in_mux = multiplier_xy_out;
+ else z_bram_in_mux = multiplier_xy_carry_in;
+
+ FSM_STATE_MUL_MN_WRITE:
+ //
+ if (z_bram_addr_reg < bram_addr_last) z_bram_in_mux = multiplier_mn_out;
+ else z_bram_in_mux = multiplier_mn_carry_in + z_bram_out;
+
+ FSM_STATE_SHIFT:
+ //
+ z_bram_in_mux = z_bram_out;
+
+ default:
+ //
+ z_bram_in_mux = {32{1'bX}};
+
+ endcase
+
+
+ //
+ // Handy Functions
+ //
+ function [OPERAND_ADDR_WIDTH:0] bram_addr_next_or_zero;
+ input [OPERAND_ADDR_WIDTH:0] bram_addr;
+ begin
+ bram_addr_next_or_zero = (bram_addr < bram_addr_last) ? bram_addr + 1'b1 : bram_addr_zero;
+ end
+ endfunction
+
+ function [OPERAND_ADDR_WIDTH:0] bram_addr_next_or_last;
+ input [OPERAND_ADDR_WIDTH:0] bram_addr;
+ begin
+ bram_addr_next_or_last = (bram_addr < bram_addr_last) ? bram_addr + 1'b1 : bram_addr_last;
+ end
+ endfunction
+
+ function [OPERAND_ADDR_WIDTH:0] bram_addr_prev_or_zero;
+ input [OPERAND_ADDR_WIDTH:0] bram_addr;
+ begin
+ bram_addr_prev_or_zero = (bram_addr > bram_addr_zero) ? bram_addr - 1'b1 : bram_addr_zero;
+ end
+ endfunction
+
+
+ // + // Round Counter + // + reg [OPERAND_ADDR_WIDTH:0] round_count = round_count_zero; + wire [OPERAND_ADDR_WIDTH:0] round_count_last = {operand_width_msb, 1'b0}; + wire [OPERAND_ADDR_WIDTH:0] round_count_next = (round_count < round_count_last) ? round_count + 1'b1 : round_count_zero;
+
+
+ // + // Main Logic + // + always @(posedge clk) + // + case (fsm_state) +
+ FSM_STATE_INIT: begin
+ //
+ z_bram_wr_reg <= (z_bram_addr_reg < bram_addr_last) ? 1'b1 : 1'b0; + z_bram_addr_reg <= z_bram_wr_reg ? bram_addr_next_or_zero(z_bram_addr_reg) : bram_addr_zero;
+ //
+ end
+
+ FSM_STATE_MUL_XY_CALC: begin + // + if (z_bram_addr_reg == bram_addr_zero) begin + // + multiplier_xy_carry_in <= {32{1'b0}};
+ //
+ end + // + end
+
+ FSM_STATE_MUL_XY_REGISTER: begin
+ //
+ z_bram_wr_reg <= 1'b1;
+ //
+ end
+
+ FSM_STATE_MUL_XY_WRITE: begin + // + z_bram_wr_reg <= 1'b0; + z_bram_addr_reg <= bram_addr_next_or_zero(z_bram_addr_reg);
+ //
+ x_bram_addr_reg <= bram_addr_next_or_zero(x_bram_addr_reg); + // + multiplier_xy_carry_in <= multiplier_xy_carry_out; + // + end
+
+ FSM_STATE_MUL_MN_CALC: begin + // + if (z_bram_addr_reg == bram_addr_zero) begin + // + multiplier_mn_carry_in <= {32{1'b0}};
+ //
+ magic_value_reg <= multiplier_magic_out[31:0];
+ //
+ end + // + end
+
+ FSM_STATE_MUL_MN_REGISTER: begin
+ //
+ z_bram_wr_reg <= 1'b1;
+ //
+ end
+
+ FSM_STATE_MUL_MN_WRITE: begin + // + z_bram_wr_reg <= 1'b0; + z_bram_addr_reg <= bram_addr_next_or_last(z_bram_addr_reg);
+ //
+ n_bram_addr_reg <= bram_addr_next_or_zero(n_bram_addr_reg); + // + multiplier_mn_carry_in <= multiplier_mn_carry_out; + // + end
+
+ FSM_STATE_SHIFT: begin
+ //
+ if (z_bram_wr_reg == 1'b0) z_bram_wr_reg <= 1'b1;
+ else if (z_bram_addr_reg == bram_addr_zero) z_bram_wr_reg <= 1'b0;
+
+ z_bram_addr_reg <= bram_addr_prev_or_zero(z_bram_addr_reg);
+ //
+ end
+ + FSM_STATE_ROUND: begin + //
+ y_bram_addr_reg <= (round_count < round_count_last) ? bram_addr_next_or_zero(y_bram_addr_reg) : bram_addr_zero;
+ // + round_count <= round_count_next;
+ // + end + + endcase
+
+
+ // + // FSM Transition Logic + // + always @(posedge clk) + // + case (fsm_state) + // + FSM_STATE_IDLE: fsm_state <= (!rdy_reg && ena_trig) ? FSM_STATE_INIT : FSM_STATE_IDLE; + + FSM_STATE_INIT: fsm_state <= (z_bram_addr < bram_addr_last ) ? FSM_STATE_INIT : FSM_STATE_MUL_XY_CALC; + FSM_STATE_ROUND: fsm_state <= (round_count < round_count_last) ? FSM_STATE_MUL_XY_CALC : FSM_STATE_FINAL;
+
+ FSM_STATE_MUL_XY_CALC: fsm_state <= FSM_STATE_MUL_XY_PIPELINE;
+ FSM_STATE_MAGIC_CALC: fsm_state <= FSM_STATE_MAGIC_PIPELINE;
+ FSM_STATE_MUL_MN_CALC: fsm_state <= FSM_STATE_MUL_MN_PIPELINE;
+
+ FSM_STATE_MUL_XY_PIPELINE: fsm_state <= FSM_STATE_MUL_XY_REGISTER;
+ FSM_STATE_MAGIC_PIPELINE: fsm_state <= FSM_STATE_MAGIC_REGISTER;
+ FSM_STATE_MUL_MN_PIPELINE: fsm_state <= FSM_STATE_MUL_MN_REGISTER;
+
+ FSM_STATE_MUL_XY_REGISTER: fsm_state <= FSM_STATE_MUL_XY_WRITE;
+ FSM_STATE_MAGIC_REGISTER: fsm_state <= FSM_STATE_MUL_MN_CALC;
+ FSM_STATE_MUL_MN_REGISTER: fsm_state <= FSM_STATE_MUL_MN_WRITE;
+
+ FSM_STATE_MUL_XY_WRITE: fsm_state <= (z_bram_addr < bram_addr_last) ? FSM_STATE_MUL_XY_CALC : FSM_STATE_MAGIC_CALC;
+ FSM_STATE_MUL_MN_WRITE: fsm_state <= (z_bram_addr < bram_addr_last) ? FSM_STATE_MUL_MN_CALC : FSM_STATE_SHIFT;
+ FSM_STATE_SHIFT: fsm_state <= (z_bram_addr > bram_addr_zero) ? FSM_STATE_SHIFT : FSM_STATE_ROUND; + + FSM_STATE_FINAL: fsm_state <= FSM_STATE_IDLE; + + default: fsm_state <= FSM_STATE_IDLE; + + endcase
+
+
+endmodule
diff --git a/src/rtl/modexps6_top.v b/src/rtl/modexps6_top.v new file mode 100644 index 0000000..29845f8 --- /dev/null +++ b/src/rtl/modexps6_top.v @@ -0,0 +1,696 @@ +`timescale 1ns / 1ps
+
+module modexps6_top
+ (
+ clk,
+
+ init, ready, + next, valid, + + modulus_width, + exponent_width, +
+ fast_public_mode,
+ + bus_cs, bus_we, + bus_addr, bus_data_wr, bus_data_rd
+ );
+
+
+ //
+ // Parameters
+ //
+ parameter MAX_MODULUS_WIDTH = 1024;
+
+
+ // + // modexps6_clog2() + // + function integer modexps6_clog2; + input integer value;
+ integer ret; + begin + value = value - 1; + for (ret = 0; value > 0; ret = ret + 1) + value = value >> 1;
+ modexps6_clog2 = ret; + end + endfunction
+
+
+ //
+ // Locals
+ //
+ localparam OPERAND_ADDR_WIDTH = modexps6_clog2(MAX_MODULUS_WIDTH / 32);
+ localparam MODULUS_NUM_BITS = modexps6_clog2(MAX_MODULUS_WIDTH + 1);
+ localparam ADDR_WIDTH_TOTAL = OPERAND_ADDR_WIDTH + 2;
+
+ localparam [OPERAND_ADDR_WIDTH-1:0] bram_user_addr_zero = {OPERAND_ADDR_WIDTH{1'b0}};
+ localparam [OPERAND_ADDR_WIDTH :0] bram_core_addr_zero = {1'b0, {OPERAND_ADDR_WIDTH{1'b0}}};
+
+ localparam [ MODULUS_NUM_BITS:0] round_count_zero = {1'b0, {MODULUS_NUM_BITS{1'b0}}};
+
+
+ // + // Ports + // + input wire clk; + + input wire init; + output wire ready; + + input wire next; + output wire valid; + + input wire [MODULUS_NUM_BITS-1:0] modulus_width; + input wire [MODULUS_NUM_BITS-1:0] exponent_width; +
+ input wire fast_public_mode;
+ + input wire bus_cs; + input wire bus_we; + input wire [ADDR_WIDTH_TOTAL-1:0] bus_addr; + input wire [ 31:0] bus_data_wr; + output wire [ 31:0] bus_data_rd;
+
+
+ //
+ // User Memory
+ //
+ wire [OPERAND_ADDR_WIDTH-1:0] ro_modulus_bram_addr; + wire [ 31:0] ro_modulus_bram_out; + + reg [OPERAND_ADDR_WIDTH-1:0] ro_message_bram_addr = bram_user_addr_zero; + wire [ 31:0] ro_message_bram_out; + + reg [OPERAND_ADDR_WIDTH-1:0] ro_exponent_bram_addr = bram_user_addr_zero; + wire [ 31:0] ro_exponent_bram_out; + + reg [OPERAND_ADDR_WIDTH-1:0] rw_result_bram_addr = bram_user_addr_zero; + wire [ 31:0] rw_result_bram_out; + reg rw_result_bram_wr = 1'b0; + wire [ 31:0] rw_result_bram_in;
+
+ modexps6_buffer_user #
+ (
+ .OPERAND_ADDR_WIDTH (OPERAND_ADDR_WIDTH)
+ )
+ mem_user
+ (
+ .clk (clk),
+
+ .bus_cs (bus_cs),
+ .bus_we (bus_we),
+ .bus_addr (bus_addr),
+ .bus_data_wr (bus_data_wr),
+ .bus_data_rd (bus_data_rd),
+
+ .ro_modulus_bram_addr (ro_modulus_bram_addr),
+ .ro_modulus_bram_out (ro_modulus_bram_out),
+
+ .ro_message_bram_addr (ro_message_bram_addr),
+ .ro_message_bram_out (ro_message_bram_out),
+
+ .ro_exponent_bram_addr (ro_exponent_bram_addr),
+ .ro_exponent_bram_out (ro_exponent_bram_out),
+
+ .rw_result_bram_addr (rw_result_bram_addr),
+ .rw_result_bram_wr (rw_result_bram_wr),
+ .rw_result_bram_in (rw_result_bram_in)
+ );
+
+
+ //
+ // Core (Internal) Memory
+ //
+ wire [OPERAND_ADDR_WIDTH:0] rw_coeff_bram_addr; + wire rw_coeff_bram_wr; + wire [ 31:0] rw_coeff_bram_in; + wire [ 31:0] rw_coeff_bram_out;
+
+ reg [OPERAND_ADDR_WIDTH:0] rw_mm_bram_addr = bram_core_addr_zero; + reg rw_mm_bram_wr = 1'b0; + reg [ 31:0] rw_mm_bram_in; + wire [ 31:0] rw_mm_bram_out;
+
+ wire [OPERAND_ADDR_WIDTH:0] rw_nn_bram_addr; + wire rw_nn_bram_wr; + wire [ 31:0] rw_nn_bram_in;
+
+ reg [OPERAND_ADDR_WIDTH:0] rw_y_bram_addr = bram_core_addr_zero; + reg rw_y_bram_wr = 1'b0; + reg [ 31:0] rw_y_bram_in; + wire [ 31:0] rw_y_bram_out;
+
+ wire [OPERAND_ADDR_WIDTH:0] rw_r_bram_addr; + wire rw_r_bram_wr; + wire [ 31:0] rw_r_bram_in; + wire [ 31:0] rw_r_bram_out;
+
+ reg [OPERAND_ADDR_WIDTH:0] rw_t_bram_addr = bram_core_addr_zero; + reg rw_t_bram_wr = 1'b0; + reg [ 31:0] rw_t_bram_in; + wire [ 31:0] rw_t_bram_out;
+ + reg [OPERAND_ADDR_WIDTH:0] ro_coeff_bram_addr = bram_core_addr_zero; + wire [ 31:0] ro_coeff_bram_out;
+ + wire [OPERAND_ADDR_WIDTH:0] ro_mm_bram_addr; + wire [ 31:0] ro_mm_bram_out;
+ + wire [OPERAND_ADDR_WIDTH:0] ro_nn_bram_addr; + wire [ 31:0] ro_nn_bram_out; + + reg [OPERAND_ADDR_WIDTH:0] ro_r_bram_addr = bram_core_addr_zero; + wire [ 31:0] ro_r_bram_out; + + wire [OPERAND_ADDR_WIDTH:0] ro_t_bram_addr; + wire [ 31:0] ro_t_bram_out;
+
+ modexps6_buffer_core #
+ (
+ .OPERAND_ADDR_WIDTH (OPERAND_ADDR_WIDTH)
+ )
+ mem_core
+ (
+ .clk (clk),
+ + .rw_coeff_bram_addr (rw_coeff_bram_addr), + .rw_coeff_bram_wr (rw_coeff_bram_wr), + .rw_coeff_bram_in (rw_coeff_bram_in), + .rw_coeff_bram_out (rw_coeff_bram_out),
+ + .rw_mm_bram_addr (rw_mm_bram_addr), + .rw_mm_bram_wr (rw_mm_bram_wr), + .rw_mm_bram_in (rw_mm_bram_in), + .rw_mm_bram_out (rw_mm_bram_out),
+ + .rw_nn_bram_addr (rw_nn_bram_addr), + .rw_nn_bram_wr (rw_nn_bram_wr), + .rw_nn_bram_in (rw_nn_bram_in), +
+ .rw_y_bram_addr (rw_y_bram_addr), + .rw_y_bram_wr (rw_y_bram_wr), + .rw_y_bram_in (rw_y_bram_in), + .rw_y_bram_out (rw_y_bram_out), + + .rw_r_bram_addr (rw_r_bram_addr), + .rw_r_bram_wr (rw_r_bram_wr), + .rw_r_bram_in (rw_r_bram_in), + .rw_r_bram_out (rw_r_bram_out), + + .rw_t_bram_addr (rw_t_bram_addr), + .rw_t_bram_wr (rw_t_bram_wr), + .rw_t_bram_in (rw_t_bram_in), + .rw_t_bram_out (rw_t_bram_out), +
+ .ro_coeff_bram_addr (ro_coeff_bram_addr), + .ro_coeff_bram_out (ro_coeff_bram_out), + + .ro_mm_bram_addr (ro_mm_bram_addr), + .ro_mm_bram_out (ro_mm_bram_out), + + .ro_nn_bram_addr (ro_nn_bram_addr), + .ro_nn_bram_out (ro_nn_bram_out), + + .ro_r_bram_addr (ro_r_bram_addr), + .ro_r_bram_out (ro_r_bram_out), + + .ro_t_bram_addr (ro_t_bram_addr), + .ro_t_bram_out (ro_t_bram_out)
+ );
+
+
+ //
+ // Small 32-bit ModInv Core
+ //
+ wire modinv_ena;
+ wire modinv_rdy;
+
+ wire [31: 0] modinv_n0;
+ wire [31: 0] modinv_n0_negative = ~modinv_n0 + 1'b1;
+ wire [31: 0] modinv_n0_modinv;
+
+ modexps6_modinv32 core_modinv32
+ (
+ .clk (clk),
+
+ .ena (modinv_ena),
+ .rdy (modinv_rdy),
+
+ .n0 (modinv_n0_negative),
+ .n0_modinv (modinv_n0_modinv)
+ );
+
+
+ //
+ // Montgomery Coefficient Calculator
+ //
+ modexps6_montgomery_coeff # + ( + .MODULUS_NUM_BITS (MODULUS_NUM_BITS),
+ .OPERAND_ADDR_WIDTH (OPERAND_ADDR_WIDTH) + ) + core_montgomery_coeff + ( + .clk (clk), + + .ena (init), + .rdy (ready), + + .modulus_width (modulus_width), + + .coeff_bram_addr (rw_coeff_bram_addr), + .coeff_bram_wr (rw_coeff_bram_wr), + .coeff_bram_in (rw_coeff_bram_in), + .coeff_bram_out (rw_coeff_bram_out), +
+ .nn_bram_addr (rw_nn_bram_addr),
+ .nn_bram_wr (rw_nn_bram_wr),
+ .nn_bram_in (rw_nn_bram_in),
+ + .modulus_bram_addr (ro_modulus_bram_addr), + .modulus_bram_out (ro_modulus_bram_out),
+
+ .modinv_n0 (modinv_n0),
+ .modinv_ena (modinv_ena),
+ .modinv_rdy (modinv_rdy) + );
+
+
+ //
+ // Montgomery Multiplier
+ //
+ reg mul_ena = 1'b0;
+ wire mul_rdy;
+
+ modexps6_montgomery_multiplier #
+ (
+ .OPERAND_NUM_BITS (MODULUS_NUM_BITS),
+ .OPERAND_ADDR_WIDTH (OPERAND_ADDR_WIDTH)
+ )
+ core_montgomery_multiplier
+ (
+ .clk (clk),
+
+ .ena (mul_ena),
+ .rdy (mul_rdy),
+
+ .operand_width (modulus_width),
+
+ .x_bram_addr (ro_t_bram_addr),
+ .x_bram_out (ro_t_bram_out),
+
+ .y_bram_addr (ro_mm_bram_addr),
+ .y_bram_out (ro_mm_bram_out),
+
+ .n_bram_addr (ro_nn_bram_addr),
+ .n_bram_out (ro_nn_bram_out),
+
+ .z_bram_addr (rw_r_bram_addr),
+ .z_bram_wr (rw_r_bram_wr),
+ .z_bram_in (rw_r_bram_in),
+ .z_bram_out (rw_r_bram_out),
+
+ .n0_modinv (modinv_n0_modinv)
+ );
+
+
+ // + // FSM + // + localparam FSM_STATE_IDLE = 6'd0; + + localparam FSM_STATE_INIT_LOAD = 6'd11; + localparam FSM_STATE_INIT_WAIT = 6'd12; + localparam FSM_STATE_INIT_UNLOAD = 6'd13; +
+ localparam FSM_STATE_READ_EI = 6'd20;
+ + localparam FSM_STATE_ROUND_BEGIN = 6'd25; + + localparam FSM_STATE_MULTIPLY_LOAD = 6'd31; + localparam FSM_STATE_MULTIPLY_WAIT = 6'd32; + localparam FSM_STATE_MULTIPLY_UNLOAD = 6'd33; + + localparam FSM_STATE_SQUARE_LOAD = 6'd41; + localparam FSM_STATE_SQUARE_WAIT = 6'd42; + localparam FSM_STATE_SQUARE_UNLOAD = 6'd43; + + localparam FSM_STATE_ROUND_END = 6'd50; + + localparam FSM_STATE_FINAL = 6'd60; + + reg [ 5: 0] fsm_state = FSM_STATE_IDLE;
+
+
+ // + // Trigger + // + reg next_dly = 1'b0; + always @(posedge clk) next_dly <= next; + wire next_trig = (next == 1'b1) && (next_dly == 1'b0);
+
+
+ // + // Valid Register + // + reg valid_reg = 1'b0; + assign valid = valid_reg;
+
+
+ // + // Next/ Valid Logic + // + always @(posedge clk) + // + if (fsm_state == FSM_STATE_FINAL) begin + // + valid_reg <= 1'b1; + // + end else if (fsm_state == FSM_STATE_IDLE) begin + // + if (valid_reg && !next) valid_reg <= 1'b0; + // + end
+
+
+ //
+ // Exponent Bit Counter
+ //
+ reg [ 4: 0] ei_bit_count = 5'd0;
+ wire ei_bit = ro_exponent_bram_out[ei_bit_count];
+
+
+ // + // Round Counter + // + reg [MODULUS_NUM_BITS:0] round_count = round_count_zero; + wire [MODULUS_NUM_BITS:0] round_count_last = exponent_width - 1'b1; + wire [MODULUS_NUM_BITS:0] round_count_next = (round_count < round_count_last) ? round_count + 1'b1 : round_count_zero;
+
+
+ // + // Handy Wires + //
+ wire [OPERAND_ADDR_WIDTH-1:0] modulus_width_msb = modulus_width[MODULUS_NUM_BITS-1:MODULUS_NUM_BITS-OPERAND_ADDR_WIDTH];
+
+ wire [OPERAND_ADDR_WIDTH :0] bram_core_addr_last = {modulus_width_msb, 1'b0};
+
+ wire [OPERAND_ADDR_WIDTH :0] bram_user_addr_last_ext = bram_core_addr_last - 1'b1; + wire [OPERAND_ADDR_WIDTH-1:0] bram_user_addr_last = bram_user_addr_last_ext[OPERAND_ADDR_WIDTH-1:0];
+
+
+ // + // Handy Functions + // + function [OPERAND_ADDR_WIDTH:0] bram_core_addr_next_or_zero; + input [OPERAND_ADDR_WIDTH:0] bram_core_addr; + begin + bram_core_addr_next_or_zero = (bram_core_addr < bram_core_addr_last) ? bram_core_addr + 1'b1 : bram_core_addr_zero; + end + endfunction
+
+ function [OPERAND_ADDR_WIDTH-1:0] bram_user_addr_next_or_zero; + input [OPERAND_ADDR_WIDTH-1:0] bram_user_addr; + begin + bram_user_addr_next_or_zero = (bram_user_addr < bram_user_addr_last) ? bram_user_addr + 1'b1 : bram_user_addr_zero; + end + endfunction
+
+
+ //
+ // Result BRAM Input
+ //
+ assign rw_result_bram_in = ei_bit ? ro_r_bram_out : rw_t_bram_out;
+
+
+ //
+ // MM BRAM Input Selector
+ //
+ always @(*) + // + case (fsm_state) + + FSM_STATE_INIT_LOAD: + // + rw_mm_bram_in = (rw_mm_bram_addr < bram_core_addr_last) ? ro_message_bram_out : {32{1'b0}};
+
+ FSM_STATE_INIT_UNLOAD:
+ //
+ rw_mm_bram_in = ro_r_bram_out;
+
+ FSM_STATE_SQUARE_UNLOAD:
+ //
+ rw_mm_bram_in = ro_r_bram_out; + + default: + // + rw_mm_bram_in = {32{1'bX}}; + + endcase
+
+
+ //
+ // Y BRAM Input Selector
+ //
+ always @(*) + // + case (fsm_state) + + FSM_STATE_INIT_LOAD: + // + rw_y_bram_in = (rw_mm_bram_addr == bram_core_addr_zero) ? 32'h00000001 : 32'h00000000;
+
+ FSM_STATE_MULTIPLY_UNLOAD:
+ //
+ rw_y_bram_in = ei_bit ? ro_r_bram_out : rw_t_bram_out; // RW! + + default: + // + rw_y_bram_in = {32{1'bX}}; + + endcase
+
+
+ //
+ // T BRAM Input Selector
+ //
+ always @(*) + // + case (fsm_state) + + FSM_STATE_INIT_LOAD: + // + rw_t_bram_in = ro_coeff_bram_out;
+
+ FSM_STATE_MULTIPLY_LOAD:
+ //
+ rw_t_bram_in = rw_y_bram_out;
+
+ FSM_STATE_SQUARE_LOAD:
+ //
+ rw_t_bram_in = rw_mm_bram_out; + + default: + // + rw_t_bram_in = {32{1'bX}}; + + endcase
+
+
+ // + // Main Logic + // + always @(posedge clk) + // + case (fsm_state) + + FSM_STATE_INIT_LOAD: begin + //
+ rw_mm_bram_wr <= (rw_mm_bram_addr < bram_core_addr_last) ? 1'b1 : 1'b0;
+ rw_y_bram_wr <= (rw_mm_bram_addr < bram_core_addr_last) ? 1'b1 : 1'b0;
+ rw_t_bram_wr <= (rw_mm_bram_addr < bram_core_addr_last) ? 1'b1 : 1'b0;
+ //
+ rw_mm_bram_addr <= rw_mm_bram_wr ? bram_core_addr_next_or_zero(rw_mm_bram_addr) : bram_core_addr_zero;
+ rw_y_bram_addr <= rw_mm_bram_wr ? bram_core_addr_next_or_zero(rw_mm_bram_addr) : bram_core_addr_zero;
+ rw_t_bram_addr <= rw_mm_bram_wr ? bram_core_addr_next_or_zero(rw_mm_bram_addr) : bram_core_addr_zero;
+ //
+ if (ro_coeff_bram_addr > bram_core_addr_zero) ro_coeff_bram_addr <= bram_core_addr_next_or_zero(ro_coeff_bram_addr);
+ else ro_coeff_bram_addr <= rw_mm_bram_wr ? bram_core_addr_zero : bram_core_addr_next_or_zero(ro_coeff_bram_addr);
+ //
+ if (ro_message_bram_addr > bram_user_addr_zero) ro_message_bram_addr <= bram_user_addr_next_or_zero(ro_message_bram_addr);
+ else ro_message_bram_addr <= rw_mm_bram_wr ? bram_user_addr_zero : bram_user_addr_next_or_zero(ro_message_bram_addr);
+ //
+ end
+
+ FSM_STATE_INIT_WAIT: begin + // + if (mul_ena) mul_ena <= mul_rdy ? 1'b0 : 1'b1; + else mul_ena <= 1'b1; + // + end
+
+ FSM_STATE_INIT_UNLOAD: begin + //
+ rw_mm_bram_wr <= (rw_mm_bram_addr < bram_core_addr_last) ? 1'b1 : 1'b0;
+ //
+ rw_mm_bram_addr <= rw_mm_bram_wr ? bram_core_addr_next_or_zero(rw_mm_bram_addr) : bram_core_addr_zero;
+ //
+ if (ro_r_bram_addr > bram_core_addr_zero) ro_r_bram_addr <= bram_core_addr_next_or_zero(ro_r_bram_addr);
+ else ro_r_bram_addr <= rw_mm_bram_wr ? bram_core_addr_zero : bram_core_addr_next_or_zero(ro_r_bram_addr);
+ //
+ end
+
+ FSM_STATE_MULTIPLY_LOAD: begin
+ //
+ rw_t_bram_wr <= (rw_t_bram_addr < bram_core_addr_last) ? 1'b1 : 1'b0;
+ //
+ rw_t_bram_addr <= rw_t_bram_wr ? bram_core_addr_next_or_zero(rw_t_bram_addr) : bram_core_addr_zero;
+ //
+ if (rw_y_bram_addr > bram_core_addr_zero) rw_y_bram_addr <= bram_core_addr_next_or_zero(rw_y_bram_addr);
+ else rw_y_bram_addr <= rw_t_bram_wr ? bram_core_addr_zero : bram_core_addr_next_or_zero(rw_y_bram_addr);
+ //
+ end +
+ FSM_STATE_MULTIPLY_WAIT: begin
+ // + if (mul_ena) mul_ena <= mul_rdy ? 1'b0 : 1'b1; + else mul_ena <= 1'b1;
+ //
+ end
+
+ FSM_STATE_MULTIPLY_UNLOAD: begin
+ //
+ rw_y_bram_wr <= (rw_y_bram_addr < bram_core_addr_last) ? 1'b1 : 1'b0;
+ //
+ rw_y_bram_addr <= rw_y_bram_wr ? bram_core_addr_next_or_zero(rw_y_bram_addr) : bram_core_addr_zero;
+ //
+ if (ei_bit) begin
+ //
+ if (ro_r_bram_addr > bram_core_addr_zero) ro_r_bram_addr <= bram_core_addr_next_or_zero(ro_r_bram_addr);
+ else ro_r_bram_addr <= rw_y_bram_wr ? bram_core_addr_zero : bram_core_addr_next_or_zero(ro_r_bram_addr);
+ //
+ end else begin
+ //
+ if (rw_t_bram_addr > bram_core_addr_zero) rw_t_bram_addr <= bram_core_addr_next_or_zero(rw_t_bram_addr);
+ else rw_t_bram_addr <= rw_y_bram_wr ? bram_core_addr_zero : bram_core_addr_next_or_zero(rw_t_bram_addr);
+ //
+ end
+ //
+ if (round_count == round_count_last) begin
+ //
+ if (rw_result_bram_addr == bram_user_addr_zero) begin
+ //
+ if (rw_y_bram_wr) begin
+ //
+ rw_result_bram_wr <= (rw_y_bram_addr > bram_core_addr_zero) ? 1'b0 : 1'b1;
+ rw_result_bram_addr <= (rw_y_bram_addr > bram_core_addr_zero) ? bram_user_addr_zero : bram_user_addr_next_or_zero(rw_result_bram_addr);
+ //
+ end else begin
+ //
+ rw_result_bram_wr <= 1'b1;
+ rw_result_bram_addr <= bram_user_addr_zero;
+ //
+ end
+ //
+ end else begin
+ //
+ rw_result_bram_wr <= (rw_result_bram_addr < bram_user_addr_last) ? 1'b1 : 1'b0;
+ rw_result_bram_addr <= bram_user_addr_next_or_zero(rw_result_bram_addr);
+ //
+ end
+ //
+ end
+ //
+ end
+
+ FSM_STATE_SQUARE_LOAD: begin
+ //
+ rw_t_bram_wr <= (rw_t_bram_addr < bram_core_addr_last) ? 1'b1 : 1'b0;
+ //
+ rw_t_bram_addr <= rw_t_bram_wr ? bram_core_addr_next_or_zero(rw_t_bram_addr) : bram_core_addr_zero;
+ //
+ if (rw_mm_bram_addr > bram_core_addr_zero) rw_mm_bram_addr <= bram_core_addr_next_or_zero(rw_mm_bram_addr);
+ else rw_mm_bram_addr <= rw_t_bram_wr ? bram_core_addr_zero : bram_core_addr_next_or_zero(rw_mm_bram_addr);
+ //
+ end
+
+ FSM_STATE_SQUARE_WAIT: begin
+ //
+ if (mul_ena) mul_ena <= mul_rdy ? 1'b0 : 1'b1; + else mul_ena <= 1'b1;
+ //
+ end
+
+ FSM_STATE_SQUARE_UNLOAD: begin
+ //
+ rw_mm_bram_wr <= (rw_mm_bram_addr < bram_core_addr_last) ? 1'b1 : 1'b0;
+ //
+ rw_mm_bram_addr <= rw_mm_bram_wr ? bram_core_addr_next_or_zero(rw_mm_bram_addr) : bram_core_addr_zero;
+ //
+ if (ro_r_bram_addr > bram_core_addr_zero) ro_r_bram_addr <= bram_core_addr_next_or_zero(ro_r_bram_addr);
+ else ro_r_bram_addr <= rw_mm_bram_wr ? bram_core_addr_zero : bram_core_addr_next_or_zero(ro_r_bram_addr);
+ //
+ end
+
+ FSM_STATE_ROUND_END: begin
+ //
+ round_count <= round_count_next;
+ //
+ if (round_count < round_count_last) begin
+ //
+ ei_bit_count <= ei_bit_count + 1'b1;
+ //
+ if (ei_bit_count == 5'd31)
+ //
+ ro_exponent_bram_addr <= bram_user_addr_next_or_zero(ro_exponent_bram_addr);
+ //
+ end else begin
+ //
+ ei_bit_count <= 5'd0;
+ //
+ ro_exponent_bram_addr <= bram_user_addr_zero;
+ //
+ end
+ //
+ end
+ + endcase
+
+
+ // + // FSM Transition Logic + // + always @(posedge clk) + // + case (fsm_state) + + FSM_STATE_IDLE: fsm_state <= (!valid_reg && next_trig) ? FSM_STATE_INIT_LOAD : FSM_STATE_IDLE; + + FSM_STATE_INIT_LOAD: fsm_state <= (rw_y_bram_addr < bram_core_addr_last) ? FSM_STATE_INIT_LOAD : FSM_STATE_INIT_WAIT; + FSM_STATE_INIT_WAIT: fsm_state <= mul_rdy ? FSM_STATE_INIT_UNLOAD : FSM_STATE_INIT_WAIT; + FSM_STATE_INIT_UNLOAD: fsm_state <= (rw_mm_bram_addr < bram_core_addr_last) ? FSM_STATE_INIT_UNLOAD : FSM_STATE_READ_EI; +
+ FSM_STATE_READ_EI: fsm_state <= FSM_STATE_ROUND_BEGIN;
+ + FSM_STATE_ROUND_BEGIN: fsm_state <= (!ei_bit && fast_public_mode && (round_count < round_count_last)) ? FSM_STATE_SQUARE_LOAD : FSM_STATE_MULTIPLY_LOAD; + + FSM_STATE_MULTIPLY_LOAD: fsm_state <= (rw_t_bram_addr < bram_core_addr_last) ? FSM_STATE_MULTIPLY_LOAD : FSM_STATE_MULTIPLY_WAIT; + FSM_STATE_MULTIPLY_WAIT: fsm_state <= mul_rdy ? FSM_STATE_MULTIPLY_UNLOAD : FSM_STATE_MULTIPLY_WAIT; + FSM_STATE_MULTIPLY_UNLOAD: fsm_state <= (rw_y_bram_addr < bram_core_addr_last) ? FSM_STATE_MULTIPLY_UNLOAD : FSM_STATE_SQUARE_LOAD; + + FSM_STATE_SQUARE_LOAD: fsm_state <= (rw_t_bram_addr < bram_core_addr_last) ? FSM_STATE_SQUARE_LOAD : FSM_STATE_SQUARE_WAIT; + FSM_STATE_SQUARE_WAIT: fsm_state <= mul_rdy ? FSM_STATE_SQUARE_UNLOAD : FSM_STATE_SQUARE_WAIT; + FSM_STATE_SQUARE_UNLOAD: fsm_state <= (rw_mm_bram_addr < bram_core_addr_last) ? FSM_STATE_SQUARE_UNLOAD : FSM_STATE_ROUND_END; + + FSM_STATE_ROUND_END: fsm_state <= (round_count < round_count_last) ? FSM_STATE_READ_EI : FSM_STATE_FINAL; + + FSM_STATE_FINAL: fsm_state <= FSM_STATE_IDLE; + + default: fsm_state <= FSM_STATE_IDLE; + + endcase
+
+
+endmodule
diff --git a/src/rtl/modexps6_wrapper.v b/src/rtl/modexps6_wrapper.v new file mode 100644 index 0000000..3fad0f9 --- /dev/null +++ b/src/rtl/modexps6_wrapper.v @@ -0,0 +1,187 @@ +module modexps6_wrapper
+ ( + clk, rst, + cs, we,
+ address, write_data, read_data + );
+
+
+ //
+ // Ports
+ // + input wire clk; + input wire rst; + + input wire cs; + input wire we; + + input wire [ 9: 0] address; + input wire [31: 0] write_data; + output wire [31: 0] read_data;
+
+
+ //
+ // Address Decoder
+ //
+ localparam ADDR_MSB_REGS = 1'b0;
+ localparam ADDR_MSB_CORE = 1'b1;
+ wire address_msb = address[9];
+ wire [ 8: 0] address_lsb = address[8:0];
+
+
+ //
+ // Output Mux
+ //
+ wire [31: 0] read_data_regs;
+ wire [31: 0] read_data_core;
+
+
+ // + // Registers + // + localparam ADDR_NAME0 = 9'h000; + localparam ADDR_NAME1 = 9'h001; + localparam ADDR_VERSION = 9'h002; + + localparam ADDR_CONTROL = 9'h008; // {next, init} + localparam ADDR_STATUS = 9'h009; // {valid, ready} + localparam ADDR_MODE = 9'h010; // 0 = slow secure, 1 = fast unsafe (public) + localparam ADDR_MODULUS_BITS = 9'h011; //
+ localparam ADDR_EXPONENT_BITS = 9'h012; //
+ localparam ADDR_GPIO_REG = 9'h020; // + + localparam CONTROL_INIT_BIT = 0; + localparam CONTROL_NEXT_BIT = 1; + + localparam STATUS_READY_BIT = 0; + localparam STATUS_VALID_BIT = 1; + + localparam CORE_NAME0 = 32'h6D6F6465; // "mode" + localparam CORE_NAME1 = 32'h78707336; // "xps6" + localparam CORE_VERSION = 32'h302E3130; // "0.10" + + + // + // Registers + // + reg [ 1: 0] reg_control; + reg reg_mode; + reg [12: 0] reg_modulus_width;
+ reg [12: 0] reg_exponent_width;
+ reg [31: 0] reg_gpio;
+
+
+ //
+ // Wires
+ //
+ wire [ 1: 0] reg_status;
+
+
+ //
+ // ModExpS6
+ //
+ modexps6_top #
+ (
+ .MAX_MODULUS_WIDTH (4096)
+ )
+ modexps6_core
+ (
+ .clk (clk),
+
+ .init (reg_control[CONTROL_INIT_BIT]),
+ .ready (reg_status[STATUS_READY_BIT]), + .next (reg_control[CONTROL_NEXT_BIT]),
+ .valid (reg_status[STATUS_VALID_BIT]), + + .modulus_width (reg_modulus_width), + .exponent_width (reg_exponent_width), +
+ .fast_public_mode (reg_mode),
+ + .bus_cs (cs && (address_msb == ADDR_MSB_CORE)),
+ .bus_we (we), + .bus_addr (address_lsb),
+ .bus_data_wr (write_data),
+ .bus_data_rd (read_data_core)
+ );
+
+
+ // + // Read Latch + // + reg [31: 0] tmp_read_data; +
+ + // + // Read/Write Interface + // + always @(posedge clk) + // + if (rst) begin + // + reg_control <= 2'b00; + reg_mode <= 1'b0; + reg_modulus_width <= 13'd1024; + reg_exponent_width <= 13'd1024; + // + end else if (cs && (address_msb == ADDR_MSB_REGS)) begin + // + if (we) begin + // + // Write Handler + // + case (address_lsb)
+ // + ADDR_CONTROL: reg_control <= write_data[ 1: 0]; + ADDR_MODE: reg_mode <= write_data[0]; + ADDR_MODULUS_BITS: reg_modulus_width <= write_data[12: 0]; + ADDR_EXPONENT_BITS: reg_exponent_width <= write_data[12: 0];
+ ADDR_GPIO_REG: reg_gpio <= write_data;
+ // + endcase + // + end else begin + // + // Read Handler + // + case (address) + // + ADDR_NAME0: tmp_read_data <= CORE_NAME0; + ADDR_NAME1: tmp_read_data <= CORE_NAME1; + ADDR_VERSION: tmp_read_data <= CORE_VERSION; + ADDR_CONTROL: tmp_read_data <= {{30{1'b0}}, reg_control}; + ADDR_STATUS: tmp_read_data <= {{30{1'b0}}, reg_status}; + ADDR_MODE: tmp_read_data <= {{31{1'b0}}, reg_mode}; + ADDR_MODULUS_BITS: tmp_read_data <= {{19{1'b0}}, reg_modulus_width};
+ ADDR_EXPONENT_BITS: tmp_read_data <= {{19{1'b0}}, reg_exponent_width};
+ ADDR_GPIO_REG: tmp_read_data <= reg_gpio; + // + default: tmp_read_data <= 32'h00000000; + // + endcase + // + end + // + end
+
+
+ //
+ // Register / Core Memory Selector
+ //
+ reg address_msb_last;
+ always @(posedge clk) address_msb_last = address_msb;
+
+ reg [31: 0] read_data_mux;
+ assign read_data = read_data_mux;
+
+ always @(*)
+ //
+ case (address_msb_last)
+ //
+ ADDR_MSB_REGS: read_data_mux = tmp_read_data;
+ ADDR_MSB_CORE: read_data_mux = read_data_core;
+ //
+ endcase
+
+ +endmodule diff --git a/src/rtl/ram_1rw_1ro_readfirst.v b/src/rtl/ram_1rw_1ro_readfirst.v new file mode 100644 index 0000000..7ba11ea --- /dev/null +++ b/src/rtl/ram_1rw_1ro_readfirst.v @@ -0,0 +1,69 @@ +`timescale 1ns / 1ps
+
+module ram_1rw_1ro_readfirst
+ (
+ clk, + a_addr, a_wr, a_in, a_out, + b_addr, b_out
+ );
+
+
+ // + // Parameters + // + parameter MEM_WIDTH = 32; + parameter MEM_ADDR_BITS = 8;
+
+
+ // + // Ports + // + input wire clk; + + input wire [MEM_ADDR_BITS-1:0] a_addr; + input wire a_wr; + input wire [MEM_WIDTH-1:0] a_in; + output wire [MEM_WIDTH-1:0] a_out; + + input wire [MEM_ADDR_BITS-1:0] b_addr; + output wire [MEM_WIDTH-1:0] b_out; + + + // + // BRAM + // + (* RAM_STYLE="BLOCK" *) + reg [MEM_WIDTH-1:0] bram[0:(2**MEM_ADDR_BITS)-1]; + + + // + // Output Registers + // + reg [MEM_WIDTH-1:0] bram_reg_a; + reg [MEM_WIDTH-1:0] bram_reg_b;
+ + assign a_out = bram_reg_a; + assign b_out = bram_reg_b; + + + // + // Read-Write Port A + // + always @(posedge clk) begin + // + bram_reg_a <= bram[a_addr];
+ // + if (a_wr) bram[a_addr] <= a_in; + // + end + + + // + // Read-Only Port B + // + always @(posedge clk) + // + bram_reg_b <= bram[b_addr];
+
+
+endmodule
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