diff options
Diffstat (limited to 'src/rtl/ipcore/tmp/_xmsgs/netgen.xmsgs')
| -rw-r--r-- | src/rtl/ipcore/tmp/_xmsgs/netgen.xmsgs | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/rtl/ipcore/tmp/_xmsgs/netgen.xmsgs b/src/rtl/ipcore/tmp/_xmsgs/netgen.xmsgs new file mode 100644 index 0000000..00fafd8 --- /dev/null +++ b/src/rtl/ipcore/tmp/_xmsgs/netgen.xmsgs @@ -0,0 +1,12 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages> +<msg type="info" file="NetListWriters" num="633" delta="old" >The generated Verilog netlist contains Xilinx <arg fmt="%s" index="1">UNISIM</arg> simulation primitives and has to be used with <arg fmt="%s" index="2">UNISIM</arg> simulation library for correct compilation and simulation.
+</msg>
+ +</messages> +
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