1 files changed, 65 insertions, 0 deletions
diff --git a/src/rtl/ipcore/multiplier_s6.veo b/src/rtl/ipcore/multiplier_s6.veo
new file mode 100644
index 0000000..fede3ea
--- /dev/null
+++ b/src/rtl/ipcore/multiplier_s6.veo
@@ -0,0 +1,65 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
+*                                                                              *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
+*                                                                              *
+*     (c) Copyright 1995-2015 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+
+/*******************************************************************************
+*     Generated from core with identifier: xilinx.com:ip:mult_gen:11.2         *
+*                                                                              *
+*     Multiplication is a fundamental DSP operation.  This core allows         *
+*     parallel and constant-coefficient multipliers to be generated.  The      *
+*     user can specify if dedicated hardware multipliers, slice logic or a     *
+*     combination of resources should be utilized.                             *
+*******************************************************************************/
+
+// Interfaces:
+//    a_intf
+//    clk_intf
+//    sclr_intf
+//    ce_intf
+//    b_intf
+//    zero_detect_intf
+//    p_intf
+//    pcasc_intf
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+multiplier_s6 your_instance_name (
+  .clk(clk), // input clk
+  .a(a), // input [31 : 0] a
+  .b(b), // input [31 : 0] b
+  .p(p) // output [63 : 0] p
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file multiplier_s6.v when simulating
+// the core, multiplier_s6. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+