core/math/modexpng - "Next-generation" modular exponentiation using specialized DSP slices present in Artix-7 FPGA

Age	Commit message (Expand)	Author
2020-01-30	Accomodate the changes to DSP slice wrappers.	Pavel V. Shatov (Meister)
2020-01-21	Refactored modular reductor module.	Pavel V. Shatov (Meister)
2019-11-20	Small change to the reductor module to try to get past 180 MHz. Previously BRAM	Pavel V. Shatov (Meister)
2019-11-18	Refactored reductor module.	Pavel V. Shatov (Meister)
2019-10-23	Added missing copyright headers.	Pavel V. Shatov (Meister)
2019-10-21	Further work:	Pavel V. Shatov (Meister)
2019-10-21	Entire CRT signature algorithm works by now.	Pavel V. Shatov (Meister)
2019-10-03	Added more micro-operations, also added "general worker" module. The worker i...	Pavel V. Shatov (Meister)
2019-10-03	Reworked storage architecture (moved I/O memory to a separate module, since t...	Pavel V. Shatov (Meister)
2019-10-01	Redesigned core architecture, unified bank structure. All storage blocks now	Pavel V. Shatov (Meister)
2019-10-01	Major rewrite (different core hierarchy, buses, wrappers, etc).	Pavel V. Shatov (Meister)