Redesigned core architecture, unified bank structure. All storage blocks now

have eight 4kbit entries and occupy one 36K BRAM tile.

1 files changed, 25 insertions, 11 deletions

diff --git a/rtl/modexpng_reductor.v b/rtl/modexpng_reductor.v
index 0f5e461..aafb38c 100644
--- a/rtl/modexpng_reductor.v
+++ b/rtl/modexpng_reductor.v
@@ -17,8 +17,9 @@ module modexpng_reductor
     //
     // Headers
     //
+    `include "modexpng_parameters.vh"
     //`include "../rtl_1/modexpng_mmm_fsm.vh"
-    `include "../rtl_1/modexpng_parameters_old.vh"
+    
     //`include "../rtl_1/modexpng_parameters_x8.vh"
 
 
@@ -39,12 +40,12 @@ module modexpng_reductor
     input  [     7:0] rd_narrow_xy_addr;
     input  [     1:0] rd_narrow_xy_bank;
     */
-    input  [     1:0] rd_wide_xy_bank_aux;
+    input  [    BANK_ADDR_W -1:0] rd_wide_xy_bank_aux;
     input  [     7:0] rd_wide_xy_addr_aux;
     input  [    17:0] rd_wide_x_dout_aux;
     input  [    17:0] rd_wide_y_dout_aux;
     //
-    input  [     1:0] rcmb_final_xy_bank;
+    input  [     BANK_ADDR_W -1:0] rcmb_final_xy_bank;
     input  [     7:0] rcmb_final_xy_addr;
     input  [    17:0] rcmb_final_x_dout;
     input  [    17:0] rcmb_final_y_dout;
@@ -60,7 +61,7 @@ module modexpng_reductor
     // Ready
     //
     reg rdy_reg  = 1'b1;
-    reg busy_now = 1'b0;
+    wire busy_now;
 
     assign rdy = rdy_reg;
     
@@ -81,9 +82,9 @@ module modexpng_reductor
     reg rcmb_xy_valid_dly2 = 1'b0;
     reg rcmb_xy_valid_dly3 = 1'b0;
 
-    reg [2:0] rcmb_xy_bank_dly1;
-    reg [2:0] rcmb_xy_bank_dly2;
-    reg [2:0] rcmb_xy_bank_dly3;
+    reg [BANK_ADDR_W -1:0] rcmb_xy_bank_dly1;
+    reg [BANK_ADDR_W -1:0] rcmb_xy_bank_dly2;
+    reg [BANK_ADDR_W -1:0] rcmb_xy_bank_dly3;
 
     reg [7:0] rcmb_xy_addr_dly1;
     reg [7:0] rcmb_xy_addr_dly2;
@@ -236,7 +237,7 @@ module modexpng_reductor
             //
             clear_rdct;
             //
-            if (busy_now && rcmb_xy_valid_dly3)
+            if (rcmb_xy_valid_dly3)
                 //
                 case (rcmb_xy_bank_dly3)
                                     
@@ -258,12 +259,25 @@ module modexpng_reductor
     //
     // Busy
     //
+    reg       busy_next = 1'b0;
+    reg [2:0] busy_now_shreg = {3{1'b0}};
+
+    assign busy_now = busy_now_shreg[2];
+    
+    always @(posedge clk)
+        //
+        if (rst) busy_now_shreg <= {3{1'b0}};
+        else begin
+            if (rdy && ena) busy_now_shreg <= {3{1'b1}};
+            else            busy_now_shreg <= {busy_now_shreg[1:0], busy_next};
+        end
+    
     always @(posedge clk)
         //
-        if (rst) busy_now <= 1'b0;
+        if (rst) busy_next <= 1'b0;
         else begin
-            if (rdy && ena) busy_now <= 1'b1;
-            //if (!rdy && !busy_now) rdy <= 1'b1;
+            if (rdy && ena) busy_next <= 1'b1;
+            if (!rdy && rcmb_xy_valid_dly3 && (rcmb_xy_bank_dly3 == BANK_RCMB_EXT)) busy_next <= 1'b0;    
         end